Semiconductor memory device

Abstract

A semiconductor memory device includes a memory cell structure including a plurality of memory cells configured by a plurality of semiconductor patterns, a plurality of word lines, a plurality of bit lines, and a plurality of information storage elements, a peripheral circuit structure stacked in a vertical direction with respect to the memory cell structure and including a plurality of peripheral circuit transistors configuring a sense amplifier, and a first multiplexer and a second multiplexer each connected to the sense amplifier, and a bonding structure between the memory cell structure and the peripheral circuit structure to bond the memory cell structure to the peripheral circuit structure. The first multiplexer is electrically connected to at least two of the plurality of bit lines, and the second multiplexer is electrically connected to at least two other bit lines among the plurality of bit lines.

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