Memory devices and method of performing a refresh operation with a memory device

Abstract

A memory device includes an address arithmetic circuit configured to generate a redundancy switching signal when a normal word line connected to a normal cell is designated as a target word line and a redundancy word line connected to a redundancy cell is designated as an adjacent word line so that a smart refresh operation is performed. The memory device also includes a redundancy control circuit configured to generate a redundancy activation signal based on the redundancy switching signal.

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