Operating methods for non-volatile memory arrays and non-volatile memory cells to improve write or erase efficiency.

Abstract

A method for operating a non-volatile memory array and a non-volatile memory cell, wherein the non-volatile memory cell is coupled to a word line, a bit line, and a common-source line, and the non-volatile memory cell includes an N-type field-effect transistor having a threshold voltage. During write or erase operations, a bit voltage, a word voltage, and a common-source voltage are applied to the bit line, the word line, and the common-source line, respectively. During the write operation, the bit voltage is equal to a high voltage, the word voltage gradually increases in response to the gradually increasing threshold voltage, and the common-source voltage gradually decreases in response to the gradually increasing threshold voltage. During the erase operation, the bit voltage is equal to a high voltage, the word voltage gradually decreases in response to the gradually decreasing threshold voltage, and the common-source voltage is equal to ground voltage.

Description

[Technical Field]

[0001] This invention relates to a method of operating a memory, and particularly to a method of operating a non-volatile memory array and a non-volatile memory cell. [Previous Technology]

[0002] Note that Complementary Metal Oxide Semiconductor (CMOS) process technology has become a common manufacturing method for application-specific integrated circuits (ASICs). In today's world of advanced computer information products, Electrically Erasable Programmable Read Only Memory (EEPROM) is widely used in electronic products because it possesses the non-volatile memory function of electrically writing and erasing data, and the data is not lost after the power is turned off.

[0003] Non-volatile memory systems are programmable, used to store charge to change the gate voltage of the memory's transistor, or to leave no charge stored, thus retaining the original gate voltage of the memory's transistor. An erase operation removes all charge stored in the non-volatile memory, returning all non-volatile memory to the gate voltage of the original memory's transistor. During write or erase operations, the critical voltage of the non-volatile memory's field-effect transistor changes. This is because the amount of charge on the gate of the field-effect transistor changes. When the critical voltage changes, the voltage of the word line remains constant, which increases the time of the write or erase operation, reducing write or erase efficiency.

[0004] Therefore, the present invention addresses the above-mentioned problems by proposing an operation method for a non-volatile memory array and a non-volatile memory cell, thereby solving the problems arising from conventional methods. [Summary of the Invention]

[0005] The present invention provides an operation method for a non-volatile memory array and a non-volatile memory cell, which shortens the time of write operation or erase operation to improve write efficiency or erase efficiency.

[0006] In one embodiment of the present invention, an operation method for a non-volatile memory array is provided. The non-volatile memory array includes multiple parallel common-source lines, multiple parallel word lines, multiple parallel bit lines, and multiple sub-memory arrays. The common-source lines include a first common-source line, the word lines are parallel to the common-source lines, the word lines include a first word line, and the bit lines are perpendicular to the word lines. The bit lines include a first bit line, a second bit line, a third bit line, and a fourth bit line. Each sub-memory array is coupled to one common-source line, one word line, and four bit lines. Each sub-memory array includes a first non-volatile memory cell, a second non-volatile memory cell, a third non-volatile memory cell, and a fourth non-volatile memory cell. A first non-volatile memory cell is coupled to a first word line, a second bit line, and a first common-source line; a second non-volatile memory cell is coupled to a first word line, a second bit line, and a first common-source line; a third non-volatile memory cell is coupled to a first word line, a third bit line, and a first common-source line; and a fourth non-volatile memory cell is coupled to a first word line, a fourth bit line, and a first common-source line. Each of the first, second, third, and fourth non-volatile memory cells contains an N-type field-effect transistor. Each of the first, second, third, or fourth non-volatile memory cells serves as a single operable memory cell. The operating method includes the following steps: applying a ground voltage to the base of the N-type field-effect transistor of the operable memory cell; and, during a write or erase operation of the operable memory cell, applying a bit voltage, a first word voltage, and a first common-source voltage to the bit line, first word line, and first common-source line coupled to the operable memory cell, respectively. The N-type field-effect transistor of the operable memory cell has a threshold voltage. During the write operation, the bit voltage is equal to the high voltage, the first word voltage increases progressively in response to the progressively increasing threshold voltage, and the first common-source voltage decreases progressively in response to the progressively increasing threshold voltage. During the erase operation, the bit voltage is equal to the high voltage, the first word voltage decreases progressively in response to the progressively decreasing threshold voltage, the first common-source voltage is equal to the ground voltage, and the high voltage is equal to the drain-to-source breakdown voltage of the N-type field-effect transistor of the operable memory cell minus the threshold voltage.

[0007] In one embodiment of the present invention, during the write operation, the first character voltage is a low voltage, a medium voltage, or a high voltage, and the first common source voltage is a medium voltage, a low voltage, or a ground voltage, wherein the high voltage is greater than the medium voltage, the medium voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

[0008] In one embodiment of the present invention, during the erasure operation, the first character voltage is a low voltage or a ground voltage, the high voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

[0009] In one embodiment of the present invention, when the operable memory cell is not performing a write operation or an erase operation, the bit lines coupled to the operable memory cell are electrically floating, and a second word voltage and a second common source voltage are respectively applied to the first word line and the first common source line. The second word voltage is a ground voltage or a low voltage, the second common source voltage is a medium voltage, the high voltage is greater than the medium voltage, the medium voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

[0010] In one embodiment of the present invention, the base is implemented as a P-type well region, a P-type semiconductor substrate or a P-type epitaxial layer.

[0011] In one embodiment of the present invention, an operation method for a non-volatile memory cell is provided. The non-volatile memory cell is coupled to a word line, a bit line, and a common source line. The non-volatile memory cell includes an N-type field-effect transistor. The operation method includes the following steps: applying a ground voltage to the base of the N-type field-effect transistor of the non-volatile memory cell; and applying a bit voltage, a first word voltage, and a first common source voltage to the bit line, the word line, and the common source line, respectively, when the non-volatile memory cell performs a write operation or an erase operation. The N-type field-effect transistor has a threshold voltage. During the write operation, the bit voltage is equal to a high voltage, the first word voltage gradually increases in response to the gradually increasing threshold voltage, and the first common source voltage gradually decreases in response to the gradually increasing threshold voltage. During the erase operation, the bit voltage is equal to the high voltage, the first word voltage decreases gradually due to the gradually decreasing critical voltage, the first common source voltage is equal to the ground voltage, and the high voltage is equal to the drain-source breakdown voltage of the N-type field-effect transistor minus the critical voltage.

[0012] In one embodiment of the present invention, during the write operation, the first character voltage is a low voltage, a medium voltage, or a high voltage, and the first common source voltage is a medium voltage, a low voltage, or a ground voltage, wherein the high voltage is greater than the medium voltage, the medium voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

[0013] In one embodiment of the present invention, during the erasure operation, the first character voltage is a low voltage or a ground voltage, the high voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

[0014] In one embodiment of the present invention, when the non-volatile memory cell is not being written or erased, the bit lines are electrically floating, and a second word voltage and a second common source voltage are applied to the word lines and the common source lines respectively. The second word voltage is a ground voltage or a low voltage, and the second common source voltage is a medium voltage. The high voltage is greater than the medium voltage, the medium voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

[0015] In one embodiment of the present invention, the base is implemented as a P-type well region, a P-type semiconductor substrate or a P-type epitaxial layer.

[0016] Based on the above, the operation method of non-volatile memory array and non-volatile memory cell applies a step voltage to the word line and common source line during the write operation, and applies a step voltage to the word line during the erase operation, so as to shorten the time of the write operation or erase operation, thereby improving the write efficiency or erase efficiency.

[0017] To enable your review committee to have a better understanding of the structural features and effects achieved by the present invention, the following preferred embodiment diagrams and detailed descriptions are provided:

Implementation Method

[0018] Embodiments of the present invention will be further explained below with reference to the accompanying drawings. Wherever possible, the same reference numerals in the drawings and description represent the same or similar components. In the drawings, shapes and thicknesses may be exaggerated for simplification and convenience. It is understood that elements not specifically shown in the drawings or described in the description are forms known to those skilled in the art. Those skilled in the art can make various changes and modifications based on the content of this invention.

[0019] Unless otherwise specified, certain conditional clauses or words, such as "can," "could," "might," or "may," are generally intended to express features, elements, or steps that are present in the embodiments of this invention, but may also be interpreted as features, elements, or steps that may not be necessary. In other embodiments, these features, elements, or steps may be unnecessary.

[0020] The description of “one embodiment” or “an embodiment” in the following text refers to a specific element, structure, or feature associated with at least one embodiment. Therefore, the multiple descriptions of “one embodiment” or “an embodiment” appearing in various places below are not directed to the same embodiment. Furthermore, specific components, structures, and features in one or more embodiments may be combined in a suitable manner.

[0021] Certain terms are used in the specification and claims to refer to specific elements. However, those skilled in the art will understand that the same element may be referred to by different names. The specification and claims do not distinguish elements by differences in name, but by differences in function. The term "comprising" as used in the specification and claims is an open-ended term and should be interpreted as "comprising but not limited to". In addition, "coupled" here includes any direct and indirect means of connection. Therefore, if the text describes a first element coupled to a second element, it means that the first element can be directly connected to the second element by electrical connection or signal connection such as wireless transmission or optical transmission, or indirectly electrically or signal connected to the second element by other elements or connection means.

[0022] The disclosure is specifically described by the following examples, which are merely illustrative. Various modifications and refinements can be made by those skilled in the art without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims. Throughout the specification and claims, unless explicitly stated otherwise, the words “a” and “the” include “a or at least one” of the element or component. Furthermore, as used in this disclosure, the singular article also includes descriptions of multiple elements or components unless clearly excluded from the specific context. Moreover, when applied in this description and throughout the claims below, unless explicitly stated otherwise, “in which” may include both “in which” and “on which”. The terms used throughout the specification and claims, unless otherwise specified, generally have their ordinary meaning in the context of this disclosure and in specific contexts. Certain terms used to describe this disclosure will be discussed below or elsewhere in this specification to provide additional guidance to practitioners in describing this disclosure. Examples throughout this specification, including examples of any terms discussed herein, are for illustrative purposes only and do not limit the scope or meaning of this disclosure or any illustrative terms. Similarly, this disclosure is not limited to the various embodiments set forth in this specification.

[0023] In the following description, an operation method for a non-volatile memory array and a non-volatile memory cell will be provided, wherein during a write operation, a step voltage is applied to the word line and the common source line, and during an erase operation, a step voltage is applied to the word line to shorten the time of the write operation or the erase operation, thereby improving the write efficiency or the erase efficiency.

[0024] Figure 1 is a circuit diagram of a non-volatile memory array according to an embodiment of the present invention. Referring to Figure 1, the operation method of the non-volatile memory array 1 is described below. The non-volatile memory array 1 includes multiple parallel common source lines SL, multiple parallel word lines WL, multiple parallel bit lines BL, and multiple sub-memory arrays M. The common source line SL includes a first common source line SL1 and a second common source line SL2. The word lines WL are parallel to the common source line SL. The word lines WL include a first word line WL1 and a second word line WL2. The bit lines BL are perpendicular to the word lines WL. The bit lines BL include a first bit line BL1, a second bit line BL2, a third bit line BL3, a fourth bit line BL4, a fifth bit line BL5, a sixth bit line BL6, a seventh bit line BL7, and an eighth bit line BL8. Each sub-memory array M is coupled to one common-source line SL, one word line WL, and four bit lines BL. Each sub-memory array M includes a first non-volatile memory cell E1, a second non-volatile memory cell E2, a third non-volatile memory cell E3, and a fourth non-volatile memory cell E4. The first non-volatile memory cell E1 is coupled to the first word line WL1, the first bit line BL1, and the first common-source line SL1. The second non-volatile memory cell E2 is coupled to the first word line WL1, the second bit line BL2, and the first common-source line SL1. The third non-volatile memory cell E3 is coupled to the first word line WL1, the third bit line BL3, and the first common-source line SL1. The fourth non-volatile memory cell E4 is coupled to the first word line WL1, the fourth bit line BL4, and the first common-source line SL1. The first non-volatile memory cell E1, the second non-volatile memory cell E2, the third non-volatile memory cell E3, and the fourth non-volatile memory cell E4 each include an N-type field-effect transistor T1, T2, T3, or T4. Each of these cells serves as an operable memory cell. Furthermore, each of the first non-volatile memory cell E1, the second non-volatile memory cell E2, the third non-volatile memory cell E3, and the fourth non-volatile memory cell E4 also includes capacitors C1, C2, C3, and C4.

[0025] Specifically, the gates of N-type field-effect transistors T1, T2, T3 and T4 are coupled to the first word line WL1 through capacitors C1, C2, C3 and C4, respectively. The sources of N-type field-effect transistors T1, T2, T3 and T4 are coupled to the first common source line SL1. The drains of N-type field-effect transistors T1, T2, T3 and T4 are coupled to the first word line BL1, the second word line BL2, the third word line BL3 and the fourth word line BL4, respectively.

[0026] In the operation method of the non-volatile memory array 1, a ground voltage is applied to the base of the N-type field-effect transistors T1, T2, T3, or T4 of the operable memory cell as the base voltage Vs. The base is implemented as a P-type well region, a P-type semiconductor substrate, or a P-type epitaxial layer. When the operable memory cell performs a write operation or an erase operation, a bit voltage, a first word voltage, and a first common source voltage are applied to the bit line BL, the first word line WL1, and the first common source line SL1 coupled to the operable memory cell, respectively. The N-type field-effect transistors T1, T2, T3, or T4 of the operable memory cell have a threshold voltage. In the write operation, the bit voltage is equal to the high voltage, the first word voltage gradually increases in response to the gradually increasing threshold voltage and serves as a step voltage, and the first common source voltage gradually decreases in response to the gradually increasing threshold voltage and serves as a step voltage. During the erase operation, the bit voltage is equal to the high voltage, the first word voltage decreases gradually due to the progressively decreasing critical voltage and serves as a step voltage, the first common source voltage is equal to the ground voltage, the high voltage is equal to the drain-to-source breakdown voltage of the N-type field-effect transistors T1, T2, T3 or T4 of the operable memory cell minus the critical voltage, and the ground voltage is zero.

[0027] For example, during a write operation, the first word voltage is a low voltage, a medium voltage, or a high voltage, and the first common-source voltage is a medium voltage, a low voltage, or ground voltage, where the high voltage is greater than the medium voltage, the medium voltage is greater than the low voltage, and the low voltage is greater than the ground voltage. The medium voltage may be equal to 0.5 times the drain-to-source breakdown voltage of the N-type field-effect transistors T1, T2, T3, or T4 in the operable memory cell, and the low voltage may be equal to 0.25 times the drain-to-source breakdown voltage of the N-type field-effect transistors T1, T2, T3, or T4 in the operable memory cell. During an erase operation, the first word voltage is a low voltage or ground voltage.

[0028] Specifically, the longer the write time, the higher the critical voltage becomes. The most efficient operating voltage for a non-volatile memory cell varies at different critical voltages. When the critical voltage of a non-volatile memory cell is approximately 1 volt, the first word voltage is low and the first common-source voltage is medium during writing, reducing the power required by the load. As writing continues, the critical voltage gradually shifts towards 1.5 volts. At this point, the operating efficiency of the memory cell gradually deteriorates. Therefore, the first word voltage is medium and the first common-source voltage is low to maintain optimal operating efficiency. Similarly, when the critical voltage is approximately 2 volts, the first word voltage becomes high and the first common-source voltage becomes ground, thereby improving overall write efficiency and shortening the write time.

[0029] The longer the erase time, the lower the critical voltage becomes. When a non-volatile memory cell has a high critical voltage, such as 2 volts, the channel lacks electron flow, which is not conducive to the generation of thermoelectric holes during erase. The first word voltage is low, so that a small current will pass through the channel, making it easy for the memory cell to perform the erase operation. As the erase continues, the critical voltage gradually decreases, for example to 1.5 volts. At this time, the memory cell has enough electron flow. However, too much electron flow will reduce the operating efficiency. Therefore, the first word voltage is set to the ground voltage to maintain better operating efficiency of the memory cell and shorten the erase time.

[0030] When the operable memory cell is not being written to or erased, the bit line BL coupled to the operable memory cell is electrically floating, and a second word voltage and a second common-source voltage are applied to the first word line WL1 and the first common-source line SL1, respectively. The second word voltage is a ground voltage or a low voltage, and the second common-source voltage is a medium voltage. The first word line WL1 is coupled to a ground voltage or a low voltage according to the process characteristics.

[0031] Figure 2 is a circuit diagram of a non-volatile memory cell according to an embodiment of the present invention. Referring to Figure 2, the operation method of the non-volatile memory cell E is described below. The non-volatile memory cell E is coupled to a word line WL, a bit line BL, and a common source line SL. The non-volatile memory cell E includes an N-type field-effect transistor T and a capacitor C. The gate of the N-type field-effect transistor T is coupled to the word line WL through the capacitor C, the drain of the N-type field-effect transistor T is coupled to the bit line BL, and the source of the N-type field-effect transistor T is coupled to the common source line SL.

[0032] In the operation method of the non-volatile memory cell E, a ground voltage is applied to the base of the N-type field-effect transistor T of the non-volatile memory cell E as a base voltage Vs. The base is implemented as a P-type well region, a P-type semiconductor substrate, or a P-type epitaxial layer. When the non-volatile memory cell E performs a write operation or an erase operation, a bit voltage, a first word voltage, and a first common-source voltage are applied to the bit line BL, the word line WL, and the common-source line SL, respectively. The N-type field-effect transistor T has a threshold voltage. During the write operation, the bit voltage is equal to the high voltage. The first word voltage gradually increases in response to the gradually increasing threshold voltage and serves as a step voltage. The first common-source voltage gradually decreases in response to the gradually increasing threshold voltage and serves as a step voltage. During the erase operation, the bit voltage is equal to the high voltage. The first word voltage decreases gradually due to the gradually decreasing critical voltage and serves as a step voltage. The first common source voltage is equal to the ground voltage. The high voltage is equal to the drain-source breakdown voltage of the N-type field-effect transistor T minus the critical voltage. The ground voltage is zero.

[0033] For example, in a write operation, the first word voltage is low, medium, or high, and the first common-source voltage is medium, low, or ground. High voltage is greater than medium voltage, medium voltage is greater than low voltage, and low voltage is greater than ground. Medium voltage can be equal to 0.5 times the drain-to-source breakdown voltage of the N-type field-effect transistor T, and low voltage can be equal to 0.25 times the drain-to-source breakdown voltage of the N-type field-effect transistor T. In an erase operation, the first word voltage is low or ground.

[0034] When the non-volatile memory cell E is not being written to or erased, the bit line BL is electrically floating, and a second word voltage and a second common-source voltage are applied to the word line WL and the common-source line SL, respectively. The second word voltage is a ground voltage or a low voltage, and the second common-source voltage is a medium voltage. The word line WL is coupled to the ground voltage or the low voltage according to the process characteristics.

[0035] According to the above embodiments, the operation method of the non-volatile memory array and the non-volatile memory cell applies a step voltage to the word line and the common source line during the write operation, and applies a step voltage to the word line during the erase operation, so as to shorten the time of the write operation or the erase operation, thereby improving the write efficiency or the erase efficiency.

[0036] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Therefore, all equivalent changes and modifications made in accordance with the shape, structure, features and spirit described in the claims of the present invention should be included in the scope of the claims of the present invention. [Simplified Explanation of the Diagram]

[0037] Figure 1 is a circuit diagram of a non-volatile memory array according to an embodiment of the present invention. Figure 2 is a circuit diagram of a non-volatile memory cell according to an embodiment of the present invention.

Claims

1. A method of operating a non-volatile memory array, the non-volatile memory array comprising multiple parallel common-source lines, multiple parallel word lines, multiple parallel bit lines, and multiple sub-memory arrays, wherein the multiple parallel common-source lines include a first common-source line, the multiple parallel word lines are parallel to the multiple parallel common-source lines, the multiple parallel word lines include a first word line, the multiple parallel bit lines are perpendicular to the multiple parallel word lines, and the multiple parallel bit lines include a first bit line, a second bit line, a third bit line, and a fourth bit line; each sub-memory array is coupled to one common-source line, one word line, and four bit lines, wherein each sub-memory array comprises a first non-volatile memory cell, a second non-volatile memory cell, a third non-volatile memory cell, and a fourth non-volatile memory cell. A memory cell, wherein a first non-volatile memory cell is coupled to a first word line, the first bit line and the first common source line; a second non-volatile memory cell is coupled to the first word line, the second bit line and the first common source line; a third non-volatile memory cell is coupled to the first word line, the third bit line and the first common source line; and a fourth non-volatile memory cell is coupled to the first word line, the fourth bit line and the first common source line. Each of the first, second, third, and fourth non-volatile memory cells includes an N-type field-effect transistor. Each of the first, second, third, or fourth non-volatile memory cells serves as an operable memory cell. The operation method includes the following steps: A ground voltage is applied to the base of the N-type field-effect transistor of the operable memory cell; and during a write or erase operation of the operable memory cell, a bit voltage, a first word voltage, and a first common-source voltage are applied to the bit line, the first word line, and the first common-source line coupled to the operable memory cell, respectively. The N-type field-effect transistor of the operable memory cell has a critical voltage, wherein during the write operation, the bit voltage is equal to the high voltage, the first word voltage gradually increases in response to the gradually increasing critical voltage, and the first common-source voltage gradually decreases in response to the gradually increasing critical voltage. During the erase operation, the bit voltage is equal to the high voltage, the first word voltage gradually decreases in response to the gradually decreasing critical voltage, the first common-source voltage is equal to the ground voltage, and the high voltage is equal to the drain-to-source breakdown voltage of the N-type field-effect transistor of the operable memory cell minus the critical voltage.

2. The method of operating a non-volatile memory array as described in claim 1, wherein during the write operation, the first word voltage is a low voltage, a medium voltage, or the high voltage, and the first common source voltage is the medium voltage, the low voltage, or the ground voltage, wherein the high voltage is greater than the medium voltage, the medium voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

3. The method of operating a non-volatile memory array as described in claim 1, wherein during the erase operation, the first word voltage is a low voltage or the ground voltage, the high voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

4. The method of operating a non-volatile memory array as described in claim 1, wherein when the operable memory cell is not performing the write operation or the erase operation, the bit line coupled to the operable memory cell is electrically floating, and a second word voltage and a second common source voltage are respectively applied to the first word line and the first common source line, wherein the second word voltage is the ground voltage or a low voltage, the second common source voltage is a medium voltage, the high voltage is greater than the medium voltage, the medium voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

5. The method of operating a non-volatile memory array as described in claim 1, wherein the base is implemented as a P-type well region, a P-type semiconductor substrate, or a P-type epitaxial layer.

6. A method of operating a non-volatile memory cell, the non-volatile memory cell being coupled to a word line, a bit line, and a common source line, the non-volatile memory cell comprising an N-type field-effect transistor, the method comprising the following steps: A ground voltage is applied to the base of the N-type field-effect transistor in the non-volatile memory cell; and during a write or erase operation in the non-volatile memory cell, a bit voltage, a first word voltage, and a first common-source voltage are applied to the bit line, the word line, and the common-source line, respectively. The N-type field-effect transistor has a critical voltage, wherein during the write operation, the bit voltage is equal to the high voltage, the first word voltage gradually increases in response to the gradually increasing critical voltage, and the first common-source voltage gradually decreases in response to the gradually increasing critical voltage. During the erase operation, the bit voltage is equal to the high voltage, the first word voltage gradually decreases in response to the gradually decreasing critical voltage, the first common-source voltage is equal to the ground voltage, and the high voltage is equal to the drain-to-source breakdown voltage of the N-type field-effect transistor minus the critical voltage.

7. The method of operating a non-volatile memory cell as described in claim 6, wherein during the write operation, the first word voltage is a low voltage, a medium voltage, or the high voltage, and the first common source voltage is the medium voltage, the low voltage, or the ground voltage, wherein the high voltage is greater than the medium voltage, the medium voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

8. The method of operating a non-volatile memory cell as described in claim 6, wherein during the erase operation, the first word voltage is a low voltage or the ground voltage, the high voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

9. The method of operating a non-volatile memory cell as described in claim 6, wherein when the non-volatile memory cell is not performing the write operation or the erase operation, the bit line is electrically floating, and a second word voltage and a second common-source voltage are respectively applied to the word line and the common-source line, the second word voltage being the ground voltage or a low voltage, the second common-source voltage being a medium voltage, the high voltage being greater than the medium voltage, the medium voltage being greater than the low voltage, and the low voltage being greater than the ground voltage.

10. A method of operating a non-volatile memory cell as described in claim 6, wherein the base is implemented as a P-type well region, a P-type semiconductor substrate, or a P-type epitaxial layer.

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