Multiphase voltage regulation circuit having interleaved clock control mechanism

Abstract

A multiphase voltage regulation circuit having an interleaved clock control mechanism includes a plurality of voltage regulators and a clock signal generating circuit. The clock signal generating circuit multiplies a target frequency by the number of the voltage regulators to obtain a reference frequency, and accordingly generates a reference clock signal in which each of a plurality of pulse waves has the reference frequency. The clock signal generating circuit divides the reference clock signal into regulation clock signals, and outputs the regulation clock signals respectively to the voltage regulators. A frequency of each of pulse waves of the regulation clock signals is equal to the target frequency. Phases of each one of the regulation clock signals are respectively not overlapping with the phases of another of the regulation clock signals. The voltage regulators operate respectively based on the regulation clock signals.

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