Circuit and method for improving sensing accuracy

Abstract

A processing circuit comprises a delay circuit for outputting a delayed signal according to a first path delay coefficient; a control circuit for outputting a controlled signal according to a second path delay coefficient; a transforming circuit for transforming the controlled signal to a transformed signal; a mixing circuit for mixing the delayed signal and the transformed signal, to generate a mixed signal; a removing circuit for removing a direct current (DC) component of the mixed signal, to generate a removed signal; a computing circuit for computing the first path delay coefficient, the second path delay coefficient and a signal power; an amplifying circuit for amplifying an amplitude of the removed signal, to generate an amplified signal; and a combining circuit for combining a plurality of chirps in the amplified signal.

Description

Technical Field

[0001] This invention relates to a circuit and method for a wireless communication system, and more particularly to a circuit and method for improving sensing accuracy. Prior Technology

[0002] A sensing device is an electronic device that senses the presence, speed, and / or distance of a target object. During sensing, the transmitting end of the sensing device transmits a signal, which is reflected by the target object and received by the receiving end. The signal received by the sensing device contains not only the target signal but also a lot of noise and interference (such as transmitter-to-receiver leakage, T2R leakage). This noise and interference cause a loss of effective number of bits (ENOB) in the internal circuitry of the sensing device, increase the noise level, and amplify phase mismatch (IQ mismatch), etc. All of these factors reduce the sensing accuracy of the device. Therefore, improving sensing accuracy is a pressing problem that needs to be solved. Summary of the Invention

[0003] One of the objectives of this invention is to provide a circuit and method to improve sensing accuracy in order to solve the above-mentioned problems.

[0004] This invention discloses a processing circuit comprising: a delay circuit for outputting a delay signal based on a first path delay coefficient; a control circuit for determining a clock phase sampling time based on a second path delay coefficient and outputting a control signal based on the clock phase sampling time; a conversion circuit coupled to the control circuit for converting the control signal into a conversion signal; a mixer circuit coupled to the delay circuit and the conversion circuit for mixing the delay signal and the conversion signal to generate a mixer signal; and a removal circuit coupled to the mixer circuit for removing the direct current from the mixer signal. The system comprises: a current (DC) component to generate a removal signal; a calculation circuit coupled to the delay circuit, the control circuit, and the removal circuit, for calculating the first path delay coefficient, the second path delay coefficient, and a signal power based on the removal signal; an amplifier circuit coupled to the removal circuit and the calculation circuit, for amplifying an amplitude of the removal signal based on the signal power to generate an amplified signal; and a combining circuit coupled to the amplifier circuit for combining a plurality of chirps in the amplified signal to generate a combined signal.

[0005] This invention also discloses a method for improving sensing accuracy, comprising: outputting a delay signal based on a first path delay coefficient; determining a clock phase sampling time based on a second path delay coefficient, and outputting a control signal based on the clock phase sampling time; converting the control signal into a conversion signal; mixing the delay signal and the conversion signal to generate a mixing signal; removing the direct current (DC) component of the mixing signal to generate a removal signal; calculating the first path delay coefficient, the second path delay coefficient, and a signal power based on the removal signal; amplifying an amplitude of the removal signal based on the signal power to generate an amplified signal; and incorporating a plurality of chirps into the amplified signal to generate a combined signal.

[0006] In summary, this invention provides a circuit and method for improving sensing accuracy. A binding gain is generated during the operation of the binding circuit. This binding gain is used to improve the signal-to-noise ratio, thereby reducing the impact of noise and interference. Furthermore, the estimated path delay is obtained by calculating the path delay coefficient and signal power. When the estimated path delay approximates the actual path delay, the DC component is obtained. By removing the DC component, the impact of leakage from the transmitting end to the receiving end is reduced. Therefore, the problem of how to improve sensing accuracy can be solved. Simple Explanation of the Diagram

[0007] Figure 1 is a schematic diagram of a sensing device according to one embodiment of the present invention. Figure 2 is a schematic diagram of a processing circuit according to one embodiment of the present invention. Figure 3 is a schematic diagram of a control circuit according to one embodiment of the present invention. Figure 4 is a schematic diagram of the clock phase according to one embodiment of the present invention. Figure 5 is a schematic diagram of a delay circuit according to one embodiment of the present invention. Figure 6 is a schematic diagram of the calculation results according to one embodiment of the present invention. Figure 7 is a schematic diagram of the sensing results according to one embodiment of the present invention. Figure 8 is a flowchart of the process of Embodiment 1 of the present invention. Figure 9 is a flowchart of the process of Embodiment 1 of the present invention. Implementation

[0008] Figure 1 is a schematic diagram of a sensing device 10 according to an embodiment of the present invention. The sensing device 10 can be applied to wireless communication systems such as wireless local area networks (WLANs) (e.g., WiFi), Long Term Evolution (LTE) systems, LTE-Advanced (LTE-A) systems, and 5th generation (5G) systems. The sensing device 10 can support the Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard (e.g., 802.11AX, 802.11be, or later versions). The 802.11 standard supports Orthogonal Frequency Division Multiple Access (OFDMA) and / or Multi-User Multiple-Input Multiple-Output (MU-MIMO) technologies. In one embodiment, the sensing device 10 can be a Frequency Modulated Continuous Wave (FMCW) device.

[0009] In Figure 1, the sensing device 10 includes a signal generating circuit 100, a first conversion circuit 102, a first filtering circuit 104, a first mixing circuit 106, a first amplifying circuit 108, a transmitting circuit 110, a receiving circuit 112, a second amplifying circuit 114, a second mixing circuit 116, a second filtering circuit 118, a processing circuit 120, and a second conversion circuit 122. The signal generating circuit 100, the first conversion circuit 102, the first filtering circuit 104, the first mixing circuit 106, the first amplifying circuit 108, and the transmitting circuit 110 can be considered as transmitting terminals. The receiving circuit 112, the second amplifying circuit 114, the second mixing circuit 116, the second filtering circuit 118, the processing circuit 120, and the second conversion circuit 122 can be considered as receiving terminals.

[0010] In the transmitting end, signal generation circuit 100 generates an initial signal I_SG. The initial signal I_SG includes a chirp signal, wherein the chirp signal contains one or more chirps. A first conversion circuit 102 is coupled to signal generation circuit 100 and converts the initial signal I_SG into a first conversion signal TR_SG1. A first filter circuit 104 is coupled to first conversion circuit 102 and filters the first conversion signal TR_SG1 to generate a first filter signal F_SG1. A first mixer circuit 106 is coupled to first filter circuit 104 and is used to adjust the frequency based on a periodic signal (e.g., ...). ,in The first mixer circuit 106 (which is the carrier frequency) mixes the first filtered signal F_SG1 to generate a first mixed signal M_SG1. In one embodiment, the first mixer circuit 106 is further coupled to an oscillator circuit (not shown in Figure 1) and obtains a periodic signal from the oscillator circuit. A first amplifier circuit 108 is coupled to the first mixer circuit 106 to amplify the amplitude of the first mixed signal M_SG1 (e.g., by multiplying the amplitude of the first mixed signal M_SG1 by the amplification factor of the first amplifier circuit 108) to generate a first amplified signal A_SG1. A transmission circuit 110 is coupled to the first amplifier circuit 108 to input the first amplified signal A_SG1 and to transmit (or output) a transmission signal TX_SG. In one embodiment, the transmission signal TX_SG includes the first amplified signal A_SG1.

[0011] In the receiving end, the receiving circuit 112 is used to receive the received signal RX_SG corresponding to the transmitted signal TX_SG, and output the output signal OP_SG. In one embodiment, the received signal RX_SG is the signal received by the receiving circuit 112 after the transmitted signal TX_SG is reflected by the sensed object OBJ. In one embodiment, the output signal OP_SG includes the received signal RX_SG. The second amplifier circuit 114 is coupled to the receiving circuit 112 and is used to amplify the amplitude of the output signal OP_SG (for example, by multiplying the amplitude of the output signal OP_SG by the amplification factor of the second amplifier circuit 114) to generate a second amplified signal A_SG2. The second mixer circuit 116 is coupled to the second amplifier circuit 114 and is used to generate a second amplified signal A_SG2 based on a periodic signal (e.g., The second mixing circuit 116 mixes the second amplified signal A_SG2 to generate a second mixing signal M_SG2. In one embodiment, the second mixing circuit 116 is further coupled to an oscillator circuit (not shown in Figure 1) and obtains a periodic signal from the oscillator circuit. The second filtering circuit 118 is coupled to the second mixing circuit 116 and is used to filter the second mixing signal M_SG2 to generate a second filtered signal F_SG2. The processing circuit 120 is coupled to the signal generation circuit 100 and the second filtering circuit 118 and is used to process the second filtered signal F_SG2 according to the initial signal I_SG to generate a combined signal CB_SG. The second conversion circuit 122 is coupled to the processing circuit 120 and is used to convert the combined signal CB_SG into a second conversion signal TR_SG2 to obtain a sensing result.

[0012] In one embodiment, at least one of the output signal OP_SG, the second amplified signal A_SG2, the second mixing signal M_SG2, and the second filtered signal F_SG2 contains a leakage signal (not shown in Figure 1). The leakage signal is noise that leaks from the transmitting end to the receiving end within the sensing device 10. The leakage signal is eliminated by the operation of the processing circuit 120. That is, the combined signal CB_SG and the second conversion signal TR_SG2 do not contain a leakage signal.

[0013] In one embodiment, the first conversion circuit 102 includes a digital-to-analog converter (DAC). In one embodiment, the first filtering circuit 104 includes a low-pass filter (LPF). In one embodiment, the first amplification circuit 108 includes a power amplifier (PA). In one embodiment, the second amplification circuit 114 includes a low-noise amplifier (LNA). In one embodiment, the second filtering circuit 118 includes a low-pass filter. In one embodiment, the second conversion circuit 122 includes a Fast Fourier Transform (FFT) circuit. In one embodiment, the FFT circuit performs at least one of Range-FFT, Doppler-FFT, and Angle-FFT.

[0014] In one embodiment, the initial signal I_SG and the combined signal CB_SG are time-domain digital signals. In one embodiment, the first conversion signal TR_SG1, the first filter signal F_SG1, the first mixer signal M_SG1, the first amplification signal A_SG1, the transmit signal TX_SG, the receive signal RX_SG, the output signal OP_SG, the second amplification signal A_SG2, the second mixer signal M_SG2, and the second filter signal F_SG2 are time-domain analog signals. In one embodiment, the second conversion signal TR_SG2 is a frequency-domain digital signal.

[0015] Figure 2 is a schematic diagram of a processing circuit 120 according to one embodiment of the present invention. The processing circuit 120 includes a delay circuit 200, a control circuit 202, a third conversion circuit 204, a third mixer circuit 206, a removal circuit 208, a calculation circuit 210, a third amplifier circuit 212, and a combination circuit 214. Specifically, the delay circuit 200 is coupled to the signal generation circuit 100 in Figure 1 and is used to output a delay signal D_SG based on a first path delay coefficient C_PD1. The control circuit 202 is coupled to the second filter circuit 118 in Figure 1 and is used to determine the clock phase sampling time based on the second path delay coefficient C_PD2, and to output a control signal CT_SG corresponding to the second filter signal F_SG2 based on the clock phase sampling time. The third conversion circuit 204 is coupled to the control circuit 202 and is used to convert the control signal CT_SG into a third conversion signal TR_SG3. The third mixing circuit 206 is coupled to the delay circuit 200 and the third conversion circuit 204, and is used to mix the delayed signal D_SG and the third conversion signal TR_SG3 to generate the third mixing signal M_SG3. The removal circuit 208 is coupled to the third mixing circuit 206, and is used to remove the direct current (DC) component of the third mixing signal M_SG3 to generate the removal signal RM_SG. The calculation circuit 210 is coupled to the delay circuit 200, the control circuit 202, and the removal circuit 208, and is used to calculate the first path delay coefficient C_PD1, the second path delay coefficient C_PD2, and the signal power P based on the removal signal RM_SG. The third amplification circuit 212 is coupled to the removal circuit 208 and the calculation circuit 210, and is used to amplify the amplitude of the removal signal RM_SG based on the signal power P to generate the third amplified signal A_SG3. The combination circuit 214 is coupled to the third amplifier circuit 212 and the second conversion circuit 122 in Figure 1, and is used to combine multiple linear frequency conversions in the third amplified signal A_SG3 to generate the combination signal CB_SG.

[0016] In one embodiment, the step of the delay circuit 200 outputting a delayed signal D_SG according to a first path delay coefficient C_PD1 includes: delaying an initial signal I_SG to generate a plurality of candidate delayed signals; and selecting one candidate delayed signal as the delayed signal D_SG from the plurality of candidate delayed signals according to the first path delay coefficient C_PD1. In one embodiment, the step of the control circuit 202 determining the clock phase sampling time according to a second path delay coefficient C_PD2 includes: dividing the sampling time of the third conversion circuit 204 into a plurality of candidate clock phase sampling times; and selecting one candidate clock phase sampling time as the clock phase sampling time from the plurality of candidate clock phase sampling times according to the second path delay coefficient C_PD2.

[0017] In one embodiment, the step of calculating the first path delay coefficient C_PD1, the second path delay coefficient C_PD2, and the signal power P based on the removal signal RM_SG includes: (A) setting the value of the phase counter to a first initial value and setting the signal power to a second initial value; (B) calculating the first path delay coefficient C_PD1 and the second path delay coefficient C_PD2 based on the value of the phase counter, and triggering an output of the initial signal I_SG corresponding to the delayed signal D_SG (i.e., triggering the signal generation circuit 100 to generate (or output) the initial signal I_SG); (C) calculating the power of the removal signal RM_SG after a linear frequency conversion time; (D) incrementing the value of the phase counter by one, resetting the signal power P to be equal to the power of the removal signal RM_SG, and repeating step (B) based on the incremented value of the phase counter and the reset signal power P, in response to the power of the removal signal RM_SG being less than the signal power P and the detection limit. The sum of margins (e.g., 3dB); and (E) decrementing the value of the phase counter by one, and calculating the first path delay coefficient C_PD1 and the second path delay coefficient C_PD2 based on the decrement of the phase counter, in response to the removal signal RM_SG having a power not less than the sum of the signal power P and the detection limit. In one embodiment, the calculation circuit 210 calculates the estimated path delay (i.e., the estimated leakage path delay from the transmitter to the receiver) based on at least one of the first path delay coefficient C_PD1, the second path delay coefficient C_PD2, and the decrement of the phase counter.

[0018] In one embodiment, the estimated path delay includes the path from the input of the first conversion circuit 102 to the output of the transmission circuit 110, the signal transmission path between the transmission circuit 110 transmitting the transmission signal TX_SG and the receiving circuit 112 receiving the reception signal RX_SG, and the path from the input of the receiving circuit 112 to the output of the third conversion circuit 204. In one embodiment, the first path delay coefficient C_PD1 is related to the integer part of the estimated path delay. In one embodiment, the second path delay coefficient C_PD2 is related to the fractional part of the estimated path delay.

[0019] In one embodiment, the step of the third amplifier circuit 212 amplifying the amplitude of the removal signal RM_SG to generate the third amplified signal A_SG3 according to the signal power P includes: calculating the gain for the removal signal RM_SG according to the signal power P; and multiplying the gain by the amplitude of the removal signal RM_SG. In one embodiment, the gain calculated by the third amplifier circuit 212 is used to improve the effective accuracy (e.g., full scale) of the conversion operation (e.g., fixed-point operation of fast Fourier transform) performed by the second conversion circuit 112.

[0020] In one embodiment, the delay circuit 200 includes delay line memory. In one embodiment, the control circuit 202 includes a clock generator. In one embodiment, the third conversion circuit 204 includes an analog-to-digital converter (ADC). In one embodiment, the delay signal D_SG, the third conversion signal TR_SG3, the third mixing signal M_SG3, the removal signal RM_SG, and the third amplification signal A_SG3 are time-domain digital signals.

[0021] In one embodiment, a combining gain is obtained by combining multiple linear frequency conversions in the third amplified signal A_SG3 via the combining circuit 214, so that the change in the received phase of a linear frequency conversion in the third amplified signal A_SG3 can be ignored (i.e., the moving speed of the sensed object (e.g., the sensed object OBJ in Figure 1) is less than a threshold, which causes the Doppler effect on the sensed object to be negligible). This can be expressed as an equation (Equation 1): (Equation 1)

[0022] in This refers to the number of linear frequency converters. In one embodiment, the combined gain is used to improve the signal-to-noise ratio (SNR) of the third amplified signal A_SG3. That is, the SNR of the combined signal CB_SG is higher than that of the third amplified signal A_SG3.

[0023] In one embodiment, the combination signal CB_SG is converted into a second conversion signal TR_SG2 via a second conversion circuit 122, and the transformation gain is obtained. This can be expressed as equation (Equation 2): (Equation 2)

[0024] in It is the sampling frequency of the third conversion circuit 204. , (is the scanning bandwidth), and It is mid-frequency resolution ( , (This refers to the linear conversion time). In one embodiment, the conversion gain is used to increase the processing gain of the second conversion circuit 122.

[0025] The following embodiments illustrate how the sensing device 10 senses a target. First, the signal generation circuit 100 generates a baseband transmission signal. (For example, the initial signal I_SG) can be represented by equation (Equation 3): (Equation 3)

[0026] in It is the sampling time of the first conversion circuit 102. , (This is the sampling frequency of the first conversion circuit 102), and This refers to the number of sampling points in the first conversion circuit 102. The first conversion circuit 102 and the first filter circuit 104 process the baseband transmission signal. To generate a signal (For example, the first filtered signal F_SG1). Next, the first mixer circuit 106 and the first amplifier circuit 108 process the signal. To generate radio frequency transmission signals (For example, the first amplified signal A_SG1 and / or the transmission signal TX_SG). Radio frequency transmission signal This can be represented by equation (Equation 4): (Equation 4)

[0027] in It is the carrier frequency, and It is the amplification factor of the first amplifier circuit 108.

[0028] Transmit radio frequency signals in transmission circuit 110 And radio frequency transmission signal After being reflected by the sensed object OBJ, the receiving circuit 112 receives a received signal. (For example, receiving signal RX_SG). Receiving signal This can be represented by equation (Equation 5): (Equation 5)

[0029] in It is related to distance carrier frequency and radar cross-section Path loss, and This refers to the round trip delay. Distance. This refers to the distance between the sensing device 10 and the sensed object. Next, through the operation of the second amplifier circuit 114, the second mixer circuit 116, and the second filter circuit 118, the baseband received signal... (For example, the second filtered signal F_SG2) is obtained. Baseband received signal This can be represented by equation (Equation 6): (Equation 6)

[0030] in It is the amplification factor of the second amplifier circuit 114.

[0031] The control circuit 202 in the processing circuit 120 controls the baseband receiving signal. The output is shown in Figure 3. In Figure 3, the sampling time of the third conversion circuit 204 is... Cut into Equal division, clock phase interval is and path delay coefficient (For example, the second path delay factor) is used to control the baseband received signal. The output of the path delay coefficient. The relevant clock phase can be seen in Figure 4. The clock phase sampling time can be expressed by equation (Equation 7): (Equation 7)

[0032] Therefore, the output signal of the control circuit 202 (e.g., the control signal CT_SG) is Furthermore, the delay circuit 200 in the processing circuit 120 delays the baseband transmission signal. As shown in Figure 5. In Figure 5, , , … It is a backup delay signal. It is a buffer The number and path delay coefficient (For example, the first path delay factor) is used to control the baseband transmission signal. The delayed output. The sampling frequency of the buffer is... Therefore, the output signal of the delay circuit 200 (e.g., the delay signal D_SG) is Furthermore, the sampling frequency of the first conversion circuit 102... and the sampling frequency of the third conversion circuit 204 Set to the same frequency, i.e. .

[0033] The third conversion circuit 204 in the processing circuit 120 converts the output signal of the control circuit 202, and the third mixer circuit 206 in the processing circuit 120 mixes the output signals of the delay circuit 200 and the third conversion circuit 204 to generate an intermediate frequency signal. (For example, the third mixer signal M_SG3). Intermediate frequency signal This can be represented by equation (Equation 8): (Equation 8)

[0034] in It is the conjugate operator.

[0035] The removal circuit 208 in the processing circuit 120 removes the intermediate frequency signal. The DC component is as follows: (Equation 9)

[0036] in It is an intermediate frequency signal. The signal after removing the DC component (e.g., removing the signal RM_SG), and It is a linear frequency conversion time The number of sampling points in the sample.

[0037] According to a calculation process, the calculation circuit 210 in the processing circuit 120 calculates the path delay factor. Path delay coefficient and signal power (For example, signal power P). The calculation process includes the following steps:

[0038] Step A: Set the value of the phase counter. Set the initial value (e.g., 0) and the signal power. For the second initial value (e.g.) ).

[0039] Step B: Calculate the path delay coefficient according to equations (Equation 10) and (Equation 11). and path delay coefficient and the trigger signal generation circuit 100 outputs a baseband transmission signal. . (Equation 10) (Equation 11)

[0040] Step C: In a linear frequency conversion time Then, calculate the signal. power .power This can be represented by equation (Equation 12): (Equation 12)

[0041] Step D: If Reset as well as , and according to the reset and Repeat step B. This is the detection limit (e.g., 3 dB).

[0042] Step E: If Reset , and according to the reset Calculate path delay coefficient Path delay coefficient and path delay The path delay coefficient is obtained based on equations (10) and (11). and path delay coefficient Based on equation (Equation 13) and / or (Equation 14), the estimated path delay is obtained. As shown below: (Equation 13) (Equation 14)

[0043] After calculating the path delay coefficient Path delay coefficient and signal power Then, the calculation circuit 210 calculates the path delay coefficient. The output is sent to the delay circuit 200 to set the path delay factor. Output to control circuit 202, and convert signal power The output is sent to the amplifier circuit 212 in the processing circuit 120.

[0044] It should be noted that when the estimated path delay... Approximate path delay At that time, that is The intermediate frequency (IF) approaches 0. At this point, the IF signal... Approximate DC component. That is, when the intermediate frequency approaches 0, the signal... The power reaches its minimum value, at which point the leakage signal from the transmitting end to the receiving end has been removed. Figure 6 is a schematic diagram of the calculation results according to one embodiment of the present invention. Figure 6 is obtained according to the above calculation process (steps A to E). In Figure 6, the horizontal axis represents the value of the phase counter. The vertical axis represents signal power. (Unit is dB). The calculation results in Figure 6 show that when At that time, signal power It has a minimum value. That is, when At that time, the estimated path delay The closest to the actual path delay .

[0045] Next, based on the signal power output by the calculation circuit 210... Amplifier circuit 212 calculates gain and amplified signal (For example, the third amplified signal A_SG3), as shown in equations (15) and (16): (Equation 15) (Equation 16)

[0046] The combining circuit 214 in the processing circuit 120 is combined with the amplified signal. middle A linear frequency converter, as shown in equation (Equation 17): (Equation 17)

[0047] in This is the output signal of the combination circuit 214 (e.g., the combination signal CB_SG). The second conversion circuit 122 in the processing circuit 120 processes the output signal. A fast Fourier transform (e.g., distance fast Fourier transform, Doppler fast Fourier transform, and / or angle fast Fourier transform) is performed to obtain the sensing results, as shown in Figure 7. Figure 7 shows the sensing results generated by the distance fast Fourier transform performed by the second conversion circuit 122. In Figure 7, the horizontal axis represents the distance between the sensing device 10 and the sensing object OBJ. (The unit is meters (m), and the vertical axis is the output signal of the circuit 214.) The power (in dB). The sensing results in Figure 7 show two peaks, representing that the sensing device 10 detected two objects. The distances between the two objects and the sensing device 10 are 1 meter and 5 meters, respectively.

[0048] The operation of the aforementioned sensing device 10 can be summarized as process 80 in Figure 8. Process 80 includes the following steps:

[0049] Step S800: Start.

[0050] Step S802: Generate an initial signal.

[0051] Step S804: Convert the initial signal into a first conversion signal.

[0052] Step S806: Filter the first conversion signal to generate a first filtered signal.

[0053] Step S808: Mix the first filtered signal according to a periodic signal to generate a first mixed signal.

[0054] Step S810: Amplify the amplitude of the first mixing signal to generate a first amplified signal.

[0055] Step S812: Transmit the first amplified signal.

[0056] Step S814: Receive a received signal corresponding to the first amplified signal.

[0057] Step S816: Amplify the amplitude of the received signal to generate a second amplified signal.

[0058] Step S818: Mix the second amplified signal according to a periodic signal to generate a second mixing signal.

[0059] Step S820: Filter the second mixing signal to generate a second filtered signal.

[0060] Step S822: Based on the initial signal, process the second filtered signal to generate a combined signal.

[0061] Step S824: Convert the combined signal into a second converted signal to obtain a sensing result.

[0062] Step S826: End.

[0063] The operation of the aforementioned processing circuit 120 can be summarized as a process 90 in Figure 9. Process 90 includes the following steps:

[0064] Step S900: Begin.

[0065] Step S902: Output a delay signal based on a first path delay coefficient.

[0066] Step S904: Determine a clock phase sampling time based on a second path delay coefficient, and output a control signal based on the clock phase sampling time.

[0067] Step S906: Convert the control signal into a conversion signal.

[0068] Step S908: Mix the delayed signal and the converted signal to generate a mixing signal.

[0069] Step S910: Remove the DC component of the mixing signal to generate a removal signal.

[0070] Step S912: Calculate the first path delay coefficient, the second path delay coefficient, and a signal power based on the removal signal.

[0071] Step S914: Amplify the amplitude of the removed signal according to the signal power to generate an amplified signal.

[0072] Step S916: Combine multiple linear frequency conversions in the amplified signal to generate a combined signal.

[0073] Step S918: End.

[0074] Processes 80-90 are used to illustrate the operation of the sensing device 10 and the processing circuit 120, respectively. For detailed explanations and variations, please refer to the foregoing. They will not be repeated here.

[0075] It should be noted that the sensing device 10, the processing circuit 120, and the circuits therein can be implemented in many ways. For example, the above-mentioned devices (circuits) can be integrated into one or more devices (circuits). In addition, the sensing device 10 and the processing circuit 120 can be implemented using hardware (e.g., circuits), software, firmware (a combination of hardware devices and computer instructions and data, where the computer instructions and data are read-only software on the hardware device), electronic systems, or combinations of the above devices, and are not limited thereto.

[0076] The word "determine" as used in the above description can be replaced with "compute", "calculate", "obtain", "generate", "output", "use", "choose / select", "decide", or "is configured to". The word "detect" as used in the above description can be replaced with "monitor", "receive", "sensor", or "obtain". The word "according to" as used in the above description can be replaced with "in response to". The word "corresponding to" as used in the above description can be replaced with "of" or "associated with". The word "via" as used in the above description can be replaced with "on", "in", or "at". The word "includes" as used in the above description can be replaced with "is / are". The word "when" as used in the above description can be replaced with "in response to".

[0077] In summary, this invention provides a circuit and method for improving sensing accuracy. The aforementioned gains (e.g., gain for signal removal, combination gain, and conversion gain) are used to improve the signal-to-noise ratio, thereby reducing the impact of noise and interference. Furthermore, by calculating the path delay coefficient and signal power, an estimated path delay is obtained. When the estimated path delay approximates the actual path delay, the DC component is obtained. By removing the DC component, the impact of leakage from the transmitting end to the receiving end is reduced. Therefore, the problem of how to improve sensing accuracy can be solved. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0078] 10: Sensing Device

[0079] 100: Signal generation circuit

[0080] 102: First conversion circuit

[0081] 104: First filter circuit

[0082] 106: First mixer circuit

[0083] 108: First Amplifier Circuit

[0084] 110: Transmission circuit

[0085] 112: Receiving circuit

[0086] 114: Second Amplifier Circuit

[0087] 116: Second mixer circuit

[0088] 118: Second filter circuit

[0089] 120: Processing Circuit

[0090] 122: Second conversion circuit

[0091] I_SG: Initial signal

[0092] TR_SG1: First conversion signal

[0093] F_SG1: First filter signal

[0094] M_SG1: First mixing signal

[0095] A_SG1: First amplified signal

[0096] TX_SG: Transmission signal

[0097] RX_SG: Receive signal

[0098] OP_SG: Output signal

[0099] A_SG2: Second amplified signal

[0100] M_SG2: Second mixing signal

[0101] F_SG2: Second filter signal

[0102] CB_SG: Combined signal

[0103] TR_SG2: Second conversion signal

[0104] 200: Delay circuit

[0105] 202: Control Circuit

[0106] 204: Third conversion circuit

[0107] 206: Third mixer circuit

[0108] 208: Remove circuit

[0109] 210: Computational Circuits

[0110] 212: Third Amplifier Circuit

[0111] 214: Combined Circuit

[0112] D_SG: Delayed signal

[0113] CT_SG: Control signal

[0114] TR_SG3: Third conversion signal

[0115] M_SG3: Third mixing signal

[0116] RM_SG: Remove signal

[0117] A_SG3: Third Amplified Signal

[0118] C_PD1: First path delay coefficient

[0119] C_PD2: Second path delay coefficient

[0120] P: Signal power , Path delay coefficient

[0121] Sampling time

[0122] Sampling time Number of cuts

[0123] Clock phase sampling time

[0124] Baseband received signal

[0125] : Output signal of control circuit

[0126] , , ,…, : Backup delay signal

[0127] Output signal of the delay circuit

[0128] Temporary register

[0129] Temporary register quantity

[0130] Signal power

[0131] The value of the counter

[0132] R: Distance

[0133] 80, 90: Process

[0134] S800, S802, S804, S806, S808, S810, S812, S814, S816, S818, S820, S822, S824, S826, S900, S902, S904, S906, S908, S910, S912, S914, S916, S918: Steps

Claims

1. A processing circuit comprising: a delay circuit for outputting a delay signal based on a first path delay coefficient; a control circuit for determining a clock phase sampling time based on a second path delay coefficient, and outputting a control signal based on the clock phase sampling time; a conversion circuit coupled to the control circuit for converting the control signal into a conversion signal; and a mixer circuit coupled to the delay circuit and the conversion circuit for mixing the delay signal and the conversion signal to generate a mixer signal. A removal circuit, coupled to the mixer circuit, is used to remove the DC component of the mixer signal to generate a removal signal; A calculation circuit, coupled to the delay circuit, the control circuit, and the removal circuit, is used to calculate the first path delay coefficient, the second path delay coefficient, and a signal power based on the removal signal; an amplifier circuit, coupled to the removal circuit and the calculation circuit, is used to amplify an amplitude of the removal signal based on the signal power to generate an amplified signal; and a combining circuit, coupled to the amplifier circuit, is used to combine a plurality of linear frequency conversions (chirps) in the amplified signal to generate a combined signal.

2. The processing circuit of claim 1, wherein the step of the delay circuit outputting the delay signal according to the first path delay coefficient comprises: delaying an initial signal to generate a plurality of candidate delay signals; and selecting one candidate delay signal from the plurality of candidate delay signals as the delay signal according to the first path delay coefficient.

3. The processing circuit as claimed in claim 1, wherein the step of the control circuit determining the clock phase sampling time according to the second path delay coefficient comprises: dividing a sampling time of the conversion circuit into a plurality of candidate clock phase sampling times; and selecting one candidate clock phase sampling time from the plurality of candidate clock phase sampling times as the clock phase sampling time according to the second path delay coefficient.

4. The processing circuit as claimed in claim 1, wherein the step of the calculation circuit calculating the first path delay coefficient, the second path delay coefficient, and the signal power according to the removal signal comprises: (A) setting a value of a phase counter to a first initial value and setting the signal power to a second initial value; (B) calculating the first path delay coefficient and the second path delay coefficient according to the value, and triggering an output of an initial signal corresponding to the delay signal; (C) calculating a power of the removal signal after a linear frequency conversion time; (D) incrementing the value by one, resetting the signal power to be equal to the power, and re-executing step (B) according to the incremented value and the reset signal power to respond that the power is less than the sum of the signal power and a detection margin; and (E) decrementing the value by one, and calculating the first path delay coefficient and the second path delay coefficient according to the decremented value to respond that the power is not less than the sum of the signal power and the detection margin.

5. The processing circuitry of claim 4, wherein the computing circuitry calculates an estimated path delay based on at least one of the first path delay coefficient, the second path delay coefficient, and the reduced value.

6. The processing circuit of claim 1, wherein the step of amplifying the amplitude of the removal signal according to the signal power to generate the amplified signal comprises: calculating a gain for the removal signal according to the signal power; and multiplying the gain by the amplitude of the removal signal.

7. The processing circuitry as claimed in claim 1, wherein the delay circuitry includes a delay line memory.

8. The processing circuitry as claimed in claim 1, wherein the control circuitry includes a clock generator.

9. The processing circuitry of claim 1, wherein a combining gain is obtained by combining the plurality of linear frequency converters in the amplified signal through the combining circuitry, in response to the neglect of changes in the received phase of a linear frequency converter in the amplified signal.

10. A method for improving sensing accuracy, comprising: outputting a delay signal based on a first path delay coefficient; determining a clock phase sampling time based on a second path delay coefficient, and outputting a control signal based on the clock phase sampling time; converting the control signal into a conversion signal; mixing the delay signal and the conversion signal to generate a mixing signal; removing a DC component of the mixing signal to generate a removal signal; calculating the first path delay coefficient, the second path delay coefficient, and a signal power based on the removal signal; amplifying an amplitude of the removal signal based on the signal power to generate an amplified signal; and combining a plurality of chirps in the amplified signal to generate a combined signal.

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