A level conversion circuit and a DC / DC converter

Abstract

A level conversion circuit and a DC / DC converter are disclosed. The level conversion circuit includes: a current bias module configured to output a bias current; a control module configured to output a control current based on the bias current under the control of an input signal located in a low voltage domain; and a level conversion module configured to output an output signal located in a high voltage domain based on the control current, wherein the logic level of the output signal is the same as the logic level of the input signal. This invention can achieve fast level conversion and can effectively resist interference from high voltage domain power supplies.

Description

Technical Field

[0001] This invention relates to the field of circuit electronics, and more particularly to a level conversion circuit and a DC / DC converter. Prior Technology

[0002] In level conversion involving different voltage domains, rapid changes in the high-voltage power supply can interfere with the level conversion circuit, potentially causing inconsistencies between the output and input signal levels. For example, a DC / DC voltage converter requires a level conversion circuit to convert a Pulse Width Modulation (PWM) signal from a low-voltage domain to a high-voltage domain before driving the high-side power transistor. When the high-side power transistor of the DC / DC voltage converter is an N-type Metal-Oxide-Semiconductor (NMOS), the bootstrap capacitor provides the high-voltage domain for the level conversion circuit. Its upper and lower plate voltages serve as the power supply and ground for the high-voltage domain. Since the voltage across the bootstrap capacitor is floating, it changes with the activation of both the high-side and low-side power transistors. If this voltage change rate is large, it will interfere with the level conversion circuit, potentially causing the circuit to fail to correctly convert the PWM signal to the high-voltage domain, resulting in an incorrect high-voltage domain PWM signal output. Summary of the Invention

[0003] A level conversion circuit according to an embodiment of the present invention includes: a current bias source module configured to output a bias current; a control module configured to output a control current based on the bias current under the control of an input signal located in a low voltage domain; and a level conversion module configured to output an output signal located in a high voltage domain based on the control current, wherein the logic level of the output signal is the same as the logic level of the input signal.

[0004] According to an embodiment of the present invention, a DC / DC converter is connected to a bootstrap capacitor. The DC / DC converter includes a level conversion circuit, a high-side drive circuit, and a high-side power transistor as described above. The high-side drive circuit is configured to output a high-side drive signal located in the high voltage domain based on the output signal of the level conversion circuit. The high-side power transistor is configured to switch on and off based on the high-side drive signal to control the voltage of the bootstrap capacitor. The bootstrap capacitor provides a high voltage domain to the level conversion circuit and the high-side drive circuit based on its voltage. Simple Explanation of the Diagram

[0005] The invention can be better understood from the following description of specific embodiments of the invention in conjunction with the accompanying drawings, wherein: Figure 1 shows a schematic diagram of a DC / DC converter with an NMOS high-side power transistor. Figure 2 shows a circuit structure diagram of a level conversion circuit according to an embodiment of the present invention; Figure 3 shows a schematic diagram of a pulse generation unit; Figure 4 shows a waveform diagram of the signal in Figure 3. Implementation

[0006] The features and exemplary embodiments of various aspects of the present invention will now be described in detail. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of the invention by illustrating examples of the invention. The invention is by no means limited to any specific configurations and algorithms presented below, but covers any modifications, substitutions, and improvements to elements, components, and algorithms without departing from the spirit of the invention. Well-known structures and techniques are not shown in the drawings and the following description in order to avoid unnecessarily obscuring the invention.

[0007] Considering that excessively rapid changes in the power supply voltage in the high-voltage domain can interfere with the normal operation of the level conversion circuit, a level conversion circuit according to an embodiment of the present invention is proposed. This level conversion circuit generates an output signal in the high-voltage domain based on a current bias module, a control module, and a level conversion module. The bias current provided by the current bias module enables rapid level conversion and effectively resists interference from the high-voltage domain power supply, thereby enabling the level conversion circuit to output an accurate signal.

[0008] Figure 1 shows a schematic diagram of a DC / DC converter with an NMOS high-side power transistor. As shown in Figure 1, the DC / DC converter 100 includes a level switching circuit 101, a high-side drive circuit 102, a low-side drive circuit 103, a high-side power transistor MH, and a low-side power transistor ML. The connection point of the high-side power transistor MH and the low-side power transistor ML serves as the switching node SW. The bootstrap capacitor C1 is connected to the switching node SW, and the output capacitor C2 is connected to the switching node SW through an inductor L. Level conversion circuit 101 is configured to output an output signal in the high voltage domain (e.g., PWM high voltage signal PWM_out) under the control of a low voltage domain input signal (e.g., PWM low voltage signal PWM_in); high-side drive circuit 102 is configured to output a high-side drive signal in the high voltage domain based on the output signal of level conversion circuit 101; high-side power transistor MH is configured to switch on and off based on the high-side drive signal to control the voltage of bootstrap capacitor C1. Specifically, the switching on and off of high-side power transistor MH can control the connection state between switching node SW and input power supply VIN, and this connection state is related to the voltage of switching node SW; low-side... The driving circuit 103 is configured to output a low-side driving signal based on the input signal. The low-side power transistor ML and the high-side power transistor MH are connected in series between the input power supply VIN and the ground terminal. The low-side power transistor ML and the high-side power transistor MH are configured to control the voltage of the switching node SW based on the low-side driving signal. Specifically, the low-side power transistor ML and the high-side power transistor MH are controlled by switching the low-side power transistor SW on and off. The connection state is related to the voltage of the switching node. Both the low-side power transistor ML and the high-side power transistor MH are implemented based on NMOS. The high-side driving circuit 102 has a similar structure to the low-side driving circuit 103. Both are used to output a large current driving signal to turn on the connected power transistor. In Figure 1, the bootstrap capacitor C1 is configured to form a high voltage domain based on the switching node SW (i.e., the lower plate is connected to the switching node SW, and the upper plate and the lower plate form a high voltage domain that floats with the voltage of the switching node SW); the first end of the inductor L is connected to the switching node SW, the second end of the inductor L is connected to the first end of the output capacitor C2, and the second end of the output capacitor C2 is connected to the ground terminal. The inductor L and the output capacitor C2 filter the voltage of the switching node SW to generate the output voltage VOUT.

[0009] In Figure 1, the upper and lower plates of the bootstrap capacitor C1 form a high-voltage domain (i.e., the voltage domain formed by the connection node BST of the upper plate and the switching node SW). The level switching circuit 101 and the high-side drive circuit 102 operate based on this high-voltage domain. When the high-side power transistor MH is turned on, the voltage of the switching node SW is rapidly pulled up; when the low-side power transistor ML is turned on, the voltage of the switching node SW is rapidly pulled down. Since the voltage across the bootstrap capacitor C1 cannot change abruptly, the voltage of the upper plate of the bootstrap capacitor C1 will also change with the voltage of the switching node SW. Power transistors typically have a fast switching speed to reduce their own switching losses. In DC / DC converters used in high-voltage applications, the input power supply VIN, which can reach hundreds of volts, causes a very large voltage change rate dV / dt at the switching node SW. This voltage change rate dV / dt can interfere with the level switching circuit 101.

[0010] Figure 2 shows a circuit structure diagram of a level conversion circuit according to an embodiment of the present invention. It can be applied to the DC / DC converter of Figure 1, and also to other circuit systems that need to convert level signals from a low voltage domain to a high voltage domain. As shown in Figure 2, the level conversion circuit 101 includes: a current bias module 11 configured to output a bias current; a control module 12 configured to output a control current based on the bias current under the control of an input signal (such as PWM_in) in the low voltage domain, wherein the low voltage domain is formed based on a low-voltage power supply terminal and a low-voltage ground terminal; and a level conversion module 13 configured to output an output signal (such as PWM_out) located in the high voltage domain based on the control current, wherein the logic level of the output signal is the same as the logic level of the input signal, and the high voltage domain is formed based on a high-voltage power supply terminal and a high-voltage ground terminal.

[0011] In Figure 2, the logic level of the signal is either a high level or a low level (represented by 1 or 0). For input signals in the low-voltage domain, when the input signal is at a low level, its actual voltage is equal to the low-voltage ground terminal; when the input signal is at a high level, its actual voltage is equal to the low-voltage power supply terminal. Similarly, for output signals in the high-voltage domain, when the output signal is at a high level, its actual voltage is equal to the high-voltage power supply terminal; when the output signal is at a low level, its actual voltage is equal to the high-voltage ground terminal. Taking Figure 2 applied to Figure 1 as an example, the voltage difference between the high-voltage power supply terminal and the high-voltage ground terminal in the high-voltage domain, and the voltage difference between the low-voltage power supply terminal and the low-voltage ground terminal in the low-voltage domain, are typically around 5V. However, the actual voltage difference may fluctuate. Compared to the low-voltage domain, the voltage values ​​at each terminal of the high-voltage domain are relatively higher. For example, in Figure 1, the low-voltage ground terminal of the low-voltage domain is AVSS, and the low-voltage power supply terminal is AVDD. The high-voltage power supply terminal of the high-voltage domain is the upper plate BST of the bootstrap capacitor C1, with a voltage of 100V, and the high-voltage ground terminal is the lower plate SW of the bootstrap capacitor C1, with a voltage of 95V. In this embodiment of the invention, "same logic level" means that when the input signal is at a low level, the output signal is also at a low level, and when the input signal is at a high level, the output signal is also at a high level.

[0012] In Figure 1, the high-voltage domain of the level conversion circuit 101 is provided by the bootstrap capacitor C1, and therefore is subject to interference from the voltage change rate dV / dt of the switching node SW. Specifically, this manifests as an internal transistor coupling current generated based on the voltage change rate dV / dt, which may interfere with the input signal, causing the logic level of the output signal to differ from the input signal. However, as shown in Figure 2, in the level conversion circuit 101 of this invention, since the control current is generated based on the bias current and the amplitude of the control current is relatively large, it can resist the above-mentioned interference, keeping the level of the output signal of the level conversion module 13 unchanged. Thus, the level conversion module 13 outputs the output signal based on the control current, and its logic level is consistent with the input signal.

[0013] In some embodiments, the control module 12 is further configured to: output a first current as a control current based on the bias current when the input signal is at a high level; and output a second current as a control current based on the bias current when the input signal is at a low level. For example, as shown in FIG2, the control module 12 includes a first transistor M1, a second transistor M2, and an inverter I1. The control terminal of the first transistor M1 and the input terminal of the inverter I1 receive an input signal (such as the PWM low-voltage signal PWM_in). The control terminal of the second transistor M2 is connected to the output terminal of the inverter I1. The first terminals of the first transistor M1 and the second transistor M2 are connected to the current bias module 11. The second terminal of the first transistor M1 outputs the first current, and the second terminal of the second transistor M2 outputs the second current. When the PWM low-voltage signal PWM_in is at a high level, the first transistor M1 is turned on, outputting the first current based on the bias current; when the PWM low-voltage signal PWM_in is at a low level, the second transistor M2 is turned on, outputting the second current based on the bias current.

[0014] In some embodiments, the control module 12 further includes a Zener diode. The cathode of the Zener diode is connected to the first terminal of the first transistor M1 or the second transistor M2, and the anode of the Zener diode is connected to the low-voltage ground terminal of the low-voltage domain. For example, as shown in FIG2, the control module 12 includes Zener diodes Z1 and Z2. The cathode of Zener diode Z1 is connected to the first terminal of the first transistor M1, the cathode of Zener diode Z2 is connected to the first terminal of the second transistor M2, and the anodes of Zener diodes Z1 and Z2 are connected to the low-voltage ground terminal AVSS. The Zener diode is used to clamp the source terminal of the first transistor M1 or the second transistor M2 connected to its cathode, preventing the source terminal of the first transistor M1 or the second transistor M2 from being coupled and causing gate breakdown when the voltage of the switching node SW rises.

[0015] In some embodiments, the level conversion module 13 includes two transistor units and an RS latch, wherein: the first transistor unit is configured to generate a pull-up current for the output node of the transistor unit based on a pull-up mirror ratio of a first current, and to generate a pull-down current for the output node of the transistor unit based on a pull-down mirror ratio of a second current; the second transistor unit is configured to generate a pull-up current for the output node of the transistor unit based on a pull-up mirror ratio of a second current, and to generate a pull-down current for the output node of the transistor unit based on a pull-down mirror ratio of a first current; each transistor unit is further configured to determine a voltage signal for the output node of the transistor unit based on the pull-up current and the pull-down current; the set terminal and reset terminal of the RS latch are respectively connected to the output node of one transistor unit, and the RS latch is configured to output an output signal (such as a PWM high-voltage signal PWM_out) based on the set terminal and the reset terminal.

[0016] In some embodiments, the level conversion module further includes two Schmitt triggers, with the output node of each transistor unit connected to an RS latch via a Schmitt trigger. The Schmitt triggers can eliminate input signal jitter, ensuring stable output signals and preventing false triggering caused by noise or minor interference.

[0017] In some embodiments, the pull-up mirror ratio and the pull-down mirror ratio of each transistor unit are different, thereby ensuring that the voltage signal of the output node of each transistor unit has a relatively clear voltage state (i.e., high level or low level).

[0018] As shown in Figure 2, the level conversion circuit 101 includes a level conversion module 13 comprising two transistor units, two Schmitt triggers I2 and I3, two inverters I4 and I5, and an RS latch I6. The first transistor unit includes transistors M3, M4, M15a, M15b, M16, M17, and M18, and the second transistor unit includes transistors M3, M4, M25a, M25b, M26, M27, and M28. The two transistor units reuse transistors M3 and M4. The two common-source, common-gate, and common-drain transistors M15a and M15b can be equivalent to one transistor M15. Similarly, transistors M25a and M25b can be equivalent to one transistor M25. The output node VD of the first transistor unit is connected to the set terminal S of RS latch I6 via Schmitt trigger I2 and inverter I4. The output node VC of the second transistor unit is connected to the reset terminal R of RS latch I6 via Schmitt trigger I3 and inverter I5. The non-inverting output port of RS latch I6 outputs the PWM high-voltage signal PWM_out. The two transistor units, the two Schmitt triggers I2 and I3, the two inverters I4 and I5, and RS latch I6 are located in the high-voltage domain. In some embodiments, whether inverters I4 and I5 are placed before RS latch I6 is related to the operating logic of RS latch, which transistor unit is connected to the reset and set terminals, whether the Schmitt triggers (I2 and I3 are of the same type) are non-inverting or inverting Schmitt triggers, and the relationship between the pull-down mirror ratio k0 and the pull-up mirror ratio k1 of the transistor unit. The final control objective is to ensure that the logic level of the PWM high-voltage signal output by RS latch is the same as the logic level of the PWM low-voltage signal. For example, in Figure 2, I2 and I3 are both inverting Schmitt triggers. Inverters I4 and I5 are provided before RS latch I6. At this time, the bit level logic of the input of Schmitt trigger I2 / I3 is the same as that of the input of RS latch I6. RS latch I6 is a latch composed of inverting OR gates. The set terminal S and the reset terminal R are both active at the high level. Its working logic is as follows: if the set terminal S is active at the high level and the reset terminal R is active at the low level, then the output is active at the high level; if the set terminal S is active at the low level and the reset terminal R is active at the high level, then the output is active at the low level; if both the set terminal S and the reset terminal R are active at the low level, then the original output state remains unchanged.For example, if inverters I4 and I5 are not set before RS latch I6, and I2 and I3 are both inverting Schmitt triggers, meaning the inputs of the Schmitt triggers have the opposite bit level logic to the inputs of RS latch I6, the output node VD is directly connected to the set terminal S of RS latch I6 through Schmitt trigger I2, and the output node VC is directly connected to the reset terminal R of RS latch I6 through Schmitt trigger I3. In this case, RS latch I6 is a latch composed of inverting and gate-type latches, with the set terminal S and the reset terminal R being low-level active. Its operating logic is as follows: if the set terminal S is high-level and the reset terminal R is low-level, then the output is low-level; if the set terminal S is low-level and the reset terminal R is high-level, then the output is high-level; if both the set terminal S and the reset terminal R are high-level, then the original output state remains unchanged.

[0019] In some embodiments, each transistor unit includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, wherein: the first ends of the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are connected to a high-voltage power supply terminal; the second end of the third transistor is connected to the control terminal of the third transistor and receives a first current, the second end of the fourth transistor is connected to the control terminal of the fourth transistor and receives a second current; the second end of the fifth transistor is connected to the first end of the seventh transistor, the control terminal of the seventh transistor, and the control terminal of the eighth transistor, the second end of the sixth transistor is connected to the first end of the eighth transistor, the second ends of the seventh transistor and the second ends of the eighth transistor are connected to a high-voltage ground terminal, the second end of the sixth transistor serves as the output node of the transistor unit, in the first transistor unit, the control terminal of the fifth transistor is connected to the control terminal of the fourth transistor, and the control terminal of the sixth transistor is connected to the control terminal of the third transistor, in the second transistor unit, the control terminal of the fifth transistor is connected to the control terminal of the third transistor, and the control terminal of the sixth transistor is connected to the control terminal of the fourth transistor. The fourth or third transistor connected to the sixth transistor forms a current mirror with the sixth transistor, generating the pull-up current of the output node; the third or fourth transistor connected to the fifth transistor forms a current mirror with the fifth transistor, the fifth transistor and the seventh transistor are in the same current path, the seventh transistor and the eighth transistor form a current mirror, and the third or fourth transistor, the fifth transistor, the seventh transistor and the eighth transistor connected to the fifth transistor generate the pull-down current of the output node.

[0020] In the level conversion circuit 101 shown in FIG. 2, transistor M3 serves as the third transistor, transistor M4 serves as the fourth transistor, equivalent transistor M15 or M25 serves as the fifth transistor, transistor M16 or M26 serves as the sixth transistor, transistor M17 or M27 serves as the seventh transistor, and transistor M18 or M28 serves as the eighth transistor.

[0021] As shown in FIG. 2, the two transistor units are symmetrically connected with respect to the control terminal of the third transistor and the control terminal of the fourth transistor. Specifically, in the first transistor unit, the control terminals of transistors M15a and M15b are connected to the control terminal of transistor M4, and the control terminal of transistor M16 is connected to the control terminal of transistor M3. Transistors M3 and M16 mirror the first current based on a pull-up mirror ratio k1 to generate a pull-up current at an output node VD, while transistors M4, M15a, M15b, M17, and M18 mirror the second current based on a pull-down mirror ratio k0 to generate a pull-down current at VD, and the voltage signal of VD is related to the pull-up current and the pull-down current. In the second transistor unit, the control terminals of transistors M25a and M25b are connected to the control terminal of transistor M3, and the control terminal of transistor M26 is connected to the control terminal of transistor M4. Transistors M4 and M26 mirror the second current based on a pull-up mirror ratio k1 to generate a pull-up current at an output node VC, while transistors M3, M25a, M25b, M27, and M28 mirror the first current based on a pull-down mirror ratio k0 to generate a pull-down current at VC, and the voltage signal of VC is related to the pull-up current and the pull-down current.

[0022] In some embodiments where the level conversion module comprises an RS trigger, the dimensions of corresponding transistors in the two transistor units are identical (for example, M16 and M26). In each transistor unit, the dimensions of the third transistor and the fourth transistor (i.e., M3 and M4) are generally the same, and generally the pull-up mirror ratio k1 and the pull-down mirror ratio k0 of each transistor unit are different, that is, k1 > k0 or k1 < k0. As shown in FIG. 2, in some embodiments, the dimensions of transistors M15b, M16, M17, and M18 in the first transistor unit may be set to be the same. Therefore, after adding transistor M15a, the mirror ratio formed by the combination of transistors M15a, M15b, M17, and M18 in the first transistor unit (the pull-down mirror ratio k0) is greater than the mirror ratio of transistor M16 (the pull-up mirror ratio k1), that is, k1 < k0. Similarly, the dimensions of transistors M25b, M26, M27, and M28 in the second transistor unit may be set to be the same. Therefore, after adding transistor M25a, the mirror ratio formed by the combination of transistors M25a, M25b, M27, and M28 in the second transistor unit (the pull-down mirror ratio k0) is greater than the mirror ratio of transistor M26 (the pull-up mirror ratio k1).

[0023] As shown in Figure 2, the second terminals of the third transistor M3 and the fourth transistor M4 are denoted as VA and VB, respectively. Taking the input signal as PWM_in and the output signal as PWM_out, and applying the level conversion circuit of Figure 2 to Figure 1 as an example, the working process of the level conversion circuit 101 in Figure 2 includes:

[0024] When PWM_in is at the low level, M1 is off, M2 is on and outputs the second current, M3 is off because no current flows through it, VA is at the high level, M25a, M25b, and M16 are off, no current flows through M27, M4 receives the second current, M26 generates the pull-up current of VC based on the mirrored second current of M4 (i.e., mirrored source current of M4), causing VC to go high, at the same time M15a and M15b mirror the second current of M4 (i.e., mirrored source current of M4) to M17, M18 mirrors the drain current of M17 to generate the pull-down current of VD, causing VD to go low. The high level of VC is input to the reset terminal R of RS latch I6 through Schmitt trigger I3 and inverter I5 (VC and the reset terminal R are both high level or both low level). The low level of VD is input to the set terminal S of RS latch I6 through Schmitt trigger I2 and inverter I4 (VD and the set terminal S are both high level or both low level). At this time, the PWM_out output by RS latch I6 is low level, that is, when PWM_in is low level, the PWM_out output by level conversion circuit 101 is low level.

[0025] When PWM_in changes from a low level to a high level, M1 turns on and outputs the first current, M2 turns off, M3 receives the first current, M25a and M25b mirror the first current to M27 based on M3, and M28 mirrors the drain current of M27 to generate the pull-down current of VC, causing VC to be pulled low. At the same time, M16 mirrors the first current to generate the pull-up current of VD, causing VD to be pulled high. The reset terminal R of RS latch I6 is at a low level, and the set terminal S is at a high level. At this time, the PWM_out output by RS latch I6 is at a high level. That is, when PWM_in changes from a low level to a high level, the PWM_out output by the level conversion circuit 101 changes from a low level to a high level.

[0026] After PWM_out becomes a high level, the high-side drive circuit 102 sends a high-side drive signal based on PWM_out to turn on the high-side power transistor MH. At this time, the voltage of the switching node SW is quickly pulled up, and the voltage of the upper plate of the bootstrap capacitor C1 also rises rapidly due to the influence of the voltage of the switching node SW, that is, the voltage of node BST rises rapidly. The rapid voltage rise will cause transistor coupling current to be generated in M3 and M4, which interferes with the voltage of VC and VD. In this embodiment, the first current output based on the bias current is used as the input of the level conversion module 13. Since the bias current is large, the first current is significantly larger than the transistor coupling current. The pull-down current of VC and the pull-up current of VD generated based on the first current will resist the interference of the coupling current.

[0027] Specifically, assuming the actual current flowing through M3 is IS3 (including the first current and the transistor coupling current through M3), and the current flowing through M4 is IS4 (the transistor coupling current through M4), because M2 is off, node VB is a high impedance point, while node VA has a large pull-down current IM1 (i.e., the first current output based on the bias current when M1 is on). VA rises slower than VB. The source-gate voltage of M3 is greater than the source-gate voltage of M4, so IS3 is significantly greater than IS4. Current IS3 is mirrored to M27 through M25a and M25b. M28 then mirrors the drain current of M27 to generate current ID28 at node VC. M26 mirrors IS4 to generate a pull-up mirror interference current IS26 at node VC. ID28 is greater than IS26, and node VC maintains a low level. For node VD, M16 mirrors IS3 to generate current IS16, M15a and M15b mirror IS4 to M17, and M18 mirrors the drain current of M17 to generate a pull-down mirrored interference current ID18 at node VD. It is important to note that although IS3 is greater than IS4, the branch containing M17 has an additional current mirrored by M15a compared to the branch containing M16. Therefore, in specific embodiments, the relationship between IS16 and ID18 may differ for different transistor units (i.e., different magnitudes of generated transistor coupling current, different pull-up mirror ratios, or different pull-down mirror ratios), resulting in different VD levels: If IS16 is greater than ID18, VD maintains a high level, and the output PWM_out of RS latch I6 maintains its original high level, meaning the transistor unit cancels out the interference of the transistor coupling current; if IS16 is less than ID18, VD becomes a low level due to the mirror interference current. Since VC maintains a low level, based on the internal working logic of RS latch I6, the output of RS latch I6 maintains the previous output state, i.e., the output PWM_out is a high level. In this case, RS latch I6 ensures that the change in VD level will not affect the level of PWM_out. In other words, under the interference of transistor coupling current, PWM_out maintains a high level regardless of how the VD level changes.

[0028] In Figure 2, after PWM_out becomes a high level, if the voltage change rate of the switching node SW is very large, resulting in a very large voltage change rate of node VA, the source voltage of the first transistor M1 will be coupled by its drain-source parasitic capacitance to a voltage difference exceeding the low-voltage power supply terminal AVDD minus the threshold voltage of the first transistor M1. As a result, the first transistor M1 changes from being on to being off and no longer outputs the first current. VA and VB have no pull-down path, and only transistor coupling current passes through transistors M3 and M4. Since each transistor unit in Figure 2 has a pull-down mirror ratio k0 greater than the pull-up mirror ratio k1, VC and VD are pulled down to a low level based on the mirror interference current. The reset terminal R and the set terminal S of RS latch I6 are both at a low level, and the output of RS latch I6 maintains the previous output state, that is, the output PWM_out is at a high level.

[0029] When PWM_in changes from a high level to a low level, M1 is turned off, M2 is turned on to output the second current, M4 receives the second current, the first transistor unit mirrors the second current to generate the pull-down current of VD, causing VD to go low, the second transistor unit mirrors the second current to generate the pull-up current of VC, causing VC to go high, the set terminal S of RS latch I6 is at a low level, the reset terminal R is at a high level, and the output PWM_out is at a low level. That is, when PWM_in changes from a high level to a low level, the output PWM_out of the level conversion circuit 101 changes from a high level to a low level.

[0030] After PWM_out becomes low level, the high-side drive circuit 102 sends a high-side drive signal based on PWM_out to turn off the high-side power transistor MH. At the same time, the low-side drive circuit 103 sends a low-side drive signal based on PWM_in to turn on the low-side power transistor ML. At this time, the voltage of the switching node SW is pulled down quickly, and the voltage of node BST drops accordingly. The voltages of nodes VA and VB in Figure 2 are discharged through the body diodes of M3 and M4. M26 changes from on to off. Node VC does not have a pull-up current to maintain its high level and may change from high level to low level. If node VC becomes low level, both inputs of RS flip-flop I6 are low level, and PWM_out maintains the previous output state, that is, the output PWM_out is low level.

[0031] After PWM_out becomes low level, the inductor L in Figure 1 may experience zero-crossing of the inductor current (this can be detected by the zero-crossing detector of the current signal of inductor L. If the inductor L experiences zero-crossing of the inductor current, the zero-crossing detector will output the inductor current zero-crossing signal). As a result, the low-side power transistor ML turns off, node SW resonates, and node BST resonates accordingly. At this time, the voltage of BST rises and falls. When the voltage of BST rises, M3 and M4 generate transistor coupling current. When the voltage of BST falls, M26 changes from on to off.

[0032] If the inductor current L crosses zero, the BST voltage rises, and transistor coupling currents are generated in M3 and M4. The mirror interference current generated by the transistor unit mirroring the transistor coupling current interferes with VC and VD (pulling down VC and pulling up VD). However, the first transistor unit mirrors the second current to generate a pull-down current for VD, and the second transistor unit mirrors the second current to generate a pull-up current for VC. Due to the larger bias current, the second current based on the bias current is significantly larger than the transistor coupling current. The pull-down current for VD and the pull-up current for VC generated based on the second current will resist the interference of the mirror interference current, keeping VC at a high level and VD at a low level, resulting in a low-level output PWM_out. Specifically, even if the second current mirror unit generates a large mirror interference current pulling down VC due to k0, both inputs of RS flip-flop I6 are at a low level, and the signal PWM_out maintains the previous output state, meaning the output PWM_out is at a low level.

[0033] If the inductor current of inductor L crosses zero, the BST voltage drops, and M26 changes from on to off. Since node VC lacks pull-up current to maintain a high level, it may change from a high level to a low level. If node VC changes to a low level, both inputs of RS flip-flop I6 are at a low level, and the output of RS latch I6 maintains the previous output state, meaning the output PWM_out is at a low level.

[0034] As shown in Figure 2, the level conversion circuit 101 may experience interference from the high-voltage domain power supply voltage change rate during the entire process of PWM_in and when the inductor current of inductor L crosses zero. However, the large bias current in the level conversion circuit 101 can resist this interference. If the bias current does not completely cancel out this interference (the VC or VD of the transistor unit changes due to interference, or M1 or M2 is turned off due to interference), based on the unequal relationship between the pull-up and pull-down mirror ratios of each transistor unit and the RS latch I6, it can be ensured that the PWM_out output by the RS latch I6 remains unchanged from the previous output state. That is, the RS latch has an anti-interference effect, and this anti-interference effect is not limited by the direction of the high-voltage domain power supply voltage change.

[0035] Specifically, the purpose of setting the unequal pull-up and pull-down mirror ratios for each transistor unit is to ensure that when both M1 and M2 are turned off, and the transistor unit generates a mirrored interference current by mirroring the transistor coupling current, VC and VD can be in the same and definite level state (both at high level or both at low level). The RS latch is specifically configured to maintain the previous output state unchanged based on the current identical level state of VC and VD. Therefore, the working logic of the RS latch, which transistor unit is connected to the reset and set terminals, the relationship between the pull-down mirror ratio k0 and the pull-up mirror ratio k1 of the transistor unit, whether an inverter is set before the reset and set terminals, and the type of Schmitt trigger are all completely related to the final output PWM_out.

[0036] As shown in Figure 2, in some embodiments, the transistor unit further includes: a first resistor R1 connected between the high-voltage power supply terminal and the second terminal of the third transistor M3; and a second resistor R2 connected between the second terminal of the fourth transistor M4 and the high-voltage ground terminal. When the level conversion module 13 includes two transistor units, these two transistor units can reuse the first resistor R1 and the second resistor R2, as shown in Figure 2. R1 and R2 are used to define the initial state of the output of the level conversion circuit 101. When the level conversion circuit 101 is first powered on, the current bias module 11 has not yet been able to output the bias current normally. R1 pulls up node VA, and R2 pulls down node VB, so that the initial state of the output PWM_out of the level conversion circuit 101 is at a low level. To reduce the impact of R1 and R2 on the subsequent normal operation of the level conversion module 13, R1 and R2 can be selected with larger resistance values.

[0037] As shown in Figure 2, in some embodiments, the transistor unit further includes: a first diode D1, with its cathode connected to the second terminal of the third transistor M3 and its anode connected to the high-voltage ground terminal; and a second diode D2, with its cathode connected to the second terminal of the fourth transistor M4 and its anode connected to the high-voltage ground terminal. These two transistor units can reuse the first diode D1 and the second diode D2. D1 is used to provide gate clamping protection for M3, M16, M25a, and M25b, and D2 is used to provide gate clamping protection for M4, M26, M15a, and M15b, preventing excessive source-gate voltage from causing breakdown when the BST voltage rises.

[0038] In some embodiments, the level conversion module 13 includes a transistor unit configured to: mirror a first current based on a pull-up mirror ratio to generate a pull-up current for the output node of the transistor unit; mirror a second current based on a pull-down mirror ratio to generate a pull-down current for the output node; and determine a voltage signal of the output node as an output signal based on the pull-up current and the pull-down current. Based on the above analysis of the working process in Figure 2, it can be seen that if the voltage change rate of the floating voltage of the bootstrap capacitor C1 is large, the interference to the level conversion circuit 101 is manifested as transistor coupling current. However, if the voltage change rate is not large enough to cause M1 or M2 to be affected by coupling and turn off, in this case, a suitable pull-down mirror ratio k0 and pull-up mirror ratio k1 can be set. The pull-up current or pull-down current of VD can directly resist the interference of the mirror interference current. At this time, the logic level of the voltage signal of node VD is the same as that of PWM_in, and it can be directly used as the PWM high voltage signal PWM_out. Therefore, in some cases, only one transistor unit can be set in the level conversion module 13, and RS flip-flops are not required. Alternatively, a Schmitt trigger and / or inverter can be added after the output node of the transistor voltage, and the PWM high voltage signal can be output by the Schmitt trigger or inverter. In this case, RS flip-flops are not required.

[0039] When the level conversion module 13 does not include an RS flip-flop and uses the voltage signal of the output node of a transistor unit as the output signal, the ratio of the pull-up mirror ratio to the pull-down mirror ratio of the transistor unit is within a preset range including 1. This ensures that when the transistor unit generates a transistor coupling current due to changes in the power supply voltage in the high-voltage domain, the voltage signal of the output node remains unchanged. For example, 1-a≤r and r≤1 / (1-a), where r=k1 / k0, 0≤a<1. Assuming that the transistor unit mirrors the first current to generate the pull-up current of VD and mirrors the transistor coupling current to generate the mirror interference current of VD, the ratio r should ensure that this pull-up current can resist the interference of the mirror interference current, thereby resisting the interference of the transistor coupling current. The same applies to the case where the transistor unit mirrors the second current to generate the pull-down current of VD. At this point, a current bias module 11 can typically be set so that the amplitude of the first or second current generated based on the bias current is significantly greater than the transistor coupling current. This allows for a direct setting of the ratio r=1, achieved by setting the fifth and sixth transistors to have the same dimensions, and the seventh and eighth transistors to have the same dimensions. Alternatively, transistors of other sizes can be selected to implement the transistor unit, as long as r is within a preset range.

[0040] In an embodiment where the level conversion module 13 includes an RS flip-flop and the RS flip-flop outputs an output signal, the ratio of the pull-up mirror ratio to the pull-down mirror ratio of each transistor unit can be located within a preset range including 1, so that when each transistor unit generates a transistor coupling current due to a change in the power supply voltage in the high voltage domain, the output signal of the RS flip-flop remains unchanged. However, the pull-up mirror ratio and the pull-down mirror ratio are preferably unequal to ensure that VC / VD has a definite level state, especially when M1 and M2 are both off and the transistor unit generates a mirrored interference current by mirroring the transistor coupling current. VC and VD can be in the same and definite level state (both high level or both low level), so that the RS latch maintains the previous output state based on the current identical level state of VC and VD. At this time, the ratio r can also be set to a certain value range so that when each transistor unit generates a transistor coupling current due to a change in the voltage of the switching node, the output signal of the RS flip-flop maintains the previous output state. The logic level of the output signal is the same as the logic level of the input signal, and the value in this value range is close to 1 but does not include 1.

[0041] As shown in Figure 2, the pull-down current and pull-up current mentioned in this embodiment mainly refer to the current located at the output node VC or VD generated by the first current or the second current through the transistor unit mirror.

[0042] As shown in Figure 2, the current bias module 11 includes: a bias current source I0, configured to output an initial current; and a bias current mirror, configured to mirror the initial current to generate an initial mirror current, wherein the bias current is determined based on the initial mirror current. Specifically, the bias current mirror includes a current control transistor and a current controlled transistor, wherein the first terminal of the bias current source is connected to the low-voltage power supply terminal AVDD, the second terminal of the bias current source is connected to the first terminal of the current control transistor, the first terminal of the current control transistor is also connected to the control terminal of the current control transistor and the control terminal of the current controlled transistor, the first terminal of the current controlled transistor outputs the initial mirror current, and the second terminals of the current control transistor and the current controlled transistor are connected to the low-voltage ground terminal AVSS. When the control module 12 includes a first transistor M1 and a second transistor M2, the current-controlled transistors may include a first current-controlled transistor M31 and a second current-controlled transistor M32. The first terminal of the first current-controlled transistor M31 is connected to the first terminal of the first transistor M1, and the first terminal of the second current-controlled transistor M32 is connected to the first terminal of the second transistor M2. The current control transistor M30, the first current-controlled transistor M31, and the second current-controlled transistor M32 all form a current mirror. Both the first current-controlled transistor M31 and the second current-controlled transistor M32 generate an initial mirror current based on the initial current. The first transistor M1 uses the received initial mirror current from the first current-controlled transistor M31 as its bias current, and the second transistor M2 uses the received initial mirror current from the second current-controlled transistor M32 as its bias current. The number and structure of the current control transistors and current-controlled transistors in the bias current mirror can be set according to actual conditions and are not limited here.

[0043] In some embodiments, the current bias module 11 is specifically configured to: generate a pulse signal based on at least one of an input signal or an external detection signal; and output a bias current based on the pulse signal. The external monitoring signal is used to indicate the circuit state of the external circuit connected to the level conversion circuit. For example, the inductor current zero-crossing signal is used to indicate that the current of the inductor L connected to the switching node in FIG1 has crossed zero, and can be used as an external detection signal. When the level conversion circuit 101 shown in FIG2 is applied to FIG1, the bias current is mainly used to resist the interference of the voltage change rate dV / dt of the switching node SW, and at the same time accelerate the signal transmission. Therefore, the bias current should have a large amplitude during the time period when the interference occurs. If the bias current maintains a large amplitude throughout all time periods, the power consumption of the entire circuit will be large. Therefore, it is possible to consider adjusting the magnitude of the bias current based on the time period when the interference occurs to reduce the power consumption. That is, when the voltage of the switching node SW is relatively stable, the interference has not occurred, or the interference has been eliminated, the current bias module 11 outputs a relatively small bias current. When the PWM_in signal changes or the interference occurs, the current bias module 11 outputs a larger bias current.

[0044] In Figure 2, assuming the pulse is at a high level, the current bias module 11 outputs a relatively large bias current when the pulse signal is at a high level, and a relatively small bias current when the pulse signal is at a low level. The pulse duty cycle of the pulse signal is less than the duty cycle of the PWM low-voltage signal PWM_in; otherwise, the effect of reducing circuit power consumption cannot be achieved. The pulse width of the pulse signal should not be less than the interference duration caused by the voltage change of the switching node SW, so that a large bias current provides support for the level conversion module 13 throughout the entire interference period.

[0045] In some specific embodiments, the pulse signal includes at least one of the following: a first pulse signal that generates a pulse when the rising edge of the input signal is detected, a second pulse signal that generates a pulse when the falling edge of the input signal is detected, and a third pulse signal that generates a pulse when the pulse start change edge of the external monitoring signal is detected.

[0046] In some embodiments, the current bias module further includes a pulse generation unit configured to generate a pulse signal based on at least one of an input signal or an external detection signal, wherein the external detection signal is used to indicate the circuit state of an external circuit connected to the level conversion circuit; and the bias current mirror further includes: a pulse-controlled transistor configured to generate a pulse current by mirroring an initial current based on a current control transistor in an on state; and a pulse control transistor configured to control the on / off state of the pulse-controlled transistor based on a pulse signal, wherein the bias current is the sum of the pulse current and the initial mirrored current. The pulse signal generated by the pulse generation unit includes at least one of the first pulse signal, the second pulse signal, and the third pulse signal mentioned above.

[0047] As shown in Figure 2, when the current-controlled transistor includes a first current-controlled transistor M31 and a second current-controlled transistor M32, the pulse-controlled transistor includes a first pulse-controlled transistor M33 and a second pulse-controlled transistor M34, and the pulse control transistor includes a first pulse control transistor M35 and a second pulse control transistor M36.

[0048] In some embodiments, the pulse-controlled transistor and the pulse control transistor are connected in series across the current-controlled transistor, and the control terminal of the pulse-controlled transistor is connected to the control terminal of the current control transistor. For example, in Figure 2, M33 and M35 are connected in series across M31, M33 and M30 share a common gate, M34 and M36 are connected in series across M32, and M34 and M30 share a common gate. In this case, the bias current is the sum of the pulse current and the initial mirror current.

[0049] Figure 3 shows a schematic diagram of a pulse generation unit. As shown in Figure 3, assuming the input signal is PWM_in and the external monitoring signal is the inductor current zero-crossing signal, the pulse generation unit includes three pulse generators (I7, I9, I10), an inverter I8, and an OR gate I11. Each pulse generator generates a pulse with a fixed pulse width based on the rising edge of the input signal. Specifically, pulse generator I7 receives PWM_in and outputs a first pulse signal as the on_pulse signal, and the control terminal of the first pulse control transistor M35 receives the on_pulse signal; pulse generator I9 receives PWM_in through inverter I8 and outputs a second pulse signal; pulse generator I10 outputs a third pulse signal; and OR gate I11 performs an OR logic operation on the second and third pulse signals and outputs an off_pulse signal, which is received by the control terminal of the second pulse control transistor M36.

[0050] Figure 4 shows a waveform diagram of the signal in Figure 3. As shown in Figure 4, the rising edge of PWM_in triggers the on_pulse signal to generate a pulse, the falling edge of PWM_in triggers the off_pulse signal to generate a pulse, and the rising edge (pulse start change edge) of the zero-crossing signal of the inductor current triggers the off_pulse signal to generate a pulse. When the on_pulse signal is at a low level, the current received by the first transistor M1 only includes the bias current generated by the first current-controlled transistor M31; when the on_pulse signal is at a high level, the first pulse control transistor M35 is turned on, causing the first pulse-controlled transistor M33 to generate a pulse current based on the initial current. At this time, the current received by the first transistor M1 includes the pulse current generated by the first pulse-controlled transistor M33 and the original bias current generated by the first current-controlled transistor M31. The operation of the off_pulse signal is the same as that of the on_pulse signal.

[0051] In Figure 2, a larger bias current can adjust the levels of VC and VD more quickly, thereby accelerating the level switching speed of PWM_out and achieving low transmission delay. For example, after PWM_in changes from a low level to a high level, a larger bias current can adjust the levels of VC and VD more quickly, so that PWM_out can change from a low level to a high level more quickly.

[0052] In conventional level-switching circuits (such as those with cross-coupling in high-voltage clamp positions), the operating voltage in the high-voltage domain (the voltage difference between BST and SW) is required to be at least the sum of two gate-source voltages. In Figure 2, based on the transistor cell structure, the high-voltage domain operating voltage required for the level-switching circuit 101 is lower, only needing to be no less than the sum of one gate-source voltage and one overdrive voltage. In comparison, the operating voltage requirement for the level-switching circuit 101 in this embodiment is significantly lower.

[0053] In Figure 2, M3, M4, M15a, M15b, M16, M25a, M25b, and M26 are all implemented using P-channel field-effect transistors, while M30, M31, M32, M33, M34, M35, M36, M1, M2, M17, M18, M27, and M28 are all implemented using N-channel field-effect transistors. Due to the high BST node voltage, the voltage difference between the drain and source of M1 and M2 is relatively large. Therefore, M1 and M2 are usually high-voltage resistant N-channel field-effect transistors.

[0054] This invention can be implemented in other specific forms without departing from its spirit and essential characteristics. For example, the algorithm described in a particular embodiment may be modified without departing from the basic spirit of the invention. Therefore, the present embodiments are to be regarded as exemplary rather than limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and all changes falling within the meaning of the claims and their equivalents are thus included within the scope of the invention.

[0055] 100: DC / DC converter 101: Level Conversion Circuit 102: High-side drive circuit 103: Low-side drive circuit 11: Current bias module 12: Control Module 13: Level Conversion Module AVDD: Low-voltage power supply terminal AVSS: Low-voltage grounding terminal BST, SW, VA, VB, VD, VC: Nodes C1: Bootstrap capacitor C2: Output capacitor CLR, R: Reset pin D1: First Dipolar Body D2: Second Dipolar Body I0: Bias current source I1, I4, I5, I8: Inverters I11: or gate I2, I3: Schmitt trigger I6:RS latch I7, I9, I10: Pulse generator IM1: Pull-down current IS26, ID18: Image interference current IS3, IS4, ID28, IS16: Current L: Inductance M1: First transistor M2: Second transistor M3, M4, M15, M15a, M15b, M16, M17, M18, M25, M25a, M25b, M26, M27, M28: Transistors M30: Current control transistor M31: First current-controlled transistor M32: Second current-controlled transistor M33: First pulse controlled transistor M34: Second Pulse Controlled Transistor M35: First pulse control transistor M36: Second pulse control transistor MH: High-side power transistor ML: Low-side power transistor on_pulse, off_pulse, PWM_out: signal PWM_in: PWM low-voltage signal Q: RS latch output terminal R1: First resistor R2: Second resistor S, SET: Set pin VIN: Input power VOUT: Output voltage Z1, Z2: Zener diodes

Claims

1. A level conversion circuit, comprising: The current bias module is configured to output bias current; The control module is configured to output a second control current based on the bias current under the control of an input signal located in the low voltage domain; And a level conversion module, configured to output an output signal in the high voltage domain based on a first control current, the logic level of the output signal being the same as the logic level of the input signal.

2. The level conversion circuit as described in claim 1, wherein, The control module includes a first transistor, a second transistor, and an inverter. The control terminal of the first transistor and the input terminal of the inverter receive the input signal. The control terminal of the second transistor is connected to the output terminal of the inverter. The first terminal of the first transistor and the first terminal of the second transistor are connected to the current bias module. The second terminal of the first transistor outputs the first current, and the second terminal of the second transistor outputs the second current.

3. The level conversion circuit as described in claim 2, wherein, The control module also includes a Zener diode, the cathode of which is connected to the first terminal of the first transistor or the second transistor, and the anode of which is connected to the low-voltage ground terminal of the low-voltage domain.

4. The level conversion circuit as described in claim 1, wherein, The level conversion module includes two transistor units and an RS latch, wherein: the first transistor unit is configured to mirror the first current based on a pull-up mirror ratio to generate a pull-up current for the output node of the transistor unit, and mirror the second current based on a pull-down mirror ratio to generate a pull-down current for the output node of the transistor unit; the second transistor unit is configured to mirror the second current based on the pull-up mirror ratio to generate a pull-up current for the output node of the transistor unit, and mirror the first current based on a pull-down mirror ratio to generate a pull-down current for the output node of the transistor unit; each transistor unit is further configured to determine a voltage signal for the output node of the transistor unit based on the pull-up current and the pull-down current; the set and reset terminals of the RS latch are respectively connected to the output node of one of the transistor units, and the RS latch is configured to output the output signal based on the set and reset terminals.

5. The level conversion circuit as described in claim 4, wherein, The level conversion module also includes two Schmitt triggers, and the output node of each of the two transistor units is connected to the RS latch through one of the Schmitt triggers.

6. The level conversion circuit as claimed in claim 4, wherein the pull-up mirror ratio of each of the two transistor units is different from the pull-down mirror ratio.

7. The level switching circuit as claimed in claim 4, wherein each of the two transistor units comprises a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, and wherein: The first terminals of the third, fourth, fifth, and sixth transistors are connected to the high-voltage power supply terminal of the high-voltage domain. The second terminal of the third transistor is connected to the control terminal of the third transistor and receives the first current. The second terminal of the fourth transistor is connected to the control terminal of the fourth transistor and receives the second current. The second terminal of the fifth transistor is connected to the first terminal of the seventh transistor, the control terminal of the seventh transistor, and the control terminal of the eighth transistor. The second terminal of the sixth transistor is connected to the first terminal of the eighth transistor. The second terminals of the seventh and eighth transistors are connected to the high-voltage ground terminal of the high-voltage domain. The second terminal of the sixth transistor serves as the output node of its respective transistor unit. In the first transistor unit of the two transistor units, the control terminal of the fifth transistor is connected to the control terminal of the fourth transistor, and the control terminal of the sixth transistor is connected to the control terminal of the third transistor. In the second transistor unit of the two transistor units, the control terminal of the fifth transistor is connected to the control terminal of the third transistor, and the control terminal of the sixth transistor is connected to the control terminal of the fourth transistor.

8. The level conversion circuit as described in claim 1, wherein, The level conversion module includes a transistor unit, which is configured to: mirror the first current based on a pull-up mirror ratio to generate a pull-up current at the output node of the transistor unit; The second current is mirrored based on the pull-down mirror ratio to generate the pull-down current of the output node; The voltage signal of the output node is determined based on the pull-up current and the pull-down current as the output signal.

9. The level conversion circuit as described in claim 8, wherein, The ratio of the pull-up mirror ratio to the pull-down mirror ratio is within a preset range including 1, so that when the transistor unit generates transistor coupling current due to the power supply voltage change in the high voltage domain, the voltage signal of the output node remains unchanged.

10. The level conversion circuit as described in claim 8, wherein, The transistor unit includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, wherein: the first terminals of the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are connected to the high-voltage power supply terminal of the high-voltage domain; the second terminal of the third transistor is connected to the control terminal of the third transistor and receives the first current; the second terminal of the fourth transistor is connected to the control terminal of the fourth transistor and receives the second current; the second terminal of the fifth transistor is connected to the first terminal of the seventh transistor, the control terminal of the seventh transistor, and the control terminal of the eighth transistor; the second terminal of the sixth transistor is connected to the first terminal of the eighth transistor; the second terminals of the seventh transistor and the eighth transistor are connected to the high-voltage ground terminal of the high-voltage domain; the control terminal of the fifth transistor is connected to the control terminal of the fourth transistor; the control terminal of the sixth transistor is connected to the control terminal of the third transistor; and the second terminal of the sixth transistor serves as the output node of the transistor unit.

11. The level conversion circuit as described in claim 7 or 10, wherein, The transistor unit further includes: a first resistor connected between the high-voltage power supply terminal and the second terminal of the third transistor; and a second resistor connected between the second terminal of the fourth transistor and the high-voltage ground terminal.

12. The level conversion circuit as described in claim 1, wherein, The current bias module is specifically configured to: generate a pulse signal based on at least one of the input signal or an external monitoring signal; and output the bias current based on the pulse signal, wherein the external monitoring signal is used to indicate the circuit status of an external circuit connected to the level conversion circuit.

13. The level conversion circuit as described in claim 12, wherein, The pulse signal includes at least one of the following: a first pulse signal that generates a pulse when the rising edge of the input signal is detected, a second pulse signal that generates a pulse when the falling edge of the input signal is detected, and a third pulse signal that generates a pulse when the pulse start change edge of an external monitoring signal is detected.

14. The level conversion circuit as described in claim 1, wherein, The current bias module includes: a bias current source configured to output an initial current; and a bias current mirror configured to mirror the initial current to generate an initial mirror current, the bias current being determined based on the initial mirror current.

15. The level conversion circuit as described in claim 14, wherein, The bias current mirror includes a current control transistor and a current controlled transistor, wherein a first terminal of the bias current source is connected to the low-voltage power supply terminal of the low-voltage domain, a second terminal of the bias current source is connected to the first terminal of the current control transistor, the first terminal of the current control transistor is also connected to the control terminal of the current control transistor and the control terminal of the current controlled transistor, the first terminal of the current controlled transistor outputs the initial mirror current, and the second terminals of the current control transistor and the second terminal of the current controlled transistor are connected to the low-voltage ground terminal of the low-voltage domain.

16. The level conversion circuit as described in claim 15, wherein, The current bias module further includes a pulse generation unit configured to generate a pulse signal based on at least one of the input signal or an external monitoring signal, wherein the external monitoring signal is used to indicate the circuit state of an external circuit connected to the level conversion circuit. Furthermore, the bias current mirror further includes: a pulse-controlled transistor, configured to, in the on state, mirror the initial current based on the current-controlled transistor to generate a pulse current; And a pulse control transistor, configured to control the on / off state of the pulse controlled transistor based on the pulse signal, wherein the bias current is the sum of the pulse current and the initial mirror current.

17. The level conversion circuit as described in claim 16, wherein, The pulse-controlled transistor and the pulse control transistor are connected in series across the two ends of the current-controlled transistor, and the control terminal of the pulse-controlled transistor is connected to the control terminal of the current control transistor.

18. A DC / DC converter connected to a bootstrap capacitor, the DC / DC converter comprising a level switching circuit, a high-side drive circuit, and a high-side power transistor as described in any one of claims 1 to 17, wherein, The high-side drive circuit is configured to output a high-side drive signal located in the high voltage domain based on the output signal of the level conversion circuit; the high-side power transistor is configured to switch on and off based on the high-side drive signal to control the voltage of the bootstrap capacitor; the bootstrap capacitor provides a high voltage domain to the level conversion circuit and the high-side drive circuit based on the voltage.

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