Clock data recovery circuit

Abstract

A clock data recovery circuit uses an edge detector to sense the rising and falling edges of the input data, and employs the resulting edge detection signal as the input for subsequent circuitry to obtain a clock signal at the correct frequency. This circuit further adjusts the clock signal's frequency using a fine tuning mechanism via a phase detector and a coarse tuning mechanism via a frequency detector, thereby achieving both a wide tuning range and precise frequency locking.

Description

[Technical Field]

[0001] The present invention relates to a clock data recovery circuit, and more particularly to a clock data recovery circuit having an edge detector. [Previous Technology]

[0002] The Internet has gradually shifted to using fiber optics as the data transmission medium. However, data transmission via fiber optics can result in clock asynchrony or noise. Therefore, a clock recovery circuit is needed at the receiving end to eliminate clock jitter and restore a distortion-free data signal. If the clock recovery circuit can operate over a wide frequency detection range, it will provide fiber optic networks with great flexibility, allowing many standards to be met using a single chip and reducing the cost of external components such as capacitors or crystal oscillators. Common methods for achieving a wide frequency detection range include using a frequency calibrator or a rotating frequency detector to acquire the frequency. However, both methods require trade-offs between noise suppression and lock-in range, resulting in bandwidth limitations. [Summary of the Invention]

[0003] The main objective of this invention is to control the frequency of a voltage-controlled oscillator by using a phase detector and the fine-tuning voltage output from the first charge pump, and a frequency detector and the coarse-tuning voltage output from the second charge pump, thereby achieving the effects of fast locking and wide frequency modulation range. Furthermore, by using the edge detection signal of the edge detector, the clock signal output by the voltage-controlled oscillator can have the best sampling point for data recovery, resulting in greater jitter tolerance and the lowest bit error rate.

[0004] A clock data recovery circuit according to the present invention includes an edge detector, a phase detector, a frequency detector, a hysteresis-locked detector, a first charge pump, a second charge pump, a voltage-controlled oscillator, a frequency up / down control circuit, and a decision circuit. The edge detector receives input data to detect the positive and negative edges of the input data, and outputs an edge detection signal. The phase detector receives the input data and a co-phase clock signal, and is used to detect the co-phase clock signal and the... The frequency detector is electrically connected to the edge detector to receive the edge detection signal. The frequency detector also receives the in-phase clock signal and a quadrature clock signal. The frequency detector is used to detect the frequency relationship between the in-phase clock signal and the edge detection signal and outputs a frequency detection signal. The hysteresis-locked detector is electrically connected to the edge detector to receive the edge detection signal. The hysteresis-locked detector also receives the in-phase clock signal. The hysteresis-locked detector is used to determine... The frequency difference between the in-phase clock signal and the edge detection signal generates a lock signal that is sent to the phase detector and the frequency detector. The first charge pump is electrically connected to the phase detector to receive the phase detection signal, and the first charge pump outputs a fine-tuning voltage via a loop filter. The second charge pump is electrically connected to the frequency detector to receive the frequency detection signal, and the second charge pump charges or discharges a capacitor according to the frequency detection signal to output a coarse-tuning voltage. The voltage-controlled oscillator is electrically connected to the first charge pump and the second... The charging pump receives the coarse adjustment voltage and the fine adjustment voltage, and the voltage-controlled oscillator outputs the in-phase clock signal and the quadrature clock signal. The frequency up / down control circuit receives the in-phase clock signal and the edge detection signal, and the frequency up / down control circuit outputs a frequency up / down control signal to the frequency detector. The decision circuit is electrically connected to the voltage-controlled oscillator to receive the in-phase clock signal. The decision circuit also receives the input data, and the decision circuit recovers the input data into output data using the in-phase clock signal.

[0005] The present invention uses the edge detector to detect the positive and negative edges of the input data so that the in-phase clock signal obtained in subsequent processing has the correct sampling frequency. The phase detector and the frequency detector adjust the frequency of the in-phase clock signal through fine adjustment mechanism and coarse adjustment mechanism respectively, so as to have the effects of wide frequency modulation range and accurate frequency locking at the same time.

Implementation Method

[0006] Please refer to Figure 1, which is a functional block diagram of a clock data recovery circuit 100 according to one embodiment of the present invention. The clock data recovery circuit 100 includes an edge detector 110, a phase detector 120, a frequency detector 130, a hysteresis-locked detector 140, a first charge pump 150, a second charge pump 160, a voltage-controlled oscillator 170, a frequency up / down control circuit 180, and a decision circuit 190.

[0007] Referring to Figure 1, the edge detector 110 receives input data Di, detects the positive and negative edges of the input data Di, and outputs an edge detection signal ED. Referring to Figure 2, in this embodiment, the edge detector 110 has a first delay unit 111 and a first XOR gate 112. The first delay unit 111 receives the input data Di and outputs delayed data Dd. The first XOR gate 112 is electrically connected to the first delay unit 111 to receive the delayed data Dd. The first XOR gate 112 also receives the input data Di and outputs the edge detection signal ED. In this embodiment, by performing an XOR logic operation on the input data Di and the delayed data Dd using the first XOR gate 112, the potential of the edge detection signal ED can rise to a high potential at both the positive and negative edges of the delayed data Dd, thereby achieving the detection of positive and negative edges and ensuring that the subsequently generated clock signal has the optimal sampling point.

[0008] Referring to Figure 1, the phase detector 120 receives the input data Di and a co-phase clock signal clkI. The phase detector 120 detects the phase relationship between the co-phase clock signal clkI and the input data Di and outputs a first phase detection signal PD_u and a second phase detection signal PD_n. Referring to Figure 3, in this embodiment, the phase detector 120 has a first D-type flip-flop 121, a second D-type flip-flop 122, a second XOR gate 123, and a third XOR gate 124. The first D-type flip-flop 121 receives the input data Di and the co-phase clock signal clkI, and the first D-type flip-flop 121 is triggered by the positive edge of the co-phase clock signal clkI to store the potential of the input data Di and output a first output signal S1. The second D-type flip-flop 122 is electrically connected to the first D-type flip-flop 121 to receive the first output signal S1. The second D-type flip-flop 122 also receives the in-phase clock signal clkI. Triggered by the negative edge of the in-phase clock signal clkI, the second D-type flip-flop 122 stores the potential of the first output signal S1 and outputs the second output signal S2. The second XOR gate 123 is electrically connected to the first D-type flip-flop 121 to receive the first output signal S1. The second XOR gate 123 also receives the input data Di. The second XOR gate 123 performs an XOR logic operation on the first output signal S1 and the input data Di to output an error pulse Err. The third XOR gate 124 is electrically connected to the first D-type flip-flop 121 and the second D-type flip-flop 122 to receive the first output signal S1 and the second output signal S2. The third XOR gate 124 performs XOR logic operation on the first output signal S1 and the second output signal S2 to output a reference pulse Ref.

[0009] Please refer to Figures 4a and 4b, which are timing diagrams of the phase detector 120. In Figure 4a, the in-phase clock signal clkI lags behind the input data Di. The first D-type flip-flop 121 is triggered by the positive edge of the in-phase clock signal clkI and stores the potential of the input data Di to obtain the first output signal S1. The second D-type flip-flop 122 is triggered by the negative edge of the in-phase clock signal clkI and stores the potential of the first output signal S1 to obtain the second output signal S2. Since the input signal of the second D-type flip-flop 122 is the first output signal S1 output by the first D-type flip-flop 121, the potential stored by the second D-type flip-flop 122 when triggered by the negative edge of the in-phase clock signal clkI is the potential of the input data Di stored when triggered by the previous positive edge of the in-phase clock signal clkI. Next, through the XOR logic operation of the second XOR gate 123 and the third XOR gate 124, the high-potential time of the reference pulse Ref when the in-phase clock signal clkI lags behind the input data Di will be longer than that of the error pulse Err. Conversely, referring to Figure 4b, when the in-phase clock signal clkI leads the input data Di, the high-potential time of the error pulse Err obtained through the logic operation of the first D-type flip-flop 121, the second D-type flip-flop 122, the second XOR gate 123, and the third XOR gate 124 will be longer than that of the reference pulse Ref. This allows the phase relationship between the in-phase clock signal clkI and the input data Di to be measured.

[0010] Referring again to Figure 3, preferably, in this embodiment, the phase detector 120 has a second delay unit 125, a first XOR gate 126, and a second XOR gate 127. The second XOR gate 123 receives the input data Di via the second delay unit 125. The second delay unit 125 delays the input data Di to prevent the input data Di from being out of sync with the first output signal S1 due to the delay of the D-type flip-flop. The first XOR gate 126 is electrically connected to the second XOR gate 123 to receive the error pulse Err. The first XOR gate 126 also receives an inverted reset signal rstb and outputs the first phase detection signal PD_u. The second XOR gate 127 is electrically connected to the third XOR gate 124 to receive the reference pulse Ref. The second XOR gate 127 also receives the inverted reset signal rstb and outputs the second phase detection signal PD_n. In this embodiment, the first gate 126 and the second gate 127 are controlled by the inverted reset signal rstb, which can prevent the frequency detector 130 from being affected by the phase detector 120 when it is detecting.

[0011] Please refer to Figures 1 and 3. The first charge pump 150 is electrically connected to the phase detector 120 to receive the first and second phase detection signals PD_u and PD_n, and the first charge pump 150 outputs a fine-tuning voltage Vf via a loop filter LF. In this embodiment, the first charge pump 150 has a first current source 151, a first switch 152, a second switch 153, a second current source 154, and a first charging capacitor 155. The two ends of the first switch 152 are electrically connected to the first current source 151 and a charging node n1, respectively. The first switch 152 is also electrically connected to the first gate 126 to receive the first phase detection signal FD_u and is controlled by the first phase detection signal FD_u. The two ends of the second switch 153 are electrically connected to the charging node n1 and the second current source 154, respectively. The second switch 153 is also electrically connected to the second gate 127 to receive and be controlled by the second phase detection signal FD_n. The first charging capacitor 155 is electrically connected to the charging node n1 and is charged via the first current source 151 and the first switch 152 or discharged via the second switch 153 and the second current source 154. The first charging capacitor 155 generates a charging voltage at the charging node n1. This charging voltage is filtered by the loop filter LF and then output as the fine-tuning voltage Vf.

[0012] Please refer to Figures 3 and 4a. Because the high-potential time of the error pulse Err when the in-phase clock signal clkI lags behind the input data Di is shorter than that of the reference pulse Ref, the on-time of the first switch 152 will be shorter than that of the second switch 153, causing the potential of the fine-tuning voltage Vf to gradually decrease due to discharge. Please refer to Figures 3 and 4b. Because the high-potential time of the error pulse Err when the in-phase clock signal clkI leads the input data Di is longer than that of the reference pulse Ref, the on-time of the first switch 152 will be longer than that of the second switch 153, causing the potential of the fine-tuning voltage Vf to gradually increase due to charging.

[0013] Please refer to Figure 1. The frequency detector 130 is electrically connected to the edge detector 110 to receive the edge detection signal ED. The frequency detector 130 also receives the in-phase clock signal clkI and a quadrature clock signal clkQ. The frequency detector 130 is used to detect the frequency relationship between the in-phase clock signal clkI and the edge detection signal ED and outputs a first frequency detection signal FD_u and a second frequency detection signal FD_n.

[0014] Please refer to Figure 5. In this embodiment, the frequency detector 130 has a digitally corrected frequency detector 131 and a frequency detection selection circuit 132. The digitally corrected frequency detector 131 is electrically connected to the edge detector 110 and the voltage-controlled oscillator 170 to receive the edge detection signal ED, the in-phase clock signal clkI, and the quadrature clock signal clkQ. The digitally corrected frequency detector 131 outputs a first rising signal up1 and a first falling signal dn1. In this embodiment, the digitally corrected frequency detector 131 has a fifth D-type flip-flop 131a, a sixth D-type flip-flop 131b, a seventh D-type flip-flop 131c, an eighth D-type flip-flop 131d, a ninth D-type flip-flop 131e, a tenth D-type flip-flop 131f, and a gate logic unit 131g. The input and clock terminals of the fifth D-type flip-flop 131a receive the in-phase clock signal clkI and the edge detection signal ED, respectively. Triggered by the edge detection signal ED, the fifth D-type flip-flop 131a stores the potential of the in-phase clock signal clkI and outputs a first potential signal E. The input and clock terminals of the sixth D-type flip-flop 131b receive the quadrature clock signal clkQ and the edge detection signal ED, respectively. Triggered by the edge detection signal ED, the sixth D-type flip-flop 131b stores the potential of the quadrature clock signal clkQ and outputs a second potential signal F. The input and clock terminals of the seventh type D flip-flop 131c are electrically connected to the output terminal of the fifth type D flip-flop 131a and receive the in-phase clock signal clkI, respectively. Triggered by the in-phase clock signal clkI, the seventh type D flip-flop 131c stores the potential of the first potential signal E and outputs a third potential signal C. The input and clock terminals of the eighth type D flip-flop 131d are electrically connected to the output terminal of the sixth type D flip-flop 131b and receive the in-phase clock signal clkI, respectively. Triggered by the in-phase clock signal clkI, the eighth type D flip-flop 131d stores the potential of the second potential signal F and outputs a fourth potential signal D. The input and clock terminals of the ninth type D flip-flop 131e are electrically connected to the output terminal of the seventh type D flip-flop 131c and receive the in-phase clock signal clkI, respectively. Triggered by the in-phase clock signal clkI, the ninth type D flip-flop 131e stores the potential of the third potential signal C and outputs a fifth potential signal A. The input and clock terminals of the tenth type D flip-flop 131f are electrically connected to the output terminal of the eighth type D flip-flop 131d and receive the in-phase clock signal clkI, respectively. Triggered by the in-phase clock signal clkI, the tenth type D flip-flop 131f stores the potential of the fourth potential signal D and outputs a sixth potential signal B.The gate logic unit 131g is electrically connected to the seventh type D flip-flop 131c, the eighth type D flip-flop 131d, the ninth type D flip-flop 131e, and the tenth type D flip-flop 131f, and the gate logic unit 131g outputs the first rising signal up1 and the first falling signal dn1. Specifically, when the second potential signal F is low and the first potential signal E rises from low to high, the first rising signal up1 rises to high; and when the second potential signal F is low and the first potential signal E falls from high to low, the first falling signal dn1 rises to high.

[0015] Please refer to Figures 6a and 6b, which are diagrams showing the relationship between the timing and state of the edge detection signal ED, the in-phase clock signal clkI, and the quadrature clock signal clkQ. State I is defined as when both the in-phase clock signal clkI and the quadrature clock signal clkQ are at low potentials. State II is defined as when the in-phase clock signal clkI is at low potentials and the quadrature clock signal clkQ is at high potentials. State III is defined as when both the in-phase clock signal clkI and the quadrature clock signal clkQ are at high potentials. State IV is defined as when the in-phase clock signal clkI is at high potentials and the quadrature clock signal clkQ is at low potentials. Please refer to Figure 6a. When the state changes sequentially between I, II, III, and IV, it indicates that the rate of the edge detection signal ED leads the rate of the in-phase clock signal clkI. Please refer to Figure 6b. When the state changes sequentially between IV, III, II, and I, it indicates that the rate of the edge detection signal ED lags behind the rate of the in-phase clock signal clkI. The frequency relationship between the edge detection signal ED, the in-phase clock signal clkI, and the quadrature clock signal clkQ can be measured by the logic operation of the digitally corrected frequency detector 131.

[0016] Please refer to Figures 1 and 5. The frequency detection selection circuit 132 is electrically connected to the edge detector 110, the voltage-controlled oscillator 170, the digitally corrected frequency detector 131, the hysteresis-locked detector 140, and the frequency up / down control circuit 180. The frequency detection selection circuit 132 receives the edge detection signal ED, the in-phase clock signal clkI, a lock signal L, and a frequency up / down control signal UP / DN. The frequency detection selection circuit 132 also outputs the first frequency detection signal FD_u and the second frequency detection signal FD_n.

[0017] In this embodiment, the frequency detection and selection circuit 132 has an eleventh D-type flip-flop 132a, a first multiplexer 132b, a second multiplexer 132c, a third multiplexer 132d, and a fourth multiplexer 132e. The input terminal and clock terminal of the eleventh D-type flip-flop 132a respectively receive the in-phase clock signal clkI and the edge detection signal ED. The eleventh D-type flip-flop 132a is triggered by the positive edge of the edge detection signal ED to store the potential of the in-phase clock signal clkI, and the eleventh D-type flip-flop 132a outputs a flip-flop signal DF. The input terminal of the first multiplexer 132b is electrically connected to the eleventh type D flip-flop 132a and a ground terminal Gnd. The first multiplexer 132b receives the flip-flop signal DF, and the control terminal of the first multiplexer 132b receives the frequency rise / fall control signal UP / DN. Under the control of the frequency rise / fall control signal UP / DN, the first multiplexer 132b determines whether to output the flip-flop signal DF or the low potential of the ground terminal Gnd as a second rise signal up2. The input terminal of the second multiplexer 132c is electrically connected to the output terminal of the first multiplexer 132b and the gate logic unit 131g. The second multiplexer 132c receives the first rising signal up1 and the second rising signal up2, and the control terminal of the second multiplexer 132c receives the lock signal L. The second multiplexer 132c outputs the first frequency detection signal FD_u. The second multiplexer 132c is controlled by the lock signal L to determine whether to output the first rising signal up1 or the second rising signal up2 as the first frequency detection signal FD_u.

[0018] The input terminal of the third multiplexer 132d is electrically connected to the eleventh type D flip-flop 132a and the ground terminal. The third multiplexer 132d receives the flip-flop signal DF, and the control terminal of the third multiplexer 132d receives the frequency rise / fall control signal UP / DN. The third multiplexer 132d is controlled by the frequency rise / fall control signal UP / DN to determine whether to output the flip-flop signal DF or the low potential of the ground terminal Gnd as a second falling signal dn2. The input terminal of the fourth multiplexer 132e is electrically connected to the output terminal of the third multiplexer 132d and the gate logic unit 131g. The fourth multiplexer 132e receives the first falling signal dn1 and the second falling signal dn2, and the control terminal of the fourth multiplexer 132e receives the lock signal L. The fourth multiplexer 132e outputs the second frequency detection signal FD_n. The fourth multiplexer 132e is controlled by the lock signal L to determine whether to output the first falling signal dn1 or the second falling signal dn2 as the second frequency detection signal FD_n.

[0019] Because the digital correction frequency detector 131 is prone to data loss when the frequency difference between the clock signal and the edge detection signal ED is too large, when the lock signal L is low, indicating that the frequency difference is too large, the first frequency rise detection signal FD_u output by the frequency detection selection circuit 132 becomes the second rise signal up2, and the second frequency detection signal FD_n output by the frequency detection selection circuit 132 becomes the second fall signal dn2. When the lock signal L is high, indicating that the frequency difference is small, the frequency rise detection signal FD_UP output by the frequency detection selection circuit 132 becomes the first rise signal up1, and the frequency fall detection signal FD_DN output by the frequency detection selection circuit 132 becomes the first fall signal dn1.

[0020] Referring to Figure 1, the second charge pump 160 is electrically connected to the frequency detector 130 to receive the first frequency detection signal FD_u and the second frequency detection signal FD_n. The second charge pump 160 charges or discharges a capacitor C according to the first frequency detection signal FD_u and the second frequency detection signal FD_n, and outputs a coarse adjustment voltage Vc. In this embodiment, the circuit structure of the second charge pump 160 is the same as that of the first charge pump 150. The charging path and the discharging path are controlled by the first frequency detection signal FD_u and the second frequency detection signal FD_n to charge or discharge the capacitor C, thereby changing the magnitude of the coarse adjustment voltage Vc. Therefore, the circuit of the second charge pump 160 will not be described in detail.

[0021] Please refer to Figures 1 and 7. The hysteresis lock detector 140 is electrically connected to the edge detector 110 to receive the edge detection signal ED. The hysteresis lock detector 140 also receives the in-phase clock signal clkI. The hysteresis lock detector 140 is used to determine the frequency difference between the in-phase clock signal clkI and the edge detection signal ED and output the lock signal L to the phase detector 120 and the frequency detector 130.

[0022] Referring to Figure 7, in this embodiment, the hysteresis-locked detector 140 has a first counter 141, a second counter 142, a reset logic operation unit 143, an inverting logic unit 144, and a locking logic unit 145. The first counter 141 is electrically connected to the edge detector 110 to receive the edge detection signal ED and count to output a first counting signal A0-AN-1. The second counter 142 receives the in-phase clock signal clkI and counts to output a second counting signal B0-BN-1. The reset logic operation unit 143 is electrically connected to the first counter 141 and the second counter 142 to receive the highest bit AN-1 and the second bit A1 of the first counting signal and the highest bit BN-1 and the second bit B1 of the second counting signal, and the reset logic operation unit 143 outputs a logic reset signal R. The inverting logic unit 144 is electrically connected to the first counter 141, the second counter 142, and the reset logic operation unit 143 to receive the most significant bit AN-1 of the first counting signal, the most significant bit BN-1 of the second counting signal, and the logic reset signal R. The inverting logic unit 144 outputs a first inverted counting signal AbN-1, a second inverted counting signal BbN-1, and a first inverted logic reset signal Rb1. The locking logic unit 145 is electrically connected to the inverting logic unit 144 to receive the first inverted counting signal AbN-1, the second inverted counting signal BbN-1, and the first inverted logic reset signal Rb1. The locking logic unit 145 outputs the locking signal L and a second inverted logic reset signal Rb2, which is transmitted to the reset terminal of one of the first counter 141 and the second counter 142.

[0023] The hysteresis lock detector 140 is mainly used to switch the frequency detector 130. The first counter 141 and the second counter 142 count the in-phase clock signal clkI and the edge detection signal ED respectively. If the highest bit of one of the counting signals rises to a high level while the highest bit of the other counting signal is still at a low level, it indicates that the frequency difference between the in-phase clock signal clkI and the edge detection signal ED is still too large. At this time, the lock signal L is at a low level, so that the frequency rise detection signal FD_UP output by the frequency detection selection circuit 132 becomes the second rise signal up2, and the frequency fall detection signal FD_DN output becomes the second fall signal dn2. The phase lock is performed based on the frequency difference between the in-phase clock signal clkI and the edge detection signal ED to shorten the lock time. When the frequencies are close, the locking signal L rises to a high potential, switching to the frequency detection selection circuit 132 and the phase detector 120 to perform phase locking, thereby achieving the effect of wide locking.

[0024] Referring to Figure 7, in this embodiment, the reset logic operation unit 143 has a first inverting gate 143a, a second inverting gate 143b, a third inverting gate 143c, and a fourth inverting gate 143d. The first inverting gate 143a is electrically connected to the first counter 141 and the second counter 142 to receive the highest bit AN-1 of the first counting signal and the highest bit NB-1 of the second counting signal, and the first inverting gate 143a outputs a first inverting gate signal. The second inverting gate 143b is electrically connected to the second counter 142 to receive the highest bit NB-1 and the second bit NB-1 of the second counting signal, and the second inverting gate 143b outputs a second inverting gate signal. The third reverse gate 143c is electrically connected to the first counter 141 to receive the most significant bit AN-1 and the second bit A1 of the first counting signal, and the third reverse gate 143c outputs a third reverse gate signal. The fourth reverse gate 143d is electrically connected to the first, second, and third reverse gates 143a, 143b, and 143c to receive the first, second, and third reverse gate signals, and the fourth reverse gate 143d outputs the logic reset signal R.

[0025] The inverting logic unit 144 includes a first inverter 144a, a second inverter 144b, and a third inverter 144c. The first inverter 144a is electrically connected to the fourth inverter 143d to receive the logic reset signal R, and the first inverter 144a outputs the first inverted logic reset signal Rb1. The second inverter 144b is electrically connected to the first counter 141 to receive the most significant bit A N-1 of the first counting signal, and the second inverter 144b outputs the first inverted counting signal Ab N-1. The third inverter 144c is electrically connected to the second counter 142 to receive the most significant bit B N-1 of the second counting signal, and the third inverter 144c outputs the second inverted counting signal Bb N-1.

[0026] The locking logic unit 145 includes an inverse OR gate 145a, a third delay unit 145b, a third D-type flip-flop 145c, and a third AND gate 145d. The inverse OR gate 145a is electrically connected to the inverting logic unit 144 to receive the first inverting count signal Ab N-1 and the second inverting count signal Bb N-1, and the inverse OR gate 145a outputs an inverse OR gate signal orb. The third delay unit 145b is electrically connected to the inverse OR gate 145a to receive the inverse OR gate signal orb, and the third delay unit 145b outputs a delayed inverse OR gate signal orbd. The third D-type flip-flop 145c is electrically connected to the inverse OR gate 145a and the third delay unit 145b to receive the inverse OR gate signal orb and the delayed inverse OR gate signal orbd. Furthermore, the third D-type flip-flop 145c outputs the locking signal L and an inverting locking signal Lb. The third gate 145d is electrically connected to the third D-type flip-flop 145c and the inverting logic unit 144 to receive the inverting locking signal Lb and the first inverting logic reset signal Rb1. The third gate 145d outputs the second inverting logic reset signal Rb2 to the reset terminal of the first counter 141 and the second counter 142.

[0027] Referring to Figure 1, the voltage-controlled oscillator 170 is electrically connected to the first charge pump 150 and the second charge pump 160 to receive the coarse adjustment voltage Vc and the fine adjustment voltage Vf, and the voltage-controlled oscillator 170 outputs the in-phase clock signal clkI and the quadrature clock signal clkQ. In this embodiment, the voltage-controlled oscillator 170 is a dual-input dual-output ring oscillator. The frequency of the output oscillation signal of the voltage-controlled oscillator 170 is simultaneously controlled by the coarse adjustment voltage Vc and the fine adjustment voltage Vf, and can be frequency-locked using the coarse adjustment voltage Vc and the fine adjustment voltage Vf. The voltage-controlled oscillator 170 also converts the dual-ended output oscillation signal into the in-phase clock signal clkI and the quadrature clock signal clkQ respectively through two dual-to-single-ended circuits.

[0028] Referring to Figure 1, the frequency up / down control circuit 180 receives the in-phase clock signal clkI and the edge detection signal ED, and the frequency up / down control circuit 180 outputs the frequency up / down control signal UP / DN to the frequency detector 130. Referring to Figure 8, the frequency up / down control circuit 180 has a dynamic comparator 181, a surge cancellation circuit 182 and a fourth D-type flip-flop 183. The dynamic comparator 181 is electrically connected to the edge detector 110 and the voltage controlled oscillator 170 to receive the edge detection signal ED and the in-phase clock signal clkI. The dynamic comparator 181 is used to compare the frequencies of the edge detection signal ED and the in-phase clock signal clkI, and the dynamic comparator 181 outputs a dynamic comparison signal DC. The surge cancellation circuit 182 is electrically connected to the dynamic comparator 181 to receive the dynamic comparison signal DC to cancel surges, and the surge cancellation circuit 182 outputs a leading signal ld. The fourth D-type flip-flop 183 is electrically connected to the surge cancellation circuit 182 and the voltage-controlled oscillator 170 to receive the leading signal ld and the in-phase clock signal clkI, and the fourth D-type flip-flop 183 outputs the frequency rise / fall control signal UP / DN.

[0029] Please refer to Figures 9a and 9b, which are timing diagrams of the in-phase clock signal clkI, the edge detection signal ED, the lead signal ld, and the frequency rise / fall control signal UP / DN of the frequency rise / fall control circuit 180. In Figure 9a, when the frequency of the edge detection signal ED is higher than that of the in-phase clock signal clkI, the lead signal ld will rise to a high level, causing the frequency rise / fall control signal UP / DN to rise to a high level. Conversely, please refer to Figure 9b, when the frequency of the edge detection signal ED is lower than that of the in-phase clock signal clkI, the lead signal ld will remain at a low level, causing the frequency rise / fall control signal UP / DN to remain at a low level. Please refer to Figures 1 and 5. By controlling the first multiplexer 132b and the third multiplexer 132d using the frequency rise / fall control signal UP / DN of the frequency up / down control circuit 180, when the frequency of the edge detection signal ED is higher than the in-phase clock signal clkI, the first multiplexer 132b is controlled to output the flip-flop signal DF as the second rising signal up2, and the third multiplexer 132d is controlled to output the flip-flop signal DF as the second falling signal dn2, thereby quickly adjusting the frequency of the in-phase clock signal clkI. Conversely, when the frequency of the edge detection signal ED is lower than the in-phase clock signal clkI, the first multiplexer 132b is controlled to output a low potential as the second rising signal up2, and the third multiplexer 132d is controlled to output a low potential as the second falling signal dn2, thereby slowly adjusting the frequency of the in-phase clock signal clkI.

[0030] Referring to Figure 1, the decision circuit 190 is electrically connected to the voltage-controlled oscillator 170 to receive the in-phase clock signal clkI. The decision circuit 190 also receives the input data Di, and the decision circuit 190 recovers the input data Di into an output data Do using the in-phase clock signal clkI. In this embodiment, the decision circuit 190 is a D-type flip-flop. The decision circuit 190 samples the input data Di using the in-phase clock signal clkI as a trigger signal and outputs the output data Do, thereby synchronizing the output data Do with the in-phase clock signal clkI and eliminating noise in the input data Di.

[0031] The present invention uses the edge detector 110 to detect the positive and negative edges of the input data Di so that the correct sampling frequency can be obtained in subsequent processing. The phase detector 120 and the frequency detector 130 adjust the frequency of the in-phase clock signal clkI with fine adjustment mechanism and coarse adjustment mechanism respectively, so that it can have the effects of wide frequency modulation range and precise frequency locking at the same time.

[0032] The scope of protection of this invention shall be determined by the appended claims. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of this invention shall fall within the scope of protection of this invention. [Simplified Explanation of the Diagram]

[0033] Figure 1: Functional block diagram of a clock data recovery circuit according to an embodiment of the present invention. Figure 2: Circuit diagram of an edge detector according to an embodiment of the present invention. Figure 3: Circuit diagram of a phase detector and a first charge pump according to an embodiment of the present invention. Figures 4a and 4b: Timing diagrams of the phase detector and the first charge pump according to an embodiment of the present invention. Figure 5: Circuit diagram of a frequency detector according to an embodiment of the present invention. Figures 6a and 6b: Timing diagrams of the frequency detector according to an embodiment of the present invention. Figure 7: Circuit diagram of a hysteresis-locked detector according to an embodiment of the present invention. Figure 8: Circuit diagram of a frequency up / down control circuit according to an embodiment of the present invention. Figures 9a and 9b: Timing diagrams of the frequency up / down control circuit according to an embodiment of the present invention.

Claims

1. A clock data recovery circuit, comprising: an edge detector receiving input data to detect the positive and negative edges of the input data, and the edge detector outputting an edge detection signal; a phase detector receiving the input data and a co-phase clock signal, the phase detector detecting the phase relationship between the co-phase clock signal and the input data and outputting a phase detection signal; and a frequency detector electrically connected to the edge detector to receive the edge detection signal, the frequency detector receiving the co-phase clock signal and a quadrature clock signal, the frequency detector detecting the frequency relationship between the co-phase clock signal and the edge detection signal and outputting a frequency detection signal. A hysteresis-locked detector, electrically connected to the edge detector to receive the edge detection signal, and the hysteresis-locked detector also receives the in-phase clock signal. The hysteresis-locked detector is used to determine the frequency difference between the in-phase clock signal and the edge detection signal and outputs a locking signal to the phase detector and the frequency detector; a first charge pump, electrically connected to the phase detector to receive the phase detection signal, and the first charge pump outputs a fine-tuning voltage through a loop filter; a second charge pump, electrically connected to the frequency detector to receive the frequency detection signal, and the second charge pump charges or discharges a capacitor according to the frequency detection signal and outputs a coarse-tuning voltage; a voltage-controlled oscillator, electrically connected to the first charge pump and the second charge pump to receive the coarse-tuning voltage and the fine-tuning voltage, and the voltage-controlled oscillator outputs the in-phase clock signal and the quadrature clock signal; A frequency up / down control circuit receives the in-phase clock signal and the edge detection signal, and outputs a frequency up / down control signal to the frequency detector; and a decision circuit electrically connected to the voltage-controlled oscillator to receive the in-phase clock signal, the decision circuit also receives the input data, and the decision circuit recovers the input data into output data using the in-phase clock signal, wherein the phase detector has a first D-type flip-flop, a second D-type flip-flop, a second XOR gate and a third XOR gate, the first D-type flip-flop receives the input data and the in-phase clock signal, and the first D-type flip-flop... A first D-type flip-flop outputs a first output signal. A second D-type flip-flop is electrically connected to the first D-type flip-flop to receive the first output signal, and the second D-type flip-flop also receives the in-phase clock signal and outputs the second output signal. A second XOR gate is electrically connected to the first D-type flip-flop to receive the first output signal, and the second XOR gate also receives the input data and outputs an error pulse. A third XOR gate is electrically connected to the first D-type flip-flop and the second D-type flip-flop to receive the first output signal and the second output signal, and the third XOR gate outputs a reference pulse.

2. The clock data recovery circuit as described in claim 1, wherein the edge detector has a first delay unit and a first XOR gate, the first delay unit receiving the input data and outputting delayed data, the first XOR gate being electrically connected to the first delay unit to receive the delayed data, the first XOR gate receiving the input data, and the first XOR gate outputting the edge detection signal.

3. The clock data recovery circuit as described in claim 2, wherein the phase detector has a second delay, a first XOR gate and a second XOR gate, the second XOR gate receiving the input data via the second delay, the first XOR gate being electrically connected to the second XOR gate to receive the error pulse, the first XOR gate receiving an inverted reset signal, the first XOR gate outputting a first phase detection signal, the second XOR gate being electrically connected to the third XOR gate to receive the reference pulse, the second XOR gate receiving the inverted reset signal, and the second XOR gate outputting a second phase detection signal.

4. As in claim 3, the clock data recovery circuit, wherein the first charge pump has a first current source, a first switch, a second switch, a second current source, and a first charging capacitor; the two ends of the first switch are electrically connected to the first current source and a charging node, respectively; the first switch is also electrically connected to a first gate to receive and be controlled by the first phase detection signal; the two ends of the second switch are electrically connected to the charging node and the second current source, respectively; the second switch is also electrically connected to a second gate to receive and be controlled by the second phase detection signal; the first charging capacitor is electrically connected to the charging node and generates a charging voltage at the charging node; the charging voltage is output as the fine-tuning voltage via the loop filter.

5. The clock data recovery circuit as described in claim 1, wherein the hysteresis-locked detector has a first counter, a second counter, a reset logic unit, an inverting logic unit, and a locking logic unit. The first counter is electrically connected to the edge detector to receive the edge detection signal and output a first counting signal. The second counter receives the in-phase clock signal and outputs a second counting signal. The reset logic unit is electrically connected to the first counter and the second counter to receive the first counting signal and the second counting signal, and the reset logic unit outputs a logic reset signal. The inverting logic unit is electrically connected to... The first counter, the second counter, and the reset logic unit are connected to receive the first counting signal, the second counting signal, and the logic reset signal. The inverting logic unit outputs a first inverted counting signal, a second inverted counting signal, and a first inverted logic reset signal. The locking logic unit is electrically connected to the inverting logic unit to receive the first inverted counting signal, the second inverted counting signal, and the first inverted logic reset signal. The locking logic unit outputs the locking signal and a second inverted logic reset signal. The second inverted logic reset signal is transmitted to the reset terminal of one of the first counter and the second counter.

6. The clock data recovery circuit as described in claim 5, wherein the reset logic unit has a first inverse gate, a second inverse gate, a third inverse gate, and a fourth inverse gate; the lock logic unit has an inverse OR gate, a third delay unit, a third D-type flip-flop, and a third inverse gate; the first inverse gate is electrically connected to the first counter and the second counter to receive the first counting signal and the second counting signal, and the first inverse gate outputs a first inverse gate signal; the second inverse gate is electrically connected to the second counter to receive the second counting signal, and the second inverse gate outputs a second inverse gate signal; the third inverse gate is electrically connected to the first counter to receive the first counting signal, and the third inverse gate outputs a third inverse gate signal; the fourth inverse gate is electrically connected to the first, second, and third inverse gates to receive the first, second, and third inverse gates. The third inverter is electrically connected to the inverting logic unit to receive the first inverting count signal and the second inverting count signal, and the third delay is electrically connected to the inverting inverter to receive the inverting count signal, and the third delay outputs a delayed inverting count signal. The third D-type flip-flop is electrically connected to the inverting inverter and the third delay to receive the inverting count signal and the delayed inverting count signal, and the third D-type flip-flop outputs the locking signal and an inverting locking signal. The third inverter is electrically connected to the third D-type flip-flop and the inverting logic unit to receive the inverting locking signal and the first inverting logic reset signal, and the third inverter outputs the second inverting logic reset signal to the reset terminals of the first counter and the second counter.

7. The clock data recovery circuit as claimed in claim 1, wherein the frequency up / down control circuit has a dynamic comparator, a surge cancellation circuit, and a fourth D-type flip-flop; the dynamic comparator is electrically connected to the edge detector and the voltage-controlled oscillator to receive the edge detection signal and the in-phase clock signal; the dynamic comparator is used to compare the edge detection signal and the in-phase clock signal; and the dynamic comparator outputs a dynamic comparison signal; the surge cancellation circuit is electrically connected to the dynamic comparator to receive the dynamic comparison signal; and the surge cancellation circuit outputs a leading signal; the fourth D-type flip-flop is electrically connected to the surge cancellation circuit and the voltage-controlled oscillator to receive the leading signal and the in-phase clock signal; and the fourth D-type flip-flop outputs the frequency up / down control signal.

8. A clock data recovery circuit as claimed in claim 1, wherein the frequency detector has a digitally calibrated frequency detector and a frequency detection selection circuit, the digitally calibrated frequency detector being electrically connected to the edge detector and the voltage-controlled oscillator to receive the edge detection signal, the in-phase clock signal and the quadrature clock signal, and the digitally calibrated frequency detector outputting a first rising signal and a first falling signal, the frequency detection selection circuit being electrically connected to the edge detector, the voltage-controlled oscillator, the digitally calibrated frequency detector, the hysteresis-locked detector and the frequency up / down control circuit, the frequency detection selection circuit receiving the edge detection signal, the in-phase clock signal, the lock signal and the frequency up / down control signal, and the frequency detection selection circuit outputting the frequency detection signal.

9. The clock data recovery circuit as described in claim 8, wherein the digital correction frequency detector has a fifth D-type flip-flop, a sixth D-type flip-flop, a seventh D-type flip-flop, an eighth D-type flip-flop, a ninth D-type flip-flop, a tenth D-type flip-flop, and a gate logic unit; the frequency detection selection circuit has an eleventh D-type flip-flop, a first multiplexer, a second multiplexer, a third multiplexer, and a fourth multiplexer; the input and clock terminals of the fifth D-type flip-flop receive the in-phase clock signal and the edge detection signal, respectively; and the input of the sixth D-type flip-flop... The input and clock terminals of the seventh D-type flip-flop are respectively connected to the output of the fifth D-type flip-flop and receive the in-phase clock signal. The input and clock terminals of the eighth D-type flip-flop are respectively connected to the output of the sixth D-type flip-flop and receive the in-phase clock signal. The input and clock terminals of the ninth D-type flip-flop are respectively connected to the output of the seventh D-type flip-flop and receive the in-phase clock signal. The input and clock terminals of the tenth D-type flip-flop are respectively connected to the output of the eighth D-type flip-flop. The output terminal of the inverter receives the in-phase clock signal. The gate logic unit is electrically connected to the seventh D-type flip-flop, the eighth D-type flip-flop, the ninth D-type flip-flop, and the tenth D-type flip-flop. The gate logic unit outputs the first rising signal and the first falling signal. The input terminal and clock terminal of the eleventh D-type flip-flop receive the in-phase clock signal and the edge detection signal, respectively. The input terminal of the first multiplexer is electrically connected to the eleventh D-type flip-flop and a ground terminal. The control terminal of the first multiplexer receives the frequency rise / fall control signal. The second multiplexer... The input terminal of the first multiplexer is electrically connected to the output terminal of the first multiplexer and the gate logic unit, and the control terminal of the second multiplexer receives the lock signal. The second multiplexer outputs a first frequency detection signal. The input terminal of the third multiplexer is electrically connected to the eleventh type D flip-flop and the ground terminal, and the control terminal of the third multiplexer receives the frequency rise / fall control signal. The input terminal of the fourth multiplexer is electrically connected to the output terminal of the third multiplexer and the gate logic unit, and the control terminal of the fourth multiplexer receives the lock signal. The fourth multiplexer outputs a second frequency detection signal.

Images