Memory system and decoding circuit

Abstract

This invention provides a memory system and decoding circuit capable of appropriately correcting periodic errors. The memory controller performs a first conversion operation on each of a plurality of first segments, each divided by a first length. This first conversion operation converts the order of symbols within a first segment using a conversion mode corresponding to the position of a first segment in the first symbol row. The memory controller then performs a second conversion operation on each of the plurality of first segments following the first conversion operation. This second conversion operation converts the order of symbols within a first segment using a common conversion mode across the plurality of first segments. Finally, the memory controller performs decoding using the same bit position on the plurality of first segments following the second conversion operation.

Description

Technical Field

[0001] This embodiment relates to a memory system and a decoding circuit. Prior Technology

[0002] In memory systems, to protect data stored in non-volatile memory such as NAND (Non-AND) flash memory, error correction codes are applied to the data written to the non-volatile memory. Therefore, when reading data stored in non-volatile memory, the decoding circuit decodes the error-corrected data (also known as the received language) read from the non-volatile memory to correct any errors contained in the received language.

[0003] In memory systems, in addition to random or sudden errors, periodic errors (hereinafter referred to as periodic errors) may also occur due to periodic electrical noise. Summary of the Invention

[0004] One embodiment aims to provide a memory system and decoding circuit that can appropriately correct cycle errors.

[0005] According to one embodiment, the memory system includes a non-volatile first memory, a volatile second memory, and a memory controller. The memory controller reads a first symbol line from the first memory. The memory controller performs a first conversion operation on each of the plurality of first segments divided into segments of a first length, wherein the first conversion operation converts the order of symbols within a first segment using a conversion mode corresponding to the position of a first segment in the first symbol line. The memory controller performs a second conversion operation on each of the plurality of first segments following the first conversion operation, wherein the second conversion operation converts the order of symbols within a first segment using a common conversion mode across the plurality of first segments. The memory controller performs decoding using the same bit on the plurality of first segments following the second conversion operation. The memory controller performs a third conversion operation, the inverse of the second conversion operation, on each of the plurality of first segments after decoding. The memory controller performs the inverse transition of the transition of the first transition, i.e., the fourth transition, on each of the plurality of first segments following the third transition. The memory controller then stores the second symbol line, which is formed by combining the plurality of first segments following the fourth transition, in the second memory. Simple Explanation of the Diagram

[0006] Figure 1 is a block diagram showing a schematic configuration example of a memory system in an implementation form. Figure 2 is a diagram showing the data flow during the write operation in the implementation mode. Figure 3 is a diagram showing the data flow during the read operation in the implementation mode. Figure 4 is a diagram illustrating one example of an encoding method for an implemented encoding circuit. Figure 5 is a block diagram showing an example of the configuration of the decoding circuit in the implementation. Figure 6 is a block diagram showing an example of the configuration of the encoding circuit in the implementation. Figure 7 is a diagram showing an example of data rotation and interweaving in the implementation mode. Figure 8 is an example of a method for calculating the number of rotations in an implementation configuration. Figure 9 is an example of the matrix structure formed after data rotation and interweaving in the implemented form. Figure 10 is a diagram illustrating a detailed configuration example of the rotary circuit, the reverse rotary circuit, and their peripheral circuits in the implementation configuration. Figure 11 is a diagram showing an example of the waveforms of various signals in the decoding circuit of an embodiment. Implementation

[0007] The memory system and decoding circuit of the embodiment are described in detail below with reference to the accompanying drawings. However, this invention is not limited to this embodiment.

[0008] (Implementation Mode) Figure 1 is a block diagram showing a schematic configuration example of a memory system in an embodiment. As shown in Figure 1, the memory system 1 includes a memory controller 10 and non-volatile memory 20. The memory system 1 can be connected to a host 30, and Figure 1 shows the connection state with the host 30. The host 30 can be, for example, a personal computer, a mobile terminal, or other electronic device.

[0009] Non-volatile memory 20 refers to non-volatile memory that stores data non-volatilely, such as NAND memory. In the following description, although NAND memory is used as an example of non-volatile memory 20, other memory devices besides NAND memory, such as 3D flash memory, ReRAM (Resistance Random Access Memory), and FeRAM (Ferroelectric Random Access Memory), can also be used as non-volatile memory 20. Furthermore, non-volatile memory 20 is not necessarily a semiconductor memory; this embodiment can be applied to various memory media other than semiconductor memory. Additionally, non-volatile memory 20 is an example of a first memory.

[0010] The memory system 1 may be a memory card that integrates the memory controller 10 and the non-volatile memory 20 into a single package, or it may be an SSD (Solid State Drive).

[0011] The memory controller 10 controls write operations to the non-volatile memory 20 according to write requests from the host 30. Similarly, the memory controller 10 controls read operations from the non-volatile memory 20 according to read requests from the host 30. The memory controller 10 includes a host I / F (Interface) 15, a memory I / F 13, a control unit 11, an encoding / decoding unit 14, and a data buffer 12. The host I / F 15, memory I / F 13, control unit 11, encoding / decoding unit 14, and data buffer 12 are interconnected via an internal bus 16. Part or all of the operation of each component of the memory controller 10 can be implemented by the CPU (Central Processing Unit) executing firmware, or by hardware.

[0012] The host I / F15 performs processing according to the interface specifications between itself and the host 30, and outputs commands received from the host 30, user data of the write target, etc., to the circuit of the internal bus 16. In addition, the host I / F15 sends user data read and restored from the non-volatile memory 20, responses from the control unit 11, etc., to the host 30.

[0013] The memory I / F13 is a circuit that performs write or read operations on the non-volatile memory 20 based on the instructions of the control unit 11.

[0014] The control unit 11 is a processor that comprehensively controls all components of the memory system 1. The control unit 11 is, for example, a CPU (Central Processing Unit). When the control unit 11 receives a request from the host 30 via the host I / F 15, it performs control corresponding to that request. For example, according to a request from the host 30, the control unit 11 instructs the memory I / F 13 to write user data and corresponding bits to the non-volatile memory 20. Also, according to a request from the host 30, the control unit 11 instructs the memory I / F 13 to read user data and corresponding bits from the non-volatile memory 20.

[0015] Furthermore, when the control unit 11 receives a write request for user data from the host 30, it stores the user data in the data buffer 12 and determines the memory region (memory area) in the non-volatile memory 20 containing the user data. That is, the control unit 11 manages the write destination of the user data. An address translation table is created that maps the logical address of the user data received from the host 30 to the physical address of the memory region in the non-volatile memory 20 containing the user data.

[0016] Furthermore, when the control unit 11 receives a read request from the host 30, it uses the aforementioned address translation table to convert the logical address specified by the read request into a physical address, and instructs the memory I / F13 to read from that physical address.

[0017] Data buffer 12 is composed of volatile memory. Data buffer 12 temporarily stores user data received from host 30 by memory controller 10 until it is stored in non-volatile memory 20. Furthermore, data buffer 12 temporarily stores user data read from non-volatile memory 20 until it is sent to host 30. Data buffer 12 can be, for example, general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory). Additionally, data buffer 12 is an example of a second type of memory.

[0018] User data sent from host 30 is transmitted to internal bus 16 and temporarily stored in data buffer 12. Encoding / decoding unit 14 encodes the user data to generate codewords. Furthermore, encoding / decoding unit 14 decodes data read from non-volatile memory 20, i.e., received language, to restore the user data. Therefore, encoding / decoding unit 14 includes encoding circuit 17 and decoding circuit 18. In addition to user data, the data encoded by encoding / decoding unit 14 may also include control data used within memory controller 10.

[0019] Figure 2 is a diagram showing the data flow during the write operation in the implementation mode.

[0020] Based on the write request from the host 30, the control unit 11 instructs the host I / F 15 to receive user data. The host I / F 15 receives the user data from the host 30 and stores the received user data in the data buffer 12.

[0021] The control unit 11 instructs the encoding circuit 17 to encode user data. At this time, the control unit 11 determines the memory location (memory address) of the codeword in the non-volatile memory 20 and instructs the determined memory location to the memory I / F 13.

[0022] The encoding circuit 17, based on instructions from the control unit 11, encodes the user data in the data buffer 12 to generate corresponding bits. As an encoding method, for example, it can employ algebraic codes such as BCH (Bose-Chaudhuri-Hocquenghem) and RS (Reed-Solomon) codes, or use such codes as component codes for column and row directions (product codes, etc.). The memory I / F 13 controls the writing of the user data stored in the data buffer 12 and the corresponding bits generated by the encoding circuit 17 to the memory location on the non-volatile memory 20 as instructed by the control unit 11.

[0023] Figure 3 is a diagram showing the data flow during the read operation in the implementation mode.

[0024] Based on the read request from the host 30, the control unit 11 specifies the address on the non-volatile memory 20 and instructs the memory I / F 13 to read the data. Furthermore, the control unit 11 instructs the decoding circuit 18 to begin decoding. Following the instructions of the control unit 11, the memory I / F 13 reads data and corresponding bits from the specified address of the non-volatile memory 20, and inputs the received language containing the read data and corresponding bits to the decoding circuit 18. The decoding circuit 18 decodes the received language read from the non-volatile memory 20. The data, after error correction by the decoding circuit 18, is stored in the data buffer 12.

[0025] The host 30 instructs the host I / F 15 to output user data at a specified time. The host I / F 15, in accordance with the instructions of the control unit 11, outputs the error-corrected data in the data buffer 12 to the host 30.

[0026] Next, the error correction code used in this embodiment will be explained. In this embodiment, as an example, the encoding circuit 17 generates a product code. The product code has the following structure: the constituent units of user data, i.e., each information symbol, are protected in both the column and row directions by a Hamming code containing a symbol of the same bit length with a predetermined same bit length. That is, in the product code, all symbols are doubly protected by component codes in both the column and row directions. A symbol is composed, for example, of a single bit (a binary field element) or a letter element other than a binary field. Furthermore, for ease of explanation, the following explanation uses an error correction code of a binary field consisting of a single bit as an example.

[0027] Figure 4 is an example of the encoding method of the encoding circuit 17 in the embodiment.

[0028] As shown in Figure 4, a matrix MX is formed by arranging 16 segments SC in both column and row directions. Each segment SC is generated by dividing the symbol rows that constitute the user data into segments of a specified length (16 symbols in this case). The 16 symbols constituting each segment SC are arranged as a submatrix of 4 symbols × 4 symbols. Each segment SC is assigned a segment number corresponding to its position in the symbol row. For example, a segment SC consisting of 16 symbols from the beginning of the symbol row to the 16th symbol is assigned segment number 0. A segment SC consisting of 16 symbols from the 17th symbol from the beginning of the symbol row to the 32nd symbol is assigned segment number 1. Hereinafter, the segment SC with segment number X is sometimes referred to as segment SC#X.

[0029] The 16 segments SC are arranged in positions corresponding to their respective segment numbers, thereby forming a matrix MX of 4 segments SC × 4 segments SC. Since each segment SC is composed of a submatrix of 4 symbols × 4 symbols, the matrix MX is a matrix of 16 symbols × 16 symbols.

[0030] For the matrix MX, correction blocks are constructed for each column and each row. For example, regarding the row direction, correction blocks C are constructed for each of the 16 rows. Regarding the column direction, correction blocks R are constructed for each of the 16 columns.

[0031] To disperse errors, each segment SC is interleaved within the submatrix that constitutes segment SC. Interleaving is the action of changing the order of symbols in a way that separates adjacent symbols from each other.

[0032] The interleaving conversion pattern is common across all segments SC. Therefore, when an error occurs in a specific period, it can be difficult to correct because the error tends to concentrate in a specific column or row of matrix MX. For example, when an error occurs in a period based on the number of symbols constituting segment SC (16 symbols in the example shown in Figure 4), the error in each segment SC is located in a common position across multiple segments SC. Therefore, in matrix MX, the error is concentrated in a specific correction block C or a specific correction block R.

[0033] In interleaving, if the switching mode varies for each segment SC, the tolerance to the aforementioned cycle errors can be improved. However, if interleaving is performed with a switching mode that varies for each segment SC, the size of the interleaving circuitry increases, and the cost of the memory system rises.

[0034] To minimize the circuit size of the decoding circuit 18 and improve its tolerance to periodic errors, in addition to interleaving, each segment SC in the decoding circuit 18 undergoes other conversion processes. Specifically, before interleaving, each segment SC undergoes a cyclic shift. The number of shifts in the cyclic shift varies depending on the segment number. This prevents errors from concentrating in a specific correction block C or a specific correction block R, even if a periodic error as described above occurs.

[0035] The process of cyclic shifting in a certain direction will be referred to as data rotation or simply rotation. The number of shifts will be denoted as the number of rotations.

[0036] Figure 5 is a block diagram showing an example of the configuration of the decoding circuit 18 in an embodiment.

[0037] The decoding circuit 18 includes an input terminal 101, a counter 102, a rotation circuit 103, an input buffer 104, an interleaving circuit 105, a decoder 106, a deinterleaving circuit 107, an output buffer 108, an inverse rotation circuit 109, a counter 110, and an output terminal 111.

[0038] Input user data read from non-volatile memory 20 to input terminal 101.

[0039] Counter 102 counts the number of symbols input from input terminal 101 in the symbol row constituting the user data input to input terminal 101. Furthermore, based on the count value, counter 102 calculates the number of segments SC input from input terminal 101 in the symbol row constituting the user data input to input terminal 101. The calculated number of segments SC is interpreted in the rotation circuit 103 as the segment number of the segment SC during data rotation processing.

[0040] Rotation circuit 103 is a circuit that performs data rotation. Rotation circuit 103 obtains the rotation number based on the segment number obtained by counter 102, and performs data rotation based on the obtained rotation number.

[0041] The input buffer 104 is configured to store a symbol row for one segment SC. The segment SC after data rotation is stored in the input buffer 104.

[0042] The interleaving circuit 105 performs interleaving on the segment SC stored in the input buffer 104.

[0043] Decoder 106 constructs a matrix MX using multiple interleaved segments SC, and performs bitwise decoding on matrix MX to correct errors contained in matrix MX.

[0044] The deinterleaving circuit 107 performs deinterleaving on each segment SC contained in the matrix MX after error correction by decoding. Deinterleaving is the inverse conversion of interleaving.

[0045] The output buffer 108 is configured to store a symbol row of one segment SC. The deinterleaved segment SC is stored in the output buffer 108.

[0046] Counter 110 counts the symbols output by the self-reverse rotation circuit 109. Furthermore, based on the count value, counter 110 calculates the number of segments SC output by the self-reverse rotation circuit 109. The calculated number of segments SC is interpreted in the reverse rotation circuit 109 as the segment number of the segment SC during the reverse data rotation processing.

[0047] The reverse rotation circuit 109 is a circuit that performs reverse data rotation. Reverse data rotation is the inverse conversion of data rotation conversion. The reverse rotation circuit 109 obtains the rotation number based on the segment number obtained by the counter 110, and performs reverse data rotation based on the obtained rotation number.

[0048] The multiple segments SC after reverse rotation are combined and output as a symbol line from output terminal 111. The symbol line output from output terminal 111 is stored in data buffer 12 as user data after error correction.

[0049] The data rotation operation performed by the rotation circuit 103 is an example of the first conversion operation. The rotation circuit 103 is an example of the first conversion circuit. The interleaving operation performed by the interleaving circuit 105 is an example of the second conversion operation. The interleaving circuit 105 is an example of the second conversion circuit. The deinterleaving operation performed by the deinterleaving circuit 107 is an example of the third conversion operation. The deinterleaving circuit 107 is an example of the third conversion circuit. The reverse rotation operation performed by the reverse rotation circuit 109 is an example of the fourth conversion operation. The reverse rotation circuit 109 is an example of the fourth conversion circuit.

[0050] Figure 6 is a block diagram showing an example of the configuration of the encoding circuit 17 in an implementation configuration.

[0051] The encoding circuit 17 includes an input terminal 201, a counter 202, a rotation circuit 203, an input buffer 204, an interleaving circuit 205, an encoder 206, and an output terminal 207.

[0052] Input terminal 201 receives user data read from data buffer 12.

[0053] Counter 202, rotation circuit 203, input buffer 204 and interleaving circuit 205 perform the same operations as counter 102, rotation circuit 103, input buffer 104 and interleaving circuit 105.

[0054] That is, counter 202 counts the number of symbols input from input terminal 201 in the symbol row of user data that constitutes input to input terminal 201. Furthermore, based on the count value, counter 202 calculates the number of segments SC input from input terminal 201 in the symbol row of user data that constitutes input to input terminal 201. The calculated number of segments SC is interpreted in the rotation circuit 203 as the segment number of the segment SC during data rotation processing.

[0055] Rotation circuit 203 is a circuit that performs data rotation. Rotation circuit 203 obtains the rotation number based on the segment number obtained by counter 202, and performs data rotation based on the obtained rotation number.

[0056] The input buffer 204 is configured to store a symbol row for one segment SC. The input buffer 204 stores the segment SC after data rotation.

[0057] The interleaving circuit 205 performs interleaving on the segment SC stored in the input buffer 204.

[0058] The encoder 206 constructs a matrix MX by interleaving multiple segments SC, and encodes the matrix MX into product code, thereby generating the corresponding bits of the product code.

[0059] Output terminal 207 outputs the same bit generated by encoder 206.

[0060] The data rotation operation performed by the rotation circuit 203 is an example of the fifth conversion operation. The interleaving operation performed by the interleaving circuit 205 is an example of the sixth conversion operation.

[0061] Figure 7 is a diagram showing an example of data rotation and interleaving in an implementation configuration. Here, for ease of understanding, symbol numbers indicating the input order are provided for each symbol of a segment of SC quantity. Furthermore, in this figure, the processing in the decoding circuit 18 is illustrated as an example, but the same processing is implemented in the encoding circuit 17.

[0062] First, the user data of one segment SC is divided into multiple characters. A character is a unit of length approximating the length of one segment SC. Also, a character is an example of a sub-segment.

[0063] In the examples shown in Figure 7 and thereafter, one character is composed of four symbols. The first to fourth symbols constitute character 0, the fifth to eighth symbols constitute character 1, the ninth to twelfth symbols constitute character 2, and the thirteenth to sixteenth symbols constitute character 3.

[0064] The rotation circuit 103 rotates each character. Specifically, the rotation circuit 103 performs a cyclic shift on the group consisting of the 1st to 4th symbols, the group consisting of the 5th to 8th symbols, the group consisting of the 9th to 12th symbols, and the group consisting of the 13th to 16th symbols. Furthermore, Figure 7 shows an example of data rotation when the data rotation direction is to the right and the rotation number is 1. That is, each character is cyclically shifted to the right by 1 symbol.

[0065] In the input buffer 104, by connecting the four characters after data rotation in the column direction, a submatrix of four symbols × four symbols, the same as that of a segment SC, is generated.

[0066] In the interleaving operation, a prescribed transformation is performed to separate adjacent symbols from each other. In the example shown in Figure 7, each row of the submatrix is ​​cyclically shifted downwards by the same number as the row numbers. This separates adjacent symbols in the column or row direction before the interleaving operation from each other after the interleaving operation. However, the examples of interleaving operations are not limited to those shown in Figure 7.

[0067] As mentioned above, the transition mode for interleaving actions is common across all SC segments. In contrast, the number of rotations in data rotation actions varies depending on the segment number.

[0068] Figure 8 is an example of a method for calculating the number of rotations in an implementation configuration. In this figure, 'sect' represents a segment number in binary notation.

[0069] In the example shown in Figure 8, the rotation number is obtained through a mutually exclusive logical sum calculation of section[1:0] and section[3:2]. Therefore, as shown in this figure, the rotation number varies depending on the section number within the range of 0 to 3. As a result, the conversion mode of data rotation actions varies for each section SC depending on the section number.

[0070] Figure 9 shows an example of the structure of matrix MX after data rotation and interleaving in the implemented form. The symbols in each segment SC represent the symbol numbers for displaying the input sequence.

[0071] As shown in Figure 9, the order of symbols within each segment SC varies depending on the segment SC (more precisely, on the number of rotations for each application). Therefore, even if a periodic error occurs in the period of a segment SC, the error will not be concentrated in a specific correction block C or a specific correction block R.

[0072] For example, the symbols with an input sequence of "1" in each segment SC are distributed across multiple correction blocks C and multiple correction blocks R. That is, the symbols with an input sequence of "1" in each segment SC will not be concentrated in any specific correction block C or any specific correction block R. Therefore, even if an error occurs with the first symbol in the input sequence of each segment SC, the error will not be concentrated in any specific correction block C or any specific correction block R. The same applies to symbols with an input sequence other than "1".

[0073] Figure 10 is a diagram illustrating a detailed configuration example of the rotary circuit 103, the reverse rotary circuit 109, and their peripheral circuits in the embodiment. In this figure, as an example, data is input to the input terminal 101 as a 4-bit wide signal.

[0074] As described above, counter 102 counts the number of symbols input from input terminal 101. Here, data is input as a 4-bit wide signal, with 4 bits constituting one character. Therefore, counter 102 counts the number of symbols input from input terminal 101 in units of characters. That is, counter 102 counts the number of characters input from input terminal 101.

[0075] Counter 102 calculates the segment number sect based on the count value word of the number of characters and the following formula (1). sect[3:0]=word[5:2]･･･(1)

[0076] Furthermore, counter 102 generates a start signal that is input to the E terminal of latch circuits 124a, 124b, 124c and 124d described later.

[0077] The rotation circuit 103 includes a latch circuit 121, a selector 122, and a rotation count calculation circuit 123.

[0078] The latch circuit 121 latches the data input from the input terminal 101. Furthermore, the data input to the input terminal 101 is a 4-bit wide signal. Therefore, the latch circuit 121 is configured to latch one word of data.

[0079] Selector 122 has four input terminals. One of the four input terminals of selector 122 is used to input data after rotating the data of one character latched in latch circuit 121 by a rotation number of "0" (i.e., the unrotated data). Another of the four input terminals of selector 122 is used to input data after rotating the data of one character latched in latch circuit 121 by a rotation number of "1". A third of the four input terminals of selector 122 is used to input data after rotating the data of one character latched in latch circuit 121 by a rotation number of "2". The remaining one of the four input terminals of selector 122 is used to input data after rotating the data of one character latched in latch circuit 121 by a rotation number of "3".

[0080] The rotation count calculation circuit 123 calculates the rotation count using the segment number obtained from the counter 102. For example, according to the example shown in Figure 8, the rotation count calculation circuit 123 obtains the rotation count by calculating the mutual exclusion logic sum of segments[1:0] and segments[3:2]. The rotation count obtained by the rotation count calculation circuit 123 is input as a selection signal to the selector 122. The selector 122 outputs the data of the 1-character that has been rotated (or has not been rotated) selected by the selection signal.

[0081] Therefore, when the data of the four characters constituting a certain segment SC is sequentially input into the rotation circuit 103, the rotation circuit 103 can perform data rotation corresponding to the segment number sect on each of the four characters.

[0082] The input buffer 104 includes latch circuits 124a, 124b, 124c, and 124d. Each latch circuit 124 has a D terminal and an E terminal. The D terminal of each latch circuit 124 is connected to the output terminal of the selector 122 of the rotary circuit 103. A start signal generated by the counter 102 is input to the E terminal of each latch circuit 124.

[0083] Counter 102 generates start signals for each latch circuit 124 based on the count value 'word'. When word[1:0] is 0, counter 102 sets the start signal of latch circuit 124a high. When word[1:0] is 1, counter 102 sets the start signal of latch circuit 124b high. When word[1:0] is 2, counter 102 sets the start signal of latch circuit 124c high. When word[1:0] is 3, counter 102 sets the start signal of latch circuit 124d high.

[0084] The data of one character latched by latch circuit 124a, one character latched by latch circuit 124b, one character latched by latch circuit 124c, and one character latched by latch circuit 124d are sequentially combined to generate a data segment SC [15:0]. The data segment SC [15:0] is then input to interleaving circuit 105.

[0085] After interleaving by the interleaving circuit 105, the data of one segment SC [15:0] is input to the decoder 106. When 16 segments SC [15:0] are input, the decoder 106 constructs a matrix MX using the 16 segments SC [15:0] and performs error correction by decoding the matrix MX. The decoder 106 outputs the 16 segments SC data sequentially from the error-corrected matrix MX. Each time the decoder 106 outputs one segment SC data [15:0], the data of that segment SC [15:0] is deinterleaved by the deinterleaving circuit 107.

[0086] Counter 110 counts the number of symbols output by the self-deinterleaving circuit 107 in units of characters. Furthermore, counter 110 calculates the segment number sect based on the count value of the number of characters and equation (1).

[0087] Output buffer 108 includes selector 125. Selector 125 has four input terminals. One character [3:0] from the data [15:0] of one segment SC output by the deinterleaving circuit 107 is input to one of the four input terminals of selector 125. Another character [7:4] from the data [15:0] of one segment SC output by the deinterleaving circuit 107 is input to another of the four input terminals of selector 125. A third character [11:8] from the data [15:0] of one segment SC output by the deinterleaving circuit 107 is input to the remaining input terminal of selector 125. A character [15:12] from the data [15:0] of one segment SC output by the deinterleaving circuit 107 is input to the remaining input terminal of selector 125. That is, for the four input terminals of the selector 125, input the four different characters that constitute the data [15:0] of a segment SC.

[0088] The word count value of counter 110, specifically word[1:0], is input as a selection signal to selector 125. When word[1:0] is 0, selector 125 outputs the data of one character [3:0] from the data of segment SC [15:0]. When word[1:0] is 1, selector 125 outputs the data of one character [7:4] from the data of segment SC [15:0]. When word[1:0] is 2, selector 125 outputs the data of one character [11:8] from the data of segment SC [15:0]. When word[1:0] is 3, selector 125 outputs the data of one character [15:11] from the data of segment SC [15:0].

[0089] The reverse rotation circuit 109 includes a latch circuit 126, a selector 127, and a rotation count calculation circuit 128.

[0090] Selector 127 has four input terminals. For one of the four input terminals of selector 127, data after performing a rotation of 0 on the data output from selector 125 (i.e., the data without rotation) is input. For another of the four input terminals of selector 127, data after performing a rotation of 1 on the data output from selector 125 is input. For yet another of the four input terminals of selector 127, data after performing a rotation of 2 on the data output from selector 125 is input. For the remaining one of the four input terminals of selector 127, data after performing a rotation of 3 on the data output from selector 125 is input.

[0091] The rotation count calculation circuit 128 calculates the rotation count using the same calculation method as the rotation count calculation circuit 123 that uses the segment number input from the counter 110. The rotation count obtained by the rotation count calculation circuit 128 is input as a selection signal to the selector 127. The selector 127 outputs a one-character data selected by the selection signal, which is either reverse-rotated or not reverse-rotated. The one-character data output by the selector 127 is latched by the latch circuit 126.

[0092] Therefore, when the data of the four characters constituting a certain segment SC is input to the inverse rotation circuit 109, the inverse rotation circuit 109 can perform an inverse conversion of the data rotation corresponding to the segment number sect for each of the four characters.

[0093] The data of one character latched in the latch circuit 126 is output from the output terminal 111.

[0094] As shown in Figure 10, the rotation circuit 103, the reverse rotation circuit 109, the counter 102, and the counter 110 are implemented using simple circuit configurations. That is, depending on the implementation, the switching operation of the switching mode, which varies for each segment SC, is realized using simple circuits.

[0095] Figure 11 is a diagram showing an example of the state of each signal in the decoding circuit 18 of the implemented configuration. In this figure, starting from the top, the waveforms of the clock signals driving each component of the decoding circuit 18, the input data input to input terminal 101, the outputs of latch circuit 124a, latch circuit 124b, latch circuit 124c, latch circuit 124d, the output of interleaving circuit 105, the number of words counted by counter 102, the segment number obtained by counter 102, and the rotation number obtained by rotation number calculation circuit 123 are all displayed. Additionally, in this figure, WD#Y (Y is an integer greater than or equal to 0) displays the Y-th character input to input terminal 101 from the beginning of the user data.

[0096] In Figure 11, user data is input starting from time t0. Counter 102 begins counting the number of words from time t1, which is two clock cycles after time t0. During the period from time t0 to time t4, which is five clock cycles after time t0, the segment number obtained by counter 102 is "0", and during this period, the rotation count obtained by rotation count calculation circuit 123 is "0".

[0097] At time t1, after two clock cycles from time t0, character WD#0 is latched in latch circuit 124a. At time t2, after one clock cycle from time t1, character WD#1 is latched in latch circuit 124b. At time t3, after one clock cycle from time t2, character WD#2 is latched in latch circuit 124c. At time t4, after one clock cycle from time t3, character WD#3 is latched in latch circuit 124d.

[0098] As described above, from time t0 to time t4, the rotation number obtained by the rotation number calculation circuit 123 is "0". Therefore, for the characters WD#0 to WD#3 latched in the latch circuit 124 corresponding to time t1 to time t4 respectively, the data rotation with rotation number "0" is performed (i.e., no data rotation is performed).

[0099] At time t5, after one clock cycle from time t4, the interleaving circuit 105 obtains characters WD#0~WD#3 as data for segment SC#0, and performs data interleaving for segment SC#0.

[0100] During the period from time t4 to time t8, which is 4 clock cycles from time t4, the segment number section obtained by counter 102 is "1", and during this period, the rotation number obtained by rotation count calculation circuit 123 is "1".

[0101] At time t5, character WD#4 is latched in latch circuit 124a. At time t6, one clock cycle has elapsed since time t5, character WD#5 is latched in latch circuit 124b. At time t7, one clock cycle has elapsed since time t6, character WD#6 is latched in latch circuit 124c. At time t8, one clock cycle has elapsed since time t7, character WD#7 is latched in latch circuit 124d.

[0102] From time t4 to time t8, the rotation number obtained by the rotation number calculation circuit 123 is "1". Therefore, the data rotation with rotation number "1" is performed on the characters WD#0 to WD#3 latched in the latch circuit 124 corresponding to time t5 to time t8 respectively.

[0103] At time t9, after one clock cycle from time t8, the interleaving circuit 105 obtains the characters WD#4~WD#7 after each of the data rotated by the number "1" and uses them as the data for segment SC#1, and performs interleaving of the data for segment SC#1.

[0104] Thus, on the one hand, the number of rotations is changed for each segment SC, and on the other hand, data rotation and interleaving are performed sequentially for multiple segments SC. Moreover, at time t10, the interleaving of the 16th segment SC, i.e. segment SC#15, is completed. In decoder 106, matrix MX is constructed by the 16th segment SC, and matrix MX is decoded.

[0105] As described above, according to the embodiment, during the read operation, the memory controller 10 reads user data from the non-volatile memory 20. The decoding circuit 18 decodes the user data read from the non-volatile memory 20. In the decoding circuit 18, the rotation circuit 103 rotates the arrangement order of the symbols within a segment SC by a number varying according to the segment number, for each of the plurality of segments SC in which the symbol row of the user data is divided according to a predetermined length. As described above, the segment number corresponds to the position of the segment SC in the symbol row. That is, the rotation circuit 103 rotates the data of each segment SC by a number of rotations corresponding to the position of the segment SC. The interleaving circuit 105 interleaves each of the plurality of segments SC after data rotation. The decoder 106 decodes the plurality of segments SC using the same bit. The deinterleaving circuit 107 deinterleaves each of the plurality of segments SC after decoding. The inverse rotation circuit 109 performs inverse data rotation on each segment SC after deinterleaving. The decoding circuit 18 outputs a symbol line combining the multiple segments SC after inverse data rotation, and the memory controller 10 stores the symbol line output by the self-decoding circuit 18 in the data buffer 12.

[0106] For each segment SC, in addition to implementing the common interleaving mode across multiple segments SC, a data rotation mode is also implemented based on the segment number. Therefore, even if a cycle error occurs, when the product code is constructed from multiple segments SC, the error can be prevented from concentrating in a specific correction block C or a specific correction block R. Therefore, memory system 1 has a higher tolerance for cycle errors.

[0107] Furthermore, as illustrated in Figure 10, a simple circuit is used to rotate the data that causes the switching mode to vary according to the symbol number.

[0108] That is, depending on the implementation, the circuit size of the decoding circuit 18 can be reduced while enabling decoding with higher tolerance to periodic errors. In other words, the decoding circuit 18 can appropriately correct periodic errors.

[0109] Furthermore, according to the embodiment, the rotation count calculation circuit 123 obtains the rotation count by calculating using the segment number. The rotation circuit 103 performs data rotation using the rotation count obtained by the rotation count calculation circuit 123.

[0110] Therefore, for each segment SC, the order of the conversion symbols can vary depending on the segment.

[0111] Furthermore, according to the embodiment, during the write operation, the memory controller 10 reads user data from the data buffer 12. The encoding circuit 17 decodes the user data read from the data buffer 12. In the encoding circuit 17, the rotation circuit 203, like the rotation circuit 103, performs data rotation on each of the plurality of segments SC with a number of rotations corresponding to the position of the segments SC. The interleaving circuit 205 interleaves each of the plurality of segments SC after data rotation. The encoder 206 generates corresponding bits by encoding the plurality of segments SC. The memory controller 10 writes the user data and corresponding bits read from the data buffer 12 into the non-volatile memory 20.

[0112] Therefore, the decoding of the above-mentioned decoding circuit 18 can be realized.

[0113] Furthermore, in the above example, as one example of processing the arrangement order of transformation symbols for transformation modes that vary depending on each segment SC, data rotation (i.e., circular shift) is listed. The processing of the arrangement order of transformation symbols for transformation modes that vary depending on each segment SC is not limited to data rotation (i.e., circular shift).

[0114] Furthermore, in the example above, the rotation circuit 103 performs data rotation on each of the plurality of characters contained in a segment SC. The unit of data rotation performed by the rotation circuit 103 is not necessarily in units of characters. The rotation circuit 103 can perform data rotation in units of segments SC, or it can perform data rotation in units of two characters.

[0115] Furthermore, in the above example, interleaving is listed as one example of the processing of the arrangement order of transformation symbols based on common transformation modes among multiple SC segments. The processing of the arrangement order of transformation symbols based on common transformation modes among multiple SC segments is not limited to interleaving.

[0116] Furthermore, in the example above, it has been explained how to encode a complex number of segments SC using product codes for error correction. The encoding of a complex number of segments SC is not limited to this.

[0117] Furthermore, each of the aforementioned encoding / decoding unit 14, encoding circuit 17, and decoding circuit 18 can also be applied to devices other than the memory system 1. For example, each of the encoding / decoding unit 14, encoding circuit 17, and decoding circuit 18 can also be applied to a communication device.

[0118] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, with omissions, substitutions, and modifications made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are also included within the scope of the invention described in the claims and its equivalents.

[0119] 1: Memory System 10: Memory controller 11: Control Department 12: Data Buffer 13: Memory I / F 14: Encoding / Decoding Section 15: Host I / F 16: Internal bus 17: Encoding Circuit 18: Decoding Circuit 20: Non-volatile memory 30: Host 101, 201: Input terminals 102,110,202: Counters 103,203: Rotating circuit 104,204: Input buffers 105, 205: Interleaving circuit 106: Decoder 107: Deinterleaving circuit 108: Output Buffer 109: Reverse Rotation Circuit 111,207: Output terminals 121, 124, 124a, 124b, 124c, 124d, 126: Latch circuits 122, 125, 127: Selectors 123, 128: Rotation Count Calculation Circuit 206: Encoder C0~C15: Correction Blocks D: Terminal E: terminal MX: Matrix R0~R15: Correction Blocks SC#0~SC#15: Section sect: section number t0~t10: Time points WD#0~WD#7: Characters WD#56~WD#59: Characters WD#60~WD#63: Characters word: count value

Claims

1. A memory system comprising: a non-volatile first memory; a volatile second memory; and a memory controller, configured to: read a first symbol line from the first memory; perform a first conversion operation on each of a plurality of first segments of the read first symbol line divided according to a first length, the first conversion operation being to convert the arrangement order of symbols within a first segment using a conversion mode corresponding to the position of the first segment in the first symbol line; perform a second conversion operation on each of the plurality of first segments after the first conversion operation, the second conversion operation being to convert the arrangement order of symbols within a first segment using a conversion mode common to the plurality of first segments; and perform decoding using the same bit on the plurality of first segments after the second conversion operation. Perform the inverse conversion of the second conversion operation, i.e., the third conversion operation, on each of the plurality of first segments after the above decoding; perform the inverse conversion of the first conversion operation, i.e., the fourth conversion operation, on each of the plurality of first segments after the above third conversion operation; and store the second symbol row formed by combining the plurality of first segments after the above fourth conversion operation in the above second memory.

2. The memory system of claim 1, wherein the memory controller is configured to, in the first conversion operation, convert the arrangement order of symbols in each of the first sub-segments contained in the first segment to each of the plurality of first sub-segments divided by a first segment according to a factor of the second length, in a conversion mode corresponding to the position of the first segment in the first symbol row.

3. The memory system of claim 2, wherein the memory controller is configured such that, in the first conversion operation, by calculating the first number using the position, the arrangement order of the symbols in each first sub-segment is cyclically shifted only according to the number of times the first number is calculated.

4. The memory system of claim 1, wherein the memory controller is configured to read a third symbol line from the second memory, perform a fifth conversion operation on each of the plurality of second segments divided according to each first length of the read third symbol line, wherein the fifth conversion operation is to convert the arrangement order of symbols in a second segment using a conversion mode corresponding to the position of the second segment in the third symbol line, and perform a sixth conversion operation on each of the plurality of second segments after the fifth conversion operation, wherein the sixth conversion operation is to convert the arrangement order of symbols in a second segment using a conversion mode common to the plurality of second segments, generate a corresponding bit by means of error correction code of the plurality of first segment groups after the sixth conversion operation, and write the third symbol line and the corresponding bit to the second memory.

5. A memory system as claimed in any of claims 1 to 4, wherein the memory controller is configured to, in the second transition operation, interleave all symbols within a first segment for each of the plurality of first segments following the first transition operation.

6. The memory system of any of the requests 1 to 4, wherein the aforementioned corresponding bits are corresponding bits of the product code.

7. A decoding circuit comprising: a first terminal input to a first symbol line; a first conversion circuit that, for each of a plurality of first segments dividing the first symbol line according to a first length, converts the arrangement order of symbols within a first segment using a conversion mode corresponding to the position of the first segment in the first symbol line; a second conversion circuit that, for each of the plurality of first segments after conversion by the first conversion circuit, converts the arrangement order of symbols within a first segment using a conversion mode common to the plurality of first segments; a decoder that performs decoding using the same bit on the plurality of first segments after conversion by the second conversion circuit; and a third conversion circuit that performs the inverse conversion of the second conversion circuit on each of the plurality of first segments after decoding. The fourth conversion circuit performs the inverse conversion of the first conversion circuit on each of the plurality of first segments after the inverse conversion of the third conversion circuit; and the second terminal outputs a second symbol row formed by combining the plurality of first segments after the inverse conversion of the fourth conversion circuit.

Images