Network packet processing apparatus and network packet processing method

Abstract

A network packet processing apparatus includes a receive (RX) ring buffer, a transmit (TX) ring buffer, a plurality of queues, a plurality of first processor cores, and a second processor core. The first processor cores read a plurality of sets of RX packet descriptors in turn according to a polling order, and process a plurality of sets of packets in parallel. Each first processor core generates at least one TX packet descriptor and at least one queue element for a set of packets, and writes the at least one queue element into a corresponding queue, where the at least one queue element has an end flag set therein. The second processor core reads the queues in turn according to the polling order. When reading the end flag, the second processor core switches to read a next queue according to the polling order.

Description

[Technical Field]

[0001] This invention relates to packet forwarding, and more particularly to a network packet processing device and related network packet processing method with multi-core parallel processing capability and packet order preservation capability. [Previous Technology]

[0002] A gateway is a common network device used to connect different networks and forward packets from one network to another, such as packet forwarding between wired and wireless networks. A network processing unit (NPU) is a high-speed programmable processor specifically designed for packet processing (e.g., packet forwarding). It has features and architectures to accelerate packet processing efficiency. However, with the continuous increase in network bandwidth, packets are transmitted at higher rates, requiring the NPU to also be able to quickly process these high-speed incoming packets. A traditional solution might use a multi-core network processor. Multi-core parallel processing can effectively improve the processing performance and packet forwarding throughput of the network processor. However, because different processor cores within the network processor may process packets at different speeds, multi-core parallel processing can lead to out-of-order packet processing. Therefore, an innovative design is needed that can utilize multi-core parallel processing technology to improve packet forwarding performance while still maintaining packet order. [Summary of the Invention]

[0003] One of the objectives of this invention is to provide a network packet processing device and related network packet processing method with multi-core parallel processing capability and packet order preservation capability.

[0004] In one embodiment of the present invention, a network packet processing apparatus is disclosed, comprising a receive ring buffer, a transmit ring buffer, a plurality of queues, a plurality of first processor cores, and a second processor core. The receive ring buffer includes a plurality of storage blocks, each storage block being used to temporarily store a receive packet descriptor of the packet before the packet is processed. The transmit ring buffer includes a plurality of storage blocks, each storage block being used to temporarily store a transmit packet descriptor of the packet after the packet is processed. The plurality of first processor cores are used to sequentially read multiple arrays of receive packet descriptors from the receive ring buffer according to a polling order, and to perform parallel processing on multiple arrays of packets according to the multiple arrays of receive packet descriptors. The plurality of queues are respectively configured for the plurality of first processor cores. Each of the plurality of first processor cores is also used to generate at least one transmit packet descriptor and at least one queue element corresponding to the at least one transmit packet descriptor for a set of packets, and to add the at least one queue element to a corresponding queue among the plurality of queues. The at least one queue element is set with an end marker. The second processor core is used to sequentially read the plurality of queues according to the polling order, and to write a transmit packet descriptor corresponding to one queue element read from each queue to the transmit ring buffer. When the second processor core reads the end marker from a current queue, it switches to read the next queue according to the polling order.

[0005] In one embodiment of the present invention, a network packet processing method is disclosed, comprising: using a plurality of first processor cores to sequentially read a plurality of receive packet descriptors from a receive ring buffer according to a polling order, and performing parallel processing on the plurality of packets according to the plurality of receive packet descriptors, wherein the receive ring buffer includes a plurality of storage blocks, each storage block being used to temporarily store a receive packet descriptor of a packet before a packet is processed; configuring a plurality of queues respectively to the plurality of first processor cores; and using each of the plurality of first processor cores to generate at least one transmit packet descriptor and a corresponding at least one transmit packet descriptor for a group of packets. The process involves: a transmission packet descriptor having at least one queue element, and adding the at least one queue element to a corresponding queue among a plurality of queues, wherein the at least one queue element is set with an end marker; and a second processor core sequentially reading the plurality of queues according to the polling order, and writing a transmission packet descriptor corresponding to a queue element read from each queue to a transmission ring buffer, wherein the transmission ring buffer includes a plurality of storage blocks, each storage block being used to temporarily store a transmission packet descriptor of the packet after the packet is processed, and when the second processor core reads the end marker from a current queue, it switches to reading the next queue according to the polling order.

[0006] The network packet processing apparatus of the present invention does not require an additional sequence number to be assigned to each packet received by the network port so as to maintain the order of packets in subsequent processing, thereby reducing overhead. In addition, when the order-keeping core approaches its processing limit, the load on the order-keeping core can be reduced by dynamically aggregating packets in the processing core. This not only ensures the order of packets, but also greatly improves the overall packet forwarding efficiency through multi-core parallel processing, maximizing the potential of parallel processing.

Implementation Method

[0007] Certain terms are used in the specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This specification and claims do not distinguish components by name differences, but by functional differences. The terms "comprising" and "including" used throughout the specification and claims are open-ended and should be interpreted as "comprising but not limited to". Furthermore, the terms "coupled" or "coupled" herein include any direct and indirect electrical connection means. Therefore, if a first device is described as coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices and connection means.

[0008] Figure 1 is a schematic diagram of a network packet processing apparatus according to an embodiment of the present invention. For example, the network packet processing apparatus 100 can be used by a network device (e.g., a gateway). As shown in Figure 1, the network packet processing apparatus 100 may include a receive (RX) ring buffer (hereinafter referred to as "RX ring buffer") 102, a transmit (TX) ring buffer (hereinafter referred to as "TX ring buffer") 104, a plurality of processor cores 106_1 to 106_M(), 108, and 110, a plurality of network ports 112 and 114, a plurality of queues 116_1 to 116_M(), and dynamic random access memory (DRAM) 118. Please note that Figure 1 only illustrates elements relevant to the present invention; in practice, the network packet processing apparatus 100 may include additional elements to implement the specified functions.

[0009] The network packet processing device 100 receives a plurality of packets (i.e., network packets) PKTs from the network connection port 112. Then, the direct memory access (DMA) controller (not shown) copies and writes each packet PKT to a packet buffer 124 configured in the dynamic random access memory 118. When the packet buffer 124 is initialized, it can be divided into a plurality of storage blocks according to a fixed block size, wherein these storage blocks are used to store the plurality of packet PKTs respectively. In this embodiment, the packet buffer 124 is disposed in the dynamic random access memory 118; however, the present invention is not limited thereto. In fact, the packet buffer 124 can be disposed in any element with data storage capability. For example, in another embodiment, the packet buffer 124 can be disposed in static random access memory (SRAM).

[0010] In this embodiment, processor cores 106_1 to 106_M, 108, and 110 can reside in the same multi-core network processor, wherein processor cores 106_1 to 106_M can serve as processing cores, and processor core 110 can serve as an order-preserving core. Furthermore, to eliminate the RX ring buffer update problem that may be caused by multi-core contention among processor cores 106_1 to 106_M, this embodiment can utilize another processor core 108, other than processor cores 106_1 to 106_M, to be responsible for updating the CPU index cpu_idx used to indicate the usage status of the RX ring buffer 102, without the intervention of processor cores 106_1 to 106_M.

[0011] The RX ring buffer 102 and TX ring buffer 104 can be configured in static random access memory, but the present invention is not limited thereto. The RX ring buffer 102 is configured to handle the reception of packet PKTs from network port 112. The TX ring buffer 104 is configured to handle the transmission of packet PKTs to be forwarded via network port 114 under the control of a direct memory access controller (not shown). Specifically, the RX ring buffer 102 is divided into a plurality of storage blocks 120, each storage block 120 being used to temporarily store the receive packet descriptor (RX packet descriptor, hereinafter referred to as "RX packet descriptor") RXD of a packet PKT before it is processed, and the TX ring buffer 104 is divided into a plurality of storage blocks 122, each storage block 122 being used to temporarily store the transmit packet descriptor (TX packet descriptor, hereinafter referred to as "TX packet descriptor") TXD of a packet after it is processed. Each packet descriptor can record some metadata corresponding to the packet. For example, a packet descriptor can have multiple fields, including the packet length field `pkt_len`, the packet address field `pkt_addr`, etc. Therefore, processor cores 106_1 to 106_M can refer to the metadata recorded in the RX packet descriptor to read the information carried by the corresponding packet stored in dynamic random access memory 118, and then perform some packet processing to generate the processed packet that will be forwarded through network port 114. After packet processing is completed, processor cores 106_1 to 106_M generate TX packet descriptors for the packets to be forwarded. While maintaining the packet order, processor core 110 writes the TX packet descriptors of the packets to be forwarded to the TX ring buffer 104. The direct memory access controller can then refer to the metadata recorded in the TX packet descriptors to read the corresponding packets from the dynamic random access memory 118 for packet forwarding.

[0012] In this embodiment, processor cores 106_1 to 106_M are used to perform parallel processing of packets, and processor core 110 is used to ensure the order of packets. In other words, the network packet processing device 100 has multi-core parallel processing capability and packet ordering capability. The operational details of multi-core parallel processing and packet ordering will be explained in conjunction with the drawings below.

[0013] First, the network packet processing device 100 will perform initialization. The plurality of storage blocks 120 of the RX ring buffer 102 will be continuously divided into a plurality of storage blocks 121. Each group of storage blocks in the plurality of storage blocks 121 is used to store a group of received packet descriptors. The number of each group of storage blocks (i.e., the number of each group of received packet descriptors) can be adjusted according to design considerations. For example, each group of storage blocks 121 will contain A consecutive storage blocks 120, and the RX ring buffer 102 can be divided into a total of B groups of storage blocks. In other words, the RX ring buffer 102 will be divided into B groups according to the method of A RX packet descriptors RXD per group, for example, A=8 and B=192. However, the present invention is not limited thereto. In addition, the value of the packet aggregation number Agg_Num will be initialized to 1 (that is, Agg_Num=1), and the length of each of the queues 116_1 to 116_M is L. Therefore, each queue 116_i (i={1, 2, …, M}) can store L queue elements. In this embodiment, each queue element can include the TX packet descriptor address field TXD_address and the end flag field end_flag. Queues 116_1 to 116_M will all be initialized to 0.

[0014] After receiving a plurality of packet PKTs at network connection port 112, the corresponding RX packet descriptors of the plurality of packet PKTs are written to the RX ring buffer 102. When the RX ring buffer 102 contains RX packet descriptors to be processed, the processor cores 106_1 to 106_M can read the RX packet descriptors from the RX ring buffer 102 for packet forwarding. As mentioned above, the RX ring buffer 102 is divided into B groups according to the method of A RX packet descriptors RXD per group. Therefore, the RX packet descriptors RXD stored in the RX ring buffer 102 can be divided into B groups of RX packet descriptors. The processor cores 106_1 to 106_M will then... A polling sequence (e.g., ) is used to read the B groups of RX packet descriptors in the RX ring buffer 102 in turn. Assuming the number of RX packet descriptors in the B groups is 192 (B=192), each group of RX packet descriptors contains 8 RX packet descriptors (A=8), and the number of processor cores 106_1 to 106_M is 3 (M=3), then the starting addresses of the 192 groups of RX packet descriptors will be sequentially allocated to processor cores 106_1 to 106_3. Each processor core will process 64 groups of RX packet descriptors (each group of RX packet descriptors contains 8 RX packet descriptors RXD), where processor core 106_1 is responsible for processing the (1+3*k)th group of RX packet descriptors (k={0, 3, 4, 5, 6, 7, 8, 9, 10 ... Processor core 106_2 is responsible for processing the (2+3*k)th group of RX packet descriptors (k={0, 1, …, 63}), and processor core 106_2 is responsible for processing the (3+3*k)th group of RX packet descriptors (k={0, 1, …, 63}).

[0015] Furthermore, processor cores 106_1 to 106_M perform parallel processing on multiple arrays of packets based on the multiple arrays of received packet descriptors obtained respectively. In other words, while one processor core is processing a set of packets (e.g., 8 packets) based on a set of received packet descriptors obtained from the RX ring buffer 102, another processor core can process another set of packets (e.g., 8 packets) based on another set of received packet descriptors obtained from the RX ring buffer 102. Since the network packet processing device 100 has multi-core parallel processing capabilities, the overall packet forwarding efficiency can be improved.

[0016] Please refer to Figure 1 and Figure 2 together. Figure 2 is a flowchart of the operation process of any processor core 106_i (i={1, 2, …, M}) among the processor cores 106_1 to 106_M shown in Figure 1. Assuming that roughly the same result can be obtained, the steps do not necessarily have to be executed in the exact order shown in Figure 2. In step S202, processor core 106_i (i={1, 2, …, M}) obtains a set of receive packet descriptors (e.g., 8 receive packet descriptors RXD) from the RX ring buffer 102 in round-robin order to process a set of packets (e.g., the 8 packets corresponding to the 8 receive packet descriptors RXD respectively). In step S204, processor core 106_i (i={1, 2, …, M}) determines whether the current value of the packet aggregation number Agg_Num is greater than 1 (i.e., determines whether packet aggregation is needed to reduce the load on the order-keeping core (i.e., processor core 110)). As mentioned earlier, the TX ring buffer 104 is configured to handle the transmission of packet PKTs that are to be forwarded via network port 114 under the control of the direct memory access controller (not shown). In this embodiment, the direct memory access controller (not shown) used to perform packet forwarding can support reading and forwarding multiple aggregated packets through a single transmission packet descriptor TXD. In addition, the value of the packet aggregation number Agg_Num is initialized to 1 (i.e., Agg_Num=1). However, the value of the packet aggregation number Agg_Num will actually increase with the processor core 106_i (i={1, 2, …, M}). The usage rate of the corresponding column 116_i (i={1, 2, …, M}) paired with M} is dynamically adjusted.

[0017] Assuming the current value of the number of aggregated packets, Agg_Num, is not greater than 1, the process proceeds to step S206. In step S206, processor core 106_i (i={1, 2, …, M}) generates a TX packet descriptor TXD based on the data of a single packet PKT, and temporarily stores this TX packet descriptor TXD in a storage device (e.g., dynamic random access memory 118). In this embodiment, the TX packet descriptor TXD generated by processor core 106_i (i={1, 2, …, M}) in step S206 is temporarily stored in dynamic random access memory 118. However, the present invention is not limited to this. In fact, the TX packet descriptor TXD can be temporarily stored in any element with data storage capability. For example, in another embodiment, the TX packet descriptor TXD generated by processor core 106_i (i={1, 2, …, M}) can be temporarily stored in static random access memory.

[0018] Figure 3 is a schematic diagram of the TX packet descriptor format according to an embodiment of the present invention. The TX packet descriptor TXD has multiple fields, such as the type field Type (1 bit), the packet length field pkt_len (16 bits), the packet address field pkt_addr (32 bits), etc. The type field Type is used to indicate the type of the TX packet descriptor TXD. For example, when the processor core generates the TX packet descriptor TXD based on the data of a single packet PKT, the type field Type will be written with a logical value of 0 (that is, Type=0), and when the processor core generates the TX packet descriptor TXD based on the data of an aggregated packet PktAgg (which is formed by aggregating multiple packet PKTs), the type field Type will be written with a logical value of 1 (that is, Type=1). Additionally, the packet address field pkt_addr is used to indicate the address of the packet corresponding to the TX packet descriptor TXD in the storage device. For example, when the processor core 106_i (i={1, 2, …, M}) generates the TX packet descriptor TXD based on the data of a single packet PKT, the packet address field pkt_addr will be written to the address of the single packet PKT in the storage device (e.g., the packet buffer 124 configured inside the dynamic random access memory 118). When the processor core 106_i (i={1, 2, …, M}) generates the TX packet descriptor TXD based on the data of the aggregated packet PktAgg (which is formed by aggregating multiple packet PKTs), the packet address field pkt_addr will be written to the address of the aggregated packet PktAgg in the storage device (e.g., the dynamic random access memory 118).

[0019] In step S206, after the processor core 106_i (i={1, 2, …, M}) generates a TX packet descriptor TXD based on the data of a single packet PKT, it will also generate a column element based on the TX packet descriptor TXD (Type=0) and add this column element to the corresponding column 116_i (i={1, 2, …, M}). The TX packet descriptor address field TXD_address of this column element will be written to the address of the TX packet descriptor TXD (Type=0) in the storage device (e.g., dynamic random access memory 118). Furthermore, the end flag field end_flag of this column element will be determined based on whether the single packet PKT corresponding to the TX packet descriptor TXD (Type=0) is a group-end packet (i.e., the processor core 106_i (i={1, 2, …, M}) is a group-end packet). In step S202, the last packet in a group of packets corresponding to a set of received packet descriptors obtained from the RX ring buffer 102 is used to determine whether to set the end flag end_flag=1. In other words, if the single packet PKT corresponding to the TX packet descriptor TXD (Type=0) is not the last packet in the group, the end flag field end_flag of the column element will be written with a logical value of 0 (that is, end_flag=0) and the end flag will not be set. On the other hand, if the single packet PKT corresponding to the TX packet descriptor TXD (Type=0) is the last packet in the group, the end flag field end_flag of the column element will be written with a logical value of 1 (that is, end_flag=1) and the end flag will be set.

[0020] Assuming that step S204 determines that the current value of the number of aggregated packets, Agg_Num, is greater than 1, the process will proceed to step S208. In step S208, processor core 106_i (i={1, 2, …, M}) generates an aggregated packet PktAgg and temporarily stores this aggregated packet PktAgg in a storage device (e.g., dynamic random access memory 118). In this embodiment, the aggregated packet PktAgg generated by processor core 106_i (i={1, 2, …, M}) in step S208 is temporarily stored in dynamic random access memory 118. However, the present invention is not limited to this. In fact, the aggregated packet PktAgg can be temporarily stored in any element with data storage capability. For example, in another embodiment, the aggregated packet PktAgg generated by processor core 106_i (i={1, 2, …, M}) can be temporarily stored in static random access memory.

[0021] Figure 4 is a schematic diagram of the aggregate packet format according to an embodiment of the present invention. In this embodiment, each aggregate packet PktAgg can aggregate up to 4 packets PKT and has a plurality of fields, such as the number of aggregated packets Num, the next aggregated packet Next field, 4 packet length fields pkt1_len (16 bits), pkt2_len (16 bits), pkt3_len (16 bits), pkt1_len (16 bits), 4 packet address fields pkt1_addr (32 bits), pkt2_addr (32 bits), pkt3_addr (32 bits), pkt4_addr (32 bits), and the next aggregated packet address next PktAgg_addr (32 bits), etc. The `Num` field, representing the number of packets being aggregated, indicates the maximum number of packets involved in the aggregation. The maximum value is 4. Therefore, the value of `Num` updates as the number of packets participating in the aggregation increases. If the number of packets to be aggregated exceeds 4 (i.e., ``), the current aggregated packet `PktAgg` can be connected to the next aggregated packet `PktAgg` by linking the `Next` field (`Next=1`) with the address of the next aggregated packet `nextPktAgg_addr`. If the number of packets to be aggregated is no greater than 4 (i.e., ``), the `Next` field will be written with a logical value of 0 (i.e., `Next=0`), indicating that the current aggregated packet `PktAgg` does not need to be connected to the next aggregated packet `PktAgg`.

[0022] The packet address field pkt1_addr is used to indicate the address of the first packet PKT participating in the aggregation in the storage device (e.g., the packet buffer 124 configured inside the dynamic random access memory 118), the packet address field pkt2_addr is used to indicate the address of the second packet PKT participating in the aggregation in the storage device (e.g., the packet buffer 124 configured inside the dynamic random access memory 118), the packet address field pkt3_addr is used to indicate the address of the third packet PKT participating in the aggregation in the storage device (e.g., the packet buffer 124 configured inside the dynamic random access memory 118), and the packet address field pkt4_addr is used to indicate the address of the fourth packet PKT participating in the aggregation in the storage device (e.g., the packet buffer 124 configured inside the dynamic random access memory 118). Additionally, the packet length field pkt1_len indicates the packet length of the first packet PKT participating in the aggregation, the packet length field pkt2_len indicates the packet length of the second packet PKT participating in the aggregation, the packet length field pkt3_len indicates the packet length of the third packet PKT participating in the aggregation, and the packet length field pkt4_len indicates the packet length of the fourth packet PKT participating in the aggregation.

[0023] In this embodiment, the processor core 106_i (i={1, 2, …, M}) generates an aggregated packet PktAgg based on the current value of the packet aggregation number Agg_Num. When the value of the packet aggregation number field Num is updated with the number of packets participating in the aggregation and reaches the value of the packet aggregation number Agg_Num (step S210), the process proceeds to step S212. In addition, when the value of the packet aggregation number field Num has not yet reached the value of the packet aggregation number Agg_Num, but the aggregated packet PktAgg already contains the last packet of the group (that is, the last packet in one group of packets corresponding to a group of received packet descriptors obtained by the processor core from the RX ring buffer 102 in step S202), since the aggregated packet PktAgg already contains all the packets in the same group, the process also proceeds to step S212.

[0024] In step S212, after the processor core 106_i (i={1, 2, …, M}) generates a TX packet descriptor TXD based on the data of the aggregate packet PktAgg and temporarily stores this TX packet descriptor TXD in a storage device (e.g., dynamic random access memory 118), a queue element is generated based on the TX packet descriptor TXD (Type=1) and this queue element is added to the corresponding queue 116_i (i={1, 2, …, M}). The TX packet descriptor address field TXD_address of this queue element is written to the address of the TX packet descriptor TXD (Type=1) in the storage device (e.g., dynamic random access memory 118). In addition, the end flag field end_flag of this queue element is based on the TX packet descriptor TXD. Whether the aggregate packet PktAgg corresponding to (Type=1) contains the last packet in a group (that is, the last packet in a group of packets corresponding to a group of received packet descriptors obtained by the processor core from the RX ring buffer 102 in step S202) determines whether to set the end flag end_flag=1. In other words, if the aggregate packet PktAgg corresponding to the TX packet descriptor TXD (Type=1) does not contain the last packet in a group, the end flag field end_flag of the column element will be written with a logical value of 0 (that is, end_flag=0) and the end flag will not be set. On the other hand, if the aggregate packet PktAgg corresponding to the TX packet descriptor TXD (Type=1) contains the last packet in a group, the end flag field end_flag of the column element will be written with a logical value of 1 (that is, end_flag=1) and the end flag will be set. In this embodiment, the TX packet descriptor TXD generated by the processor core 106_i (i={1, 2, …, M}) in step S212 is temporarily stored in dynamic random access memory 118. However, the present invention is not limited to this. In fact, the TX packet descriptor TXD can be temporarily stored in any element with data storage capability. For example, in another embodiment, the TX packet descriptor TXD generated by the processor core 106_i (i={1, 2, …, M}) can be temporarily stored in static random access memory.

[0025] Processor cores 106_1 to 106_M are processing cores used to read M sets of RX packet descriptors (each set of RX packet descriptors contains a plurality of RX packet descriptors RXD) from the RX ring buffer 102, and perform multi-core parallel processing on the plurality of packets according to the M sets of received packet descriptors. The processed packets will enter the queues 116_1 to 116_M in the form of queue elements. The queues 116_1 to 116_M are respectively configured to processor cores 106_1 to 106_M. Therefore, processor core 106_i (i={1, 2, …, M}) will add the corresponding queue elements of the processed packets to the corresponding queue 116_i (i={1, 2, …, M}) in sequence. To ensure packet ordering, the network packet processing device 100 utilizes a dedicated ordering core (i.e., processor core 110) to read queue elements from queues 116_1 to 116_M and writes the TX packet descriptors (TXDs) to the TX ring buffer 104 in the correct order. However, when queue 116_i (i={1, 2, …, M}) approaches its capacity limit, it indicates that the ordering core (i.e., processor core 110) is about to reach its processing limit. To reduce the load on the ordering core (i.e., processor core 110), processor core 106_i (i={1, 2, …, M}) enables packet aggregation to effectively reduce the number of queue elements to be processed in queue 116_i (i={1, 2, …, M}). In step S214, processor core 106_i (i={1, 2, …, M}) checks the utilization rate (e.g., the percentage of elements in the queue to be processed) of the corresponding query column 116_i (i={1, 2, …, M}). When the utilization rate of column 116_i (i={1, 2, …, M}) is higher than the threshold_full, processor core 106_i (i=1, 2, …, M) increases the value of the packet aggregation number Agg_Num, for example, Agg_Num = Agg_Num*2 (step S216). When the utilization rate of queue 116_i (i={1, 2, …, M}) is lower than another threshold, threshold_empty, processor core 106_i (i={1, 2, …, M}) will reduce the value of the packet aggregation number Agg_Num, for example, Agg_Num = Agg_Num / 2 (step S218). Furthermore, if the utilization rate of queue 116_i (i={1, 2, …, M}) is between the two thresholds threshold_full and threshold_empty, processor core 106_i (i={1, 2, …, M}) can maintain the current value of the packet aggregation number Agg_Num.

[0026] As mentioned above, processor core 110 is a pre-order core. In this embodiment, processor core 110 will read the queues 116_1 to 116_M configured for processor cores 106_1 to 106_M in turn according to the same polling order (that is, the polling order in which processor cores 106_1 to 106_M read the complex array RX packet descriptors in the RX ring buffer 102 in turn), and write the TX packet descriptor TXD corresponding to the queue element read in each queue 116_i (i={1, 2, …, M}) to the TX ring buffer 104. When processor core 110 reads the end flag end_flag=1 from the current queue, it will switch to read the next queue according to the polling order. Please refer to Figure 1 and Figure 5 together. Figure 5 is a flowchart of the operation flow of processor core 110 shown in Figure 1. In step S502, the processor core 110 reads queue elements starting from the current queue in a polling order (e.g., ...). Each queue from 116_1 to 116_M outputs queue elements to the processor core 110 one by one according to the first-in-first-out (FIFO) principle. Whenever the processor core 110 reads the current queue element, it reads the TX packet descriptor TXD from the storage device (e.g., dynamic random access memory 118) according to the address recorded in the TX packet descriptor address field TXD_address in the current queue element, and writes the TX packet descriptor TXD to the TX ring buffer 104 (step S504). In step S506, the processor core 110 checks whether the current queue element has the end flag end_flag=1 set. If the current queue element does not have an end flag (end_flag=1), the processor core 110 will continue reading the next queue element from the current queue as the current queue read (step S502). If the current queue element has an end flag (end_flag=1), the processor core 110 will switch to read the next queue according to the polling order (step S508), and then the process will return to step S502.

[0027] In summary, the network packet processing device 100 of the present invention utilizes processor cores 106_1 to 106_M as processing cores to achieve multi-core parallel processing of a plurality of packets, and utilizes a dedicated processor core 110 as an order-preserving core to maintain the order of the plurality of packets after multi-core parallel processing. Furthermore, for the order-preserving processing of packets, since processor cores 106_1 to 106_M will read a complex array of RX packet descriptors from the RX ring buffer 102 in a polling order, and a dedicated processing core 110... The processor core 110 will use the same polling order to read the queues 116_1 to 116_M configured for the processor cores 106_1 to 106_M, and the queue element of the last packet in the corresponding group will be set with an end marker. Therefore, the dedicated processor core 110 can write the corresponding TX packet descriptors to the TX ring buffer 104 in sequence according to the packet receiving order, as shown in Figure 1. Assume that each group of RX packet descriptors has 4 RX packet descriptors, the number of processing cores is 3 (M=3), and the polling order is as follows. Processor core 106_1 sequentially adds four queue elements 126_1, 126_2, 126_3, and 126_4 to the corresponding queue 116_1. Queue elements 126_1, 126_2, 126_3, and 126_4 correspond to four consecutive packets (labeled 1, 2, 3, and 4), and queue element 126_4 has its end flag set to end_flag=1. Processor core 106_2 sequentially adds two queue elements 128_1 and 128_2 to the corresponding queue 116_2. Queue element 128_1 corresponds to an aggregated packet (Num=2) containing two consecutive packets (labeled 5 and 6), and queue element 128_2 corresponds to an aggregated packet (Num=2) containing two consecutive packets (labeled 7 and 8). Queue element 128_2 also has its end flag set to end_flag=1. Processor core 106_M adds a queue element 130 to the corresponding queue 116_2, where queue element 130 corresponds to an aggregated packet (Num=4) containing 4 consecutive packets (labeled as 9, 10, 11, 12), and queue element 130 sets the end flag end_flag=1.Because the polling order is as follows, processor core 110 will first read queue 116_1. When processor core 110 reads queue 116_1, it will sequentially read queue elements 126_1, 126_2, 126_3, and 126_4. Since queue element 126_4 has an end flag (end_flag) set, after reading queue element 126_4, processor core 110 will switch to read the next queue (i.e., queue 116_2) based on the polling order. When processor core 110 reads queue 116_2, it will sequentially read queue element 126_1, 126_2, 126_3, and 126_4. 1. 128_2: Since column element 128_2 has an end flag set, after reading column element 128_2, processor core 110 will switch to read the next column (i.e., column 116_M) based on the polling order. When processor core 110 reads column 116_M, it will read column element 130. Since column element 130 has an end flag set, after reading column element 130, processor core 110 will switch to read the next column (i.e., column 116_1) based on the polling order.

[0028] The network packet processing apparatus 100 of the present invention does not require an additional sequence number to be assigned to each packet received by the network port 112 so as to maintain the packet order in the future, thereby reducing overhead. Furthermore, when the order-preserving core (i.e., processor core 110) approaches its processing limit, the load on the order-preserving core (i.e., processor core 110) is reduced by dynamically aggregating packets in the processing cores (i.e., processor cores 106_1 to 106_M). This not only ensures the packet order but also significantly improves the overall packet forwarding efficiency through multi-core parallel processing, maximizing the potential of parallel processing. The above description is only a preferred embodiment of the present invention. All equivalent variations and modifications made within the scope of the claims of the present invention should be considered within the scope of the present invention. [Simplified Explanation of the Diagram]

[0029] Figure 1 is a schematic diagram of a network packet processing device according to an embodiment of the present invention. Figure 2 is a flowchart of the operation flow of the processor core shown in Figure 1 as the processing core. Figure 3 is a schematic diagram of a transmission packet descriptor format according to an embodiment of the present invention. Figure 4 is a schematic diagram of an aggregated packet format according to an embodiment of the present invention. Figure 5 is a flowchart of the operation flow of the processor core shown in Figure 1 as the order-preserving core.

Claims

1. A network packet processing apparatus, comprising: a receiving ring buffer, including a plurality of storage blocks, each storage block being used to temporarily store a receiving packet descriptor of the packet before the packet is processed; and a transmitting ring buffer, including a plurality of storage blocks, each storage block being used to temporarily store a transmitting packet descriptor of the packet after the packet is processed. Multiple rows; A plurality of first processor cores are configured to read multiple arrays of receive packet descriptors from the receive ring buffer in turn according to a polling order, and to perform parallel processing on multiple arrays of packets according to the multiple arrays of receive packet descriptors. The plurality of columns are respectively configured to the plurality of first processor cores. Each of the plurality of first processor cores is configured to generate at least one transmit packet descriptor and at least one column element corresponding to the at least one transmit packet descriptor for a set of packets, and to add the at least one column element to a corresponding column in the plurality of columns. The at least one column element is set with an end marker. And a second processor core, used to read the plurality of columns in turn according to the polling order, and write a transmission packet descriptor corresponding to one of the columns read in each column to the transmission ring buffer, wherein when the second processor core reads the end mark from a current column, it will switch to read the next column according to the polling order.

2. The network packet processing apparatus as described in claim 1, wherein the complex array of receive packet descriptors has the same number of receive packet descriptors.

3. The network packet processing apparatus as described in claim 2, wherein the plurality of storage blocks of the receiving ring buffer are continuously divided into a plurality of storage blocks, and each of the plurality of storage blocks is used to store a set of received packet descriptors.

4. The network packet processing apparatus as described in claim 1, wherein each column element includes a transmit packet descriptor address field and an end marker field, the transmit packet descriptor address field indicating the address of a transmit packet descriptor in a storage device, and the end marker field indicating whether the end marker is set.

5. The network packet processing apparatus as described in claim 1, wherein the at least one queue element corresponding to the last packet in the group of packets has the end marker set.

6. The network packet processing apparatus as described in claim 1, wherein the group of packets includes a first packet, the at least one transport packet descriptor includes a first transport packet descriptor corresponding only to the first packet, and the at least one queue element includes a first queue element corresponding to the first transport packet descriptor.

7. The network packet processing apparatus as described in claim 6, wherein each of the plurality of first processor cores further sets the number of packet aggregations based on the utilization rate of the corresponding column, and generates the first transmission packet descriptor when it is determined that the number of packet aggregations is not greater than 1.

8. The network packet processing apparatus as described in claim 1, wherein the group of packets includes a plurality of first packets, the at least one transmit packet descriptor includes a first transmit packet descriptor corresponding to the plurality of first packets, and the at least one queue element includes a first queue element corresponding to the first transmit packet descriptor.

9. The network packet processing apparatus as described in claim 8, wherein each of the plurality of first processor cores further sets the number of packet aggregations based on the utilization rate of the corresponding column, and generates the first transmission packet descriptor when it is determined that the number of packet aggregations is greater than 1.

10. The network packet processing apparatus as described in claim 9, wherein when it is determined that the number of packet aggregations is greater than 1, each of the plurality of first processor cores generates an aggregated packet, the aggregated packet aggregating the plurality of first packets, and a packet address field in the first transmit packet descriptor records the address of the aggregated packet in a storage device.

11. A network packet processing method, comprising: sequentially reading multiple arrays of receive packet descriptors from a receive ring buffer according to a polling order using a plurality of first processor cores, and performing parallel processing on the multiple arrays of packets based on the multiple arrays of receive packet descriptors, wherein the receive ring buffer includes a plurality of storage blocks, each storage block being used to temporarily store a receive packet descriptor of a packet before a packet is processed; and configuring a plurality of queues to the plurality of first processor cores respectively; Each of the plurality of first processor cores generates at least one transport packet descriptor and at least one queue element corresponding to the at least one transport packet descriptor for a set of packets, and adds the at least one queue element to a corresponding queue among the plurality of queues, wherein the at least one queue element is set with an end marker; and a second processor core reads the plurality of queues in turn according to the polling order, and writes the transport packet descriptor corresponding to one queue element read in each queue to a transport ring buffer, wherein the transport ring buffer includes a plurality of storage blocks, each storage block is used to temporarily store a transport packet descriptor of the packet after the packet is processed, and when the second processor core reads the end marker from a current queue, it will switch to read the next queue according to the polling order.

12. The network packet processing method as described in request item 11, wherein the complex array of receive packet descriptors has the same number of receive packet descriptors.

13. The network packet processing method as described in claim 12, further comprising: continuously dividing the plurality of storage blocks of the receive ring buffer into a plurality of storage blocks; and using each of the storage blocks in the plurality of storage blocks to store a set of receive packet descriptors.

14. The network packet processing method as described in claim 11, wherein each column element includes a transmit packet descriptor address field and an end marker field, the transmit packet descriptor address field indicating the address of a transmit packet descriptor in a storage device, and the end marker field indicating whether the end marker is set.

15. The network packet processing method as described in claim 11, wherein the at least one column element corresponding to the last packet in the group of packets will have the end marker set.

16. The network packet processing method as described in claim 11, wherein the group of packets includes a first packet, the at least one transport packet descriptor includes a first transport packet descriptor corresponding only to the first packet, and the at least one queue element includes a first queue element corresponding to the first transport packet descriptor.

17. The network packet processing method as described in claim 16, further comprising: setting a packet aggregation number based on the utilization rate of the corresponding queue through each of the plurality of first processor cores, and generating the first transmission packet descriptor when it is determined that the packet aggregation number is not greater than 1.

18. The network packet processing method as described in claim 11, wherein the group of packets includes a plurality of first packets, the at least one transmit packet descriptor includes a first transmit packet descriptor corresponding to the plurality of first packets, and the at least one queue element includes a first queue element corresponding to the first transmit packet descriptor.

19. The network packet processing method as described in claim 18 further includes: setting a packet aggregation number based on the utilization rate of the corresponding queue through each of the plurality of first processor cores, and generating the first transmission packet descriptor when it is determined that the packet aggregation number is greater than 1.

20. The network packet processing method as described in claim 19, further comprising: when it is determined that the number of packet aggregations is greater than 1, generating an aggregated packet through each of the plurality of first processor cores, wherein the aggregated packet aggregates the plurality of first packets, and a packet address field in the first transmission packet descriptor records the address of the aggregated packet in a storage device.

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