Electronic memory device , a method for fabricating an electronic memory device, and a method for revising an IC layout design

Abstract

An electronic memory device includes a non-memory-cell region and a memory-cell region. The non-memory-cell and the memory-cell region include circuitry formed in a substrate. The memory-cell region includes first, second, and third segments. The first segment is located closest to the non-memory-cell region in a top view. The second and third segments are each located farther from the non-memory-cell region than the first segment. A first interconnect structure is disposed over a first side of the substrate in a cross-sectional side view. The first interconnect structure includes first and second interconnect layers. The first and second interconnect layers are configured to route a memory signal to the first and second segments, respectively. A second interconnect structure is disposed over a second side of the substrate. The second interconnect structure includes a third interconnect layer configured to route the memory signal to the third segment.

Description

Technical Field

[0001] This disclosure generally relates to integrated circuit (IC) devices, and in particular to improving the performance of electronic memory devices by reducing the effects of load and / or device parasitic effects. Prior Technology

[0002] The electronics industry's demand for smaller, faster electronic devices that can support increasingly complex and sophisticated functions is constantly growing. Therefore, the semiconductor industry's ongoing trend is towards manufacturing low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been largely achieved by shrinking the size of semiconductor ICs (e.g., minimizing feature size), thereby improving production efficiency and reducing associated costs. However, shrinking size also increases the complexity of semiconductor manufacturing processes. Therefore, for semiconductor ICs and devices to continue to evolve, semiconductor manufacturing processes and technologies must also continuously advance.

[0003] As integrated circuit devices shrink, component parasitic effects (such as parasitic resistance and / or parasitic capacitance) can become a problem. For example, memory devices (e.g., static random access memory; SRAM) may use a metal line to carry memory device signals (e.g., bit line (BL) signals) for the memory cell array. However, if this metal line extends too far into the memory cell array, and the memory cell array is long, the parasitic effects associated with such metal lines can adversely affect the performance of the memory device, such as speed and / or power consumption. Therefore, while memory device designs are generally sufficient to meet their intended purpose, they are not entirely satisfactory in all aspects. Summary of the Invention

[0004] This disclosure provides an electronic memory device, including a non-memory cell region including a non-memory cell circuit at least partially formed in a substrate; a memory cell region including a memory cell circuit at least partially formed in the substrate, wherein the memory cell region includes at least a first segment, a second segment, and a third segment, wherein in a top view, the first segment is closest to the non-memory cell region, and in the top view, the second segment and the third segment are both further away from the non-memory cell region than the first segment; and a first interconnect structure, in a cross-sectional side view, disposed on a first side of the substrate, wherein the first interconnect structure includes... The substrate includes at least one first interconnect layer and a second interconnect layer, wherein the first interconnect layer is configured to route a specific type of memory signal from a non-memory cell region to a first segment of a memory cell region, and wherein the second interconnect layer is configured to route the specific type of memory signal from the non-memory cell region to a second segment of a memory cell region; and a second interconnect structure, in a cross-sectional side view, disposed on a second side of the substrate, wherein the second side is different from the first side, wherein the second interconnect structure includes at least one third interconnect layer, wherein the third interconnect layer is configured to route the specific type of memory signal from the non-memory cell region to a third segment of a memory cell region.

[0005] This disclosure provides a method for manufacturing an electronic memory device, including forming a non-memory cell circuit in a first region of a substrate and forming a memory cell circuit in a second region of the substrate, wherein in a planar top view, the first region and the second region are adjacent to each other in a first horizontal direction; in a cross-sectional side view, a first interconnect structure is formed on a front surface of the substrate, wherein the first interconnect structure includes at least a first interconnect layer and a second interconnect layer disposed on the first interconnect layer, wherein the first interconnect layer includes a component configured to route a predefined memory signal to the first region located in the second region. A first conductive element of a memory cell circuit in a segment, wherein a second interconnect layer includes a second conductive element configured to route a predefined memory signal to a memory cell circuit located in a second segment of a second region; and in a cross-sectional side view, a second interconnect structure is formed on a back side of a substrate, wherein the second interconnect structure includes at least one third interconnect layer, wherein the third interconnect layer includes a third conductive element configured to route a predefined memory signal to a memory cell circuit located in a third segment of a second region, wherein both the third segment and the second segment are further away from the first region than the first segment.

[0006] This disclosure provides a method for modifying an integrated circuit layout design, including accessing a first integrated circuit layout design of an electronic memory device, wherein the first integrated circuit layout design includes a non-memory cell region; a memory cell region disposed adjacent to the non-memory cell region in a first horizontal direction; and a first signal line extending from the non-memory cell region to the memory cell region in the first horizontal direction, wherein the first signal line extends through a large portion of the memory cell region in the first horizontal direction; and performing a modification operation to modify the first integrated circuit layout design into a second integrated circuit layout design, wherein the modification operation includes configuring at least a second signal line and a third signal line such that, in the first horizontal direction, the second signal line and the third signal line extend from the non-memory cell region to different portions of the memory cell region, wherein the second signal line and the third signal line are configured to carry a signal of the same type as the first signal line, and the second signal line and the third signal line are configured on a plurality of interconnect layers different from the first signal line. Simple Explanation of the Diagram

[0007] The following detailed description, in conjunction with the accompanying drawings, is recommended for the best understanding of all aspects of this disclosure. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity, the dimensions of these features may be arbitrarily increased or decreased. Figure 1A is a schematic perspective view of a semiconductor device. Figure 1B is a schematic top view of a semiconductor device. Figure 1C is a cross-sectional side view of a semiconductor device. Figure 2 is a circuit diagram of an SRAM cell. Figures 3 and 4 are top block diagrams of a memory device according to one of the various embodiments of the present disclosure. Figures 5A to 5C illustrate modifications made to the original integrated circuit layout design according to various embodiments of this disclosure to produce a modified integrated circuit layout design. Figure 6 illustrates a cross-sectional side view of a memory device according to one of the various embodiments of the present disclosure. Figures 7A to 7C illustrate modified integrated circuit layout designs according to various embodiments of this disclosure. Figures 8A and 8B illustrate front and rear plan views of a portion of an integrated circuit layout according to various embodiments of the present disclosure. Figure 9 is a block diagram of a semiconductor manufacturing system. Figure 10 is a flowchart illustrating a method of manufacturing an electronic memory device according to various embodiments of the present disclosure. Figure 11 is a flowchart illustrating a method for modifying an integrated circuit layout design according to various embodiments of the present disclosure. Implementation

[0008] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. To simplify this disclosure, specific examples of apparatus and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. For example, the phrase "above" or "on" a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby potentially preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various instances of the invention. Such repetition is for the purpose of brevity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0009] Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. Such repetition is for the sake of brevity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations discussed. Moreover, in this disclosure, a description of a feature being formed in, connected to, and / or coupled to another feature may include embodiments in which the features are in direct contact, or embodiments in which additional features are interposed between these features, such that these features may not be in direct contact. Furthermore, the use of spatial relative terms, such as "lower," "upper," "horizontal," "vertical," "above," "over," "below," "beneath," "up," "down," "top," "bottom," and their derivatives (e.g., "horizontally," "downwardly," "upwardly," etc.), is for the convenience of understanding the relationship between one feature and another in this disclosure. These spatial relative terms are intended to cover the different orientations of the apparatus containing these features. Furthermore, when using terms such as "about" or "approximate" to describe numbers or ranges of numbers, the term is intended to cover numbers within a reasonable range that includes the number being described, such as within + / - 10% of the described number, or other values ​​understood by one of ordinary skill in the art. For example, the term "about 5 nanometers" covers a size range of 4.5 nanometers to 5.5 nanometers.

[0010] This disclosure generally relates to integrated circuit (IC) devices, and more particularly to improving the performance of electronic memory devices by reducing the effects of load and / or device parasitic effects. In this regard, field-effect transistors (FETs) (such as three-dimensional FinFETs or gate-all-around (GAA) devices) can be used to implement electronic memory devices such as static random access memory (SRAM) devices. Electronic memory devices (e.g., SRAM devices) can utilize a metal line in an interconnect structure to route memory device signals (e.g., bit line (BL) signals) to the memory cell array of the electronic memory device. However, as integrated circuit manufacturing processes advance to more advanced technology nodes, the effects of device parasitic effects (e.g., parasitic resistance or parasitic capacitance) may become more pronounced. For example, the metal wires used to route signals from memory devices may become so thin that the parasitic resistance associated with such wires can begin to significantly degrade the performance of the electronic memory device. Furthermore, such wires may generate parasitic capacitances with other nearby conductive components, which can also degrade the performance of the electronic memory device. Moreover, these effects can be exacerbated when a single metal wire is used to route memory device signals that roughly cover the entire length of the memory cell array of the electronic memory device. In particular, the memory cell array at the furthest end of the metal wire may experience greater parasitic resistance and / or capacitance.

[0011] To address the aforementioned issues, this disclosure utilizes metal lines from multiple interconnect layers located above and below a substrate to perform signal routing operations to different regions of the electronic memory device. For example, a metal line in a metal-0 layer of a front interconnect structure can be used to route bit line (BL) signals to a memory cell array in a nearby region of the electronic memory device (e.g., near a location of a region of the electronic memory device relative to the origin of the metal line, such as a peripheral circuit region). A metal line in a metal-2 layer of the front interconnect structure can be used to route bit line (BL) signals to a memory cell array in an intermediate region of the electronic memory device. A metal line in a metal-0 layer of a back interconnect structure can be used to route bit line (BL) signals to a memory cell array in a distant region of the electronic memory device.

[0012] The metal lines of these different interconnect layers can also be configured to have different widths. For example, on the front side of the interconnect structure, the metal line from the second metal layer (metal-2) can be configured to be wider than the metal line from the zero metal layer (metal-0) because the metal line from the second metal layer (metal-2) should route the bit line (BL) signal to a more distant area, which could otherwise increase parasitic resistance. The thicker metal line of the second metal layer (metal-2) may help reduce parasitic resistance. In addition, the bit line (BL) signal to be routed to a more distant area may also bypass potential interference from nearby areas because it does not have to cross the metal line of the zero metal layer (metal-0). Similarly, the metal line from the zero metal layer (metal-0) on the back side of the interconnect structure can be configured to be wider than the metal line from the zero metal layer (metal-0) on the front side of the interconnect structure, and may even be thicker than the metal line from the second metal layer (metal-2) on the front side of the interconnect structure. This is because the metal line is intended to route the bit line (BL) signal to a more distant area. Using the second metal layer (metal-2) of the front interconnect structure and the zero metal layer (metal-0) of the back interconnect structure to route the bit line (BL) signal may also result in reduced parasitic capacitance, as these metal layers are further away from other conductive elements that can form parasitic capacitances with the metal line. The parasitic capacitance is inversely proportional to the distance between the two conductive elements.

[0013] The embodiments of the present disclosure will now be discussed in more detail with reference to Figures 1A to 1C, 2 to 4, 5A to 5C, 6, 7A to 7C, 8A to 8B, and 9 to 11. More specifically, Figures 1A to 1C will describe the basic structure of example transistors (e.g., fin field-effect transistors and gate-all-loop (GAA) devices) that can be used to implement electronic memory devices. Figure 2 will depict an example of an electronic memory device. Figures 3 and 4 are top block diagrams of a memory device according to one of the various embodiments of the present disclosure. Figures 5A to 5C are top views of an integrated circuit design layout according to various embodiments of the present disclosure. Figure 6 is a cross-sectional side view of an integrated circuit device according to various embodiments of the present disclosure. Figures 7A to 7C are top views of an integrated circuit design layout according to various embodiments of the present disclosure. Figures 8A to 8B are top views of a front and a back side of an SRAM cell according to various embodiments of the present disclosure. Figure 9 is a block diagram of a semiconductor manufacturing system according to various embodiments of the present disclosure. Figure 10 is a flowchart illustrating a method of manufacturing a memory device according to various embodiments of the present disclosure. Figure 11 is a flowchart illustrating a method of modifying an integrated circuit layout design according to various embodiments of the present disclosure.

[0014] Referring to Figures 1A and 1B, a three-dimensional perspective view and a top view of a portion of an integrated circuit device 90 are illustrated, respectively. The integrated circuit device 90 may be an intermediate device or a portion thereof manufactured during integrated circuit fabrication, and may include SRAM and / or other logic circuits, passive components (e.g., resistors, capacitors, and inductors), and active components (e.g., p-type FETs (PFETs), n-type FETs (NFETs), FinFETs, MOSFETs, CMOS transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, and / or other memory cells).

[0015] In the embodiments of Figures 1A and 1B, the integrated circuit device 90 includes a FinFET device. In this respect, a FinFET device is a fin-like field-effect transistor device. FinFET devices have recently become increasingly popular in the semiconductor industry due to several advantages compared to traditional MOSFET devices (e.g., "planar" transistor devices). These advantages may include better chip area efficiency, increased carrier mobility, and manufacturing processes compatible with planar device fabrication processes. Therefore, using FinFET elements to design part or all of an integrated circuit chip may be ideal.

[0016] As shown in Figure 1A, the integrated circuit device 90 includes a substrate 110. The substrate 110 may comprise a basic (single element) semiconductor, such as silicon, germanium, and / or other suitable materials; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; or an alloy semiconductor, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium arsenide phosphide (GaInAsP), and / or other suitable materials. The substrate 110 may be a single layer of material with a uniform composition. Alternatively, the substrate 110 may comprise multiple material layers with similar or different compositions suitable for manufacturing the integrated circuit device. In one example, the substrate 110 may be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer. In another example, substrate 110 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or combinations thereof. Various doped regions (e.g., source / drain regions) may be formed inside or on substrate 110. Depending on design requirements, the doped regions may be doped with n-type dopants (such as phosphorus or arsenic) and / or p-type dopants (such as boron). Doped regions may be formed directly on substrate 110, in a p-well structure, in an n-well structure, in a dual-well structure, or using a bump structure. Doped regions may be formed by implanting dopant atoms, in-situ doped epitaxial growth, and / or other suitable techniques.

[0017] A three-dimensional active region (also referred to as an active region) containing a nanostructure is formed on the substrate 110. The active region is an elongated fin structure protruding upward from the substrate 110. The protruding structure 120 may also be referred to as fin structure 120 below. Fin structure 120 can be manufactured using suitable processes, including lithography and etching processes. The lithography process may include forming a photoresist layer covering the substrate 110, exposing the photoresist as a pattern, performing a post-exposure baking process, and developing the photoresist to form a masking element (not shown) containing the photoresist. Then, the masking element is used to etch grooves into the substrate 110, leaving fin structure 120 on the substrate 110. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In some embodiments, the fin structure 120 may be formed through a double-patterning or multi-patterning process. Generally, double-patterning or multi-patterning processes combine lithography with a self-aligning process, allowing the created patterns to have smaller pitches, for example, smaller than those achievable using a single, direct lithography process. For example, a thin layer is formed over a substrate and patterned using a lithography process. Spacers are formed along the sides of the patterned thin layer using a self-aligning process. The thin layer is then removed, and the remaining spacers (or mandrels) can then be used to pattern the fin structure 120.

[0018] The integrated circuit device 90 also includes source / drain features 122 formed on the fin structure 120. The source / drain features 122 may include an epitaxially grown epitaxial layer on the fin structure 120. The integrated circuit device 90 also includes an isolation structure 130 formed on the substrate 110. The isolation structure 130 electrically isolates the various elements of the integrated circuit device 90. The isolation structure 130 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials. In some embodiments, the isolation structure 130 may include shallow trench isolation (STI) features. In one embodiment, the isolation structure 130 is formed during the formation of the fin structure 120 by etching trenches in the substrate 110. The trench can then be filled with the aforementioned isolation material, followed by a chemical mechanical planarization (CMP) process. Other isolation structures, such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures, can also be used to implement isolation structure 130. Alternatively, isolation structure 130 may comprise a multilayer structure, for example, having one or more thermal oxide liner layers.

[0019] The integrated circuit device 90 also includes a gate structure formed on the fin structure 120 and bonded to three sides of the fin structure in the channel region of each fin structure 120. The gate structure 140 may be a dummy gate structure (e.g., comprising an oxide gate dielectric and a polysilicon gate electrode) or an HKMG structure comprising a high-k gate dielectric and a metal gate electrode, wherein the HKMG structure is formed by replacing the dummy gate structure. Although not shown, the gate structure 140 may include additional material layers, such as an interfacial layer (IL), a capping layer, other suitable layers, or combinations thereof on the fin structure 120.

[0020] Referring to Figure 1B, multiple fin structures 120 are arranged along the X-axis length direction, and multiple gate structures 140 are arranged along the Y-axis length direction, that is, typically perpendicular to the fin structures 120. In many embodiments, the integrated circuit device 90 includes additional features, such as gate spacers disposed along the sidewalls of the gate structures 140, a hard mask layer disposed on the gate structures 140, and many other features.

[0021] It should be understood that the embodiments of this disclosure discussed below may be applicable to multichannel devices, such as gate-full-loop (GAA) devices. Figure 1C shows a schematic cross-sectional side view of a portion of an integrated circuit device 5 manufactured according to an embodiment of this disclosure, wherein the integrated circuit device 5 is a gate-full-loop (GAA) device, hereinafter referred to as gate-full-loop (GAA) device 5. It is understood that in some embodiments, the gate-full-loop (GAA) device 5 may be an NFET, and in other embodiments it may be a PFET.

[0022] Referring to Figure 1C, a cross-sectional view of the gate-full-loop (GAA) device 5 is taken along the XZ plane, where the X direction (same as the X direction in Figure 1A) is horizontal and the Z direction (same as the Z direction in Figure 1A) is vertical. The gate-full-loop (GAA) device 5 includes a fin structure 10, which may be similar to the fin structure 120 discussed above. In some embodiments, the fin structure 10 includes silicon. The gate-full-loop (GAA) device 5 includes a source / drain feature 20, which may be similar to the source / drain feature 122 discussed above. In an embodiment where the gate-full-loop (GAA) device 5 is an NFET, the source / drain feature 20 includes silicon phosphorus (SiP). In an embodiment where the gate-full-loop (GAA) device 5 is a PFET, the source / drain feature 20 includes silicon germanium (SiGe).

[0023] The gate-all-loop (GAA) device 5 includes multiple channels, such as channels 30 to 33, as shown in FIG1C. Each of channels 30 to 33 comprises a semiconductor material, such as silicon or a silicon compound. Channels 30 to 33 are nanostructures (e.g., having dimensions in the range of several nanometers), and each channel may also have an elongated shape and extend in the X direction. In some embodiments, channels 30 to 33 may each have a nano-wire shape, a nano-sheet shape, a nano-tube shape, etc. The cross-sectional profile of the nanowire, nanosheet, or nanotube may be circular / annular, square, rectangular, hexagonal, elliptical, or a combination thereof.

[0024] In some embodiments, the lengths of channels 30 to 33 (e.g., measured in the X direction) may differ from one another. For example, the length of channel 30 may be less than the length of channel 31, the length of channel 31 may be less than the length of channel 32, and the length of channel 32 may be less than the length of channel 33. In some embodiments, each of channels 30 to 33 may not have a uniform width.

[0025] In some embodiments, the width of each of channels 30 to 33 (e.g., measured in the Y direction of FIG1A) is between about 15 nm and about 150 nm. Multiple interface layers 40 may also be formed on the upper and lower surfaces of channels 30 to 33.

[0026] The gate-all-around (GAA) device 5 further includes a gate structure disposed above and between channels 30 and 33. The gate structure may include a gate dielectric layer 50. In some embodiments, the gate dielectric layer 50 includes a high-dielectric-constant gate dielectric layer. The gate structure also includes one or more work function metal layers 60. In an embodiment where the gate-all-around (GAA) device 5 is an NFET, the one or more work function metal layers 60 include N-type work function metal layers, such as titanium aluminum carbon (TiAlC). In an embodiment where the gate-all-around (GAA) device 5 is a PFET, the one or more work function metal layers 60 include P-type work function metal layers, such as titanium nitride (TiN).

[0027] The gate structure also includes filler metal 80. In portions of the gate structure formed on channels 30 to 33, filler metal 80 is formed on one or more work function metal layers 60. The one or more work function metal layers 60 are U-shaped and surround the filler metal 80, and the gate dielectric layer 50 is also U-shaped and surrounds the one or more work function metal layers 60. In portions of the gate structure formed between channels 30 and 33, filler metal 80 is surrounded circumferentially by one or more work function metal layers 60 (in a cross-sectional view), and then surrounded circumferentially by the gate dielectric layer 50. It is understood that the gate structure may also include a glue layer formed between the one or more work function metal layers 60 and the filler metal 80 to increase adhesion. However, for simplicity, such a glue layer is not specifically described herein.

[0028] The gate all-around (GAA) device 5 further includes a gate spacer 91 and an internal spacer 95 disposed on the sidewall of the gate dielectric layer 50. The internal spacer 95 is also disposed between channels 30 and 33. The gate spacer and the internal spacer 95 may contain a dielectric material, such as a low-k material such as silicon oxycarbonitrile (SiOCN), silicon oxynitride (SiON), silicon nitride (SiN), or silicon oxycarbonitrile (SiOC).

[0029] The gate-all-around (GAA) device 5 also includes a source / drain contact 96 formed on the source / drain feature 20. The source / drain contact 96 may contain a conductive material such as cobalt, copper, aluminum, tungsten, or a combination thereof. The source / drain contact 96 is surrounded by a barrier layer, such as barrier layer 97A and barrier layer 97B, which helps prevent or reduce the diffusion of material from the source / drain contact 96 and into the source / drain contact 96. In some embodiments, barrier layer 97A comprises titanium nitride (TiN), and barrier layer 97B comprises silicon nitride (SiN). A silicon layer 98 may also be formed between the source / drain feature 20 and the source / drain contact 96 to reduce source / drain contact resistance. The silicate layer 98 may comprise a metallic silicate material, such as cobalt silicate in some embodiments.

[0030] The gate all-loop (GAA) device 5 also includes an interlayer dielectric (ILD) 99. The interlayer dielectric 99 provides electrical isolation between the various elements of the gate all-loop (GAA) device 5, for example, between the gate structure and the source / drain contact 96.

[0031] Full-gate-all-around (GAA) devices may also offer advantages such as better wafer area efficiency and increased carrier mobility. Therefore, advanced integrated circuit wafers can also be implemented using GAA devices. However, it is understood that, unless otherwise required, this disclosure is not limited to any particular number of devices or device regions, nor to any particular device configuration. For example, although FinFET devices or GAA devices have been described as potential transistors that can be used to implement integrated circuit wafers or portions thereof, the concepts of this disclosure, as described in more detail below, may also apply to integrated circuit wafers implemented using planar field-effect transistor devices.

[0032] It is understood that, unless otherwise required, this disclosure is not limited to any particular number of devices or device regions, nor to any particular device configuration. For example, although the integrated circuit device 90 is illustrated in Figures 1A and 1B as a three-dimensional FinFET device and in Figure 1C as a gate all-loop (GAA) device, the concepts of this disclosure may also be applied to planar field-effect transistor devices.

[0033] Figure 2 illustrates an example type of electronic memory device in which planar transistors, FinFETs, or gate-all-loop (GAA) transistors can be used. In a specific example of Figure 2, a circuit diagram of an example SRAM device is shown, for example, as a single-port SRAM cell (e.g., a 1-bit SRAM cell) 200. The single-port SRAM cell 200 includes pull-up transistors PU1 and PU2; pull-down transistors PD1 and PD2; and pass-gate transistors PG1 and PG2. As shown in the circuit diagram, pull-up transistors PU1 and PU2 are p-type transistors, and pass-gate transistors PG1 and PG2, and pull-down transistors PD1 and PD2 are n-type transistors. According to various embodiments disclosed herein, the transmit gate transistor PG1, transmit gate transistor PG2, pull-down transistor PD1, and pull-down transistor PD2 are implemented with thinner spacers than the pull-up transistors PU1 and PU2. Since the single-port SRAM cell 200 includes six transistors in the illustrated embodiment, it can also be referred to as a 6T SRAM cell. In any case, FinFET or gate all-loop (GAA) transistors can be used to implement the transmit gate transistor PG1, transmit gate transistor PG2, pull-down transistor PD1, pull-down transistor PD2, pull-up transistor PU1, and / or pull-up transistor PU2.

[0034] The drain of pull-up transistor PU1 is coupled to the drain of pull-down transistor PD1, and the drain of pull-up transistor PU2 is coupled to the drain of pull-down transistor PD2. Pull-up transistors PU1 and PD1 are cross-coupled with pull-up transistors PU2 and PD2 to form a first data latch. The gate of pull-up transistor PU2 is coupled to the gate of pull-down transistor PD2, and is also coupled to the drains of pull-up transistors PU1 and PD1 to form a first storage node SN1. The gate of pull-up transistor PU1 is coupled to the gate of pull-down transistor PD1, and is also coupled to the drains of pull-up transistors PU2 and PD2 to form a complementary first storage node SNB1. The source of pull-up transistor PU1 and the source of pull-up transistor PU2 are coupled to the power supply voltage Vcc (also known as Vdd), and the source of pull-down transistor PD1 and the source of pull-down transistor PD2 are coupled to voltage Vss, which may be electrically grounded in some embodiments.

[0035] The first storage node SN1 of the first data latch is coupled to a signal line called a bit line (BL) via a transmit gate transistor PG1, and the complementary first storage node SNB1 is coupled to a complementary signal line called a bit line bar (BLB) via a transmit gate transistor PG2. The first storage node SN1 and the complementary first storage node SNB1 are complementary nodes and are typically at opposite logic levels (logic high or logic low). The gates of transmit gate transistors PG1 and PG2 are coupled to a word line (WL) signal, which can be used to select a specific row of memory cells. SRAM elements (such as single-port SRAM cells 200) can be implemented using planar transistor devices, FinFET devices, and / or gate all-loop (GAA) devices.

[0036] Figure 3 is a block diagram of a portion of an electronic memory device 300 in which a single-port SRAM cell 200 may be configured. For example, the electronic memory device 300 may include an SRAM cell array region 310 for implementing multiple SRAM devices (e.g., the single-port SRAM cell 200 of Figure 1). As an SRAM cell array, the SRAM devices in the SRAM cell array region may comprise substantially identical SRAM cell blocks (e.g., an array) as repeating circuit units. In some embodiments, the SRAM devices in the SRAM cell array region 310 are implemented using FinFETs and / or gate-all-loop (GAA) transistors discussed above with reference to Figures 1A to 1C. However, it is understood that other types of transistors (e.g., planar transistors) may also be used to configure SRAM devices in the SRAM cell array region 310.

[0037] The electronic memory device 300 may also include various non-memory cell circuitry regions surrounding the SRAM cell array region 310. Therefore, these non-memory cell circuitry regions may also be referred to as peripheral regions or peripheral circuitry. In the example shown in FIG3, the peripheral region of the electronic memory device 300 includes an input / output (I / O) region 320, a word line driver (WL DRV) region 330, and a control circuitry (CNT) region 340. In some embodiments, the I / O region 320 includes circuitry for processing the input / output of the SRAM devices in the SRAM cell array region 310, the word line driver region 330 includes circuitry for driving the word lines (WL) of the SRAM devices in the SRAM cell array region 310, and the control circuitry region 340 includes circuitry for controlling the electrical operation of the SRAM devices in the SRAM cell array region 310. As described above, the input / output region 320, the word line driver region 330, and the control circuitry region 340 may be collectively referred to as the peripheral region or individually.

[0038] Although not specifically described herein for simplicity, it is understood that the electronic memory device 300 may also include other types of non-memory cell regions as in other embodiments, such as standard cell regions containing logic circuits for performing Boolean logic operations, electronic fuse regions containing microscopic electronic fuses configured to dynamically reprogram the chip in real time, or a general-purpose input / output (GPIO) region configured to handle input / output between the electronic memory device 300 and devices external to the electronic memory device 300. It should be understood that the transistors in the input / output region 320, the word line driver region 330, the control circuit region 340, and / or other types of non-memory cell regions may also be implemented using the aforementioned FinFET and / or gate-all-loop (GAA) transistors.

[0039] The block diagram in Figure 3 is a planar top view horizontally defined by an X-axis and a Y-axis (which may be the same as or different from the X and Y directions discussed above; see Figures 1A to 1C). The input / output area 320 is directly disposed next to the SRAM cell array area 310 in the X direction, the word line driver area 330 is directly disposed next to the SRAM cell array area 310 in the Y direction, and the control circuit area 340 is directly disposed next to the word line driver area 330 in the X direction and directly disposed next to the input / output area 320 in the Y direction.

[0040] The block diagram in Figure 3 also includes a memory signal line 380 configured to carry a specific type of memory signal. For example, in the illustrated embodiment, the memory signal line 380 may be configured to carry a bit line (BL) signal, and therefore the memory signal line 380 may also be referred to hereinafter as a BL signal line 380. However, it is understood that the memory signal line 380 may carry other types of memory device signals in other embodiments, such as inverted bit line (BLB) or other suitable signals.

[0041] The BL signal line 380 may include a metal line (e.g., a conductive element) formed in a multilayer interconnect structure, wherein the metal line is configured to carry or route electrical signals, such as bit line signals, from a non-memory cell region (e.g., input / output region 320) to a memory cell region (e.g., SRAM cell array region 310). However, as the size of the SRAM cell array region 310 increases, the length of the BL signal line 380 may also increase, which may lead to problems related to load and / or parasitic effects. For example, if the size of an SRAM array is greater than or equal to 128 bits, the correspondingly long BL signal line 380 may be significantly affected by load and / or parasitic effects. Problems caused by the parasitic resistance of the BL signal line 380 may worsen with an increase in the length of the BL signal line 380 and / or a decrease in the width of the BL signal line 380. Parasitic capacitance may be formed by coupling the BL signal line 380 to other nearby conductive components (e.g., two conductive plates with dielectric material between them), but it may also be aggravated as the length of the BL signal line 380 increases and / or the distance between the BL signal line 380 and other nearby conductive components decreases. Due to load and / or parasitic effects, the device performance of the electronic memory device 300 may be degraded. For example, the electronic memory device 300 may operate at a slower speed, dissipate more power, generate more heat, and / or have a shorter lifespan.

[0042] To address the aforementioned issues, this disclosure modifies the integrated circuit layout design of the electronic memory device 300 by implementing multiple additional signal lines to facilitate the carrying / routing of bit line (BL) signals. For example, Figure 4 shows a block diagram of a portion of the electronic memory device 300 according to the modified integrated circuit layout design. For consistency and clarity, similar components appearing in Figures 3 and 4 are labeled with the same reference numerals.

[0043] Referring to Figure 4, the electronic memory device 300 still includes an SRAM cell array region 310, but the SRAM cell array region 310 is divided into multiple segments. For example, in the embodiment shown in Figure 4, the SRAM cell array region 310 is divided into segments 310A, 310B, and 310C. Segment 310A is located closest to the input / output region 320, segment 310B is located further away from the input / output region 320 than segment 310A, and segment 310C is located furthest from the input / output region 320 (e.g., further away from the input / output region 320 than both segments 310A and 310B). Each of segments 310A through 310C may still contain an SRAM cell array of the same type as the SRAM cell array region 310 of Figure 3.

[0044] Corresponding segments of the BL signal line 380 are configured in each of segments 310A to 310C. For example, unlike a relatively long BL signal line 380 (as shown in Figure 3), segment 380A of the BL signal line is configured in segment 310A of the SRAM cell array region 310, segment 380B of the BL signal line is configured in segment 310B of the SRAM cell array region 310, and segment 380C of the BL signal line is configured in segment 310C of the SRAM cell array region 310, wherein the length of each of segments 380A to 380C of the BL signal line is shorter in the X direction than the length of the BL signal line 380 in Figure 3. The smaller length of each of segments 380A to 380C of the BL signal line reduces load and / or parasitic resistance and capacitance, which in turn helps to improve device performance, such as speed and / or power consumption.

[0045] SRAM cell array region 310 is further configured with additional memory signal lines to assist in routing specific memory signals (e.g., the BL signal herein) to different segments of SRAM cell array region 310. In the embodiment shown herein, since the specific memory signal carried by memory signal line 380 is a bit line (BL) signal, these additional memory signal lines are also configured to carry bit line (BL) signals. For example, a BL signal line 400 is configured to assist in routing the bit line (BL) signal directly from input / output region 320 to segment 310B of SRAM cell array region 310, while bypassing segment 380A of the BL signal line in segment 310A. Similarly, BL signal line 410 is configured to facilitate direct routing of the BL signal from input / output region 320 to segment 310C of SRAM cell array region 310, while bypassing segment 380A of the BL signal line in segment 310A and segment 380B of the BL signal line in segment 310B. This is achieved by configuring BL signal line 400 and BL signal line 410 in a different interconnect layer than segments 380A to 380C of the BL signal line. For example, segments 380A to 380C of the BL signal line can be disposed in a metal-0 interconnect layer of a front interconnect structure, while the BL signal line 400 can be disposed in a metal-2 interconnect layer of the front interconnect structure (i.e., two layers above the metal-0 interconnect layer), and the BL signal line 410 can be disposed in a back-side metal-0 interconnect layer of a back interconnect structure, wherein the front interconnect structure and the back interconnect structure are located on opposite sides of the substrate forming the circuit of the electronic memory device 300.

[0046] As described above, BL signal lines 400 and 410 are located in different interconnect layers from segments 380A to 380C of the BL signal lines. This allows bit line (BL) signals to be directly transmitted to segments 310B and 310C of the SRAM cell array region 310, while bypassing potential interference from circuitry and / or segments 380A-380B of the BL signal lines. For example, because BL signal lines 400 or 410 are configured in an interconnect layer further away from other conductive elements, the distance between other conductive elements and BL signal lines 400 or 410 is increased, potentially reducing parasitic capacitance associated with BL signal lines 400 and 410. Furthermore, BL signal lines 400 and 410 are configured to have larger dimensions not only in the X direction than segments 380A to 380C of the BL signal lines, but also in the Y direction. In other words, both BL signal lines 400 and 410 are wider than sections 380A to 380C of the BL signal lines. The wider BL signal lines 400 and 410 compared to sections 380A to 380C result in lower parasitic resistance for both BL signal lines. Therefore, device performance may be further improved.

[0047] Referring again to Figure 4, the SRAM cell array region 310 includes multiple middle strap regions disposed between segments 310A and 310C. For example, a middle strap region 390 is located between segments 310A and 310B of the SRAM cell array region 310, and a middle strap region 391 is located between segments 310B and 310C of the SRAM cell array region 310. Middle strap regions 390 and 391 are configured to facilitate electrical routing. For example, a BL signal line 400 may extend (in the X direction) from the input / output region 320 to the middle strap region 390. The intermediate strip region 390 may include one or more conductive vias and / or metal lines configured to be electrically coupled to the BL signal line 400 and to segment 380B of the BL signal line in segment 310B of the SRAM cell array region. Therefore, the BL signal can be routed from the input / output region 320, via the BL signal line 400 and the conductive vias and / or metal lines of the intermediate strip region 390 (while bypassing segment 310A of the SRAM cell array region 310), to the SRAM cell array circuitry in segment 310B of the SRAM cell array region. Similarly, the intermediate strip region 391 may include one or more conductive vias and / or metal lines configured to be electrically coupled to the BL signal line 410 and to segment 380C of the BL signal line in segment 310C of the SRAM cell array region. Therefore, the BL signal can be routed from the input / output region 320, via the BL signal line 410 and the conductive vias and / or metal lines of the intermediate strip region 391 (while bypassing sections 310A to 310B of the SRAM cell array region 310), to the SRAM cell array circuit in section 310C of the SRAM cell array region.

[0048] Figures 5A to 5C illustrate a modification process of one of the integrated circuit layout designs according to an embodiment of the present disclosure. More specifically, Figure 5A illustrates an original integrated circuit layout design 500, and Figures 5B and 5C illustrate modified integrated circuit layout designs 510A and 510B based on the original integrated circuit layout design 500. The original integrated circuit layout design 500 and the modified integrated circuit layout designs 510A through 510B are all represented in plan view, where the plan view corresponds to a horizontal plane defined by the X and Y directions. In some embodiments, the original integrated circuit layout design 500 may be in the format of a Graphic Data System (GDS) file, which includes solder masks, geometry, layers, component labels, and an overall layout of a circuit. In some embodiments, the Graphic Data System (GDS) file may have a binary format. In some embodiments, the original integrated circuit layout design 500 may be generated by an integrated circuit design company, which may then send the original integrated circuit layout design to an integrated circuit manufacturer (e.g., an integrated circuit foundry). The integrated circuit manufacturer may access and modify the original integrated circuit layout design 500 to generate a modified integrated circuit layout design, in which case the modified integrated circuit layout design comprises modified integrated circuit layout design 510A and modified integrated circuit layout design 510B.

[0049] Referring to FIG. 5A, the original integrated circuit layout design 500 includes the integrated circuit layout design of the SRAM cell array region 310 of FIG. 3. For consistency and clarity, similar elements appearing in FIG. 3-4 and FIG. 5A-5C are labeled with the same reference numerals. The original integrated circuit layout design 500 includes a plurality of memory signal lines 380, each configured to carry a specific type of memory signal. For example, a memory signal line 380 may be configured to carry a bit line (BL) signal, and a bit line (BL) signal may also be referred to as BL signal line 380. The bit line (BL) signal may be generated by a non-memory cell circuit, such as by circuitry in the peripheral region of the SRAM device (e.g., write driver circuitry and sense amplifier). As described above with reference to FIG. 3, the BL signal line 380 may extend in the X direction through a large portion of the SRAM cell array region 310. For example, the BL signal line 380 may have a dimension 520 measured in the X direction, and the entire SRAM cell array region 310 may have a dimension 530 measured in the X direction. In some embodiments, the dimension 520 is between about 20 micrometers and about 50 micrometers, and the dimension 530 is between about 21 micrometers and about 51 micrometers.

[0050] The relatively long length of the BL signal line 380 means that it can provide BL signals to almost all SRAM cells in any given column and / or row of the array. Unfortunately, such a long BL signal line 380 can also lead to load problems and / or amplified parasitic effects, as described above with reference to Figure 3. Therefore, to mitigate these concerns, this disclosure modifies the original integrated circuit layout design 500 to produce modified integrated circuit layout design 510A (a front plan top view) and modified integrated circuit layout design 510B (a rear plan top view), wherein the original BL signal line 380 can be broken down into multiple different BL signal line segments 380A, 380B, and 380C, and additional BL signal lines 400 and 410 are configured to assist in routing the bit line (BL) signals. Please note that although modified integrated circuit layout designs 510A and 510B have been drawn separately to emphasize BL signal line 400 and BL signal line 410 respectively, the modified integrated circuit layout designs 510A and 510B are still part of the same integrated circuit layout design. The SRAM cell array region 310 in the original integrated circuit layout design 500 has also been modified into segments 310A, 310B, and 310C of the SRAM cell array region in the modified integrated circuit layout designs 510A to 510B. The modified integrated circuit layout designs 510A to 510B also have intermediate strip regions 390 and 391 located between segments 310A, 310B, and 310C of the SRAM cell array region.

[0051] According to the modified integrated circuit layout designs 510A to 510B, each of the BL signal line segments 380A to 380C has a dimension 540 measured along the X direction, which is smaller than the dimension 520 of the BL signal line 380 in the original integrated circuit layout design 500. Since the length of each BL signal line segment 380A to 380C is smaller, the modified integrated circuit layout designs 510A to 510B inevitably result in reduced load and / or parasitic effects.

[0052] Furthermore, the implementation of BL signal lines 400 and 410 can reduce the load and / or parasitic effects associated with the original integrated circuit layout design 500. More specifically, in some embodiments, the BL signal line 380 in the original integrated circuit layout design 500 is disposed in the bottom interconnect layer (e.g., the 0th metal layer) of the front interconnect structure, as are segments 380A to 380C of the BL signal lines in the modified integrated circuit layout designs 510A to 510C. The above embodiments are illustrated in Figure 6, which is a cross-sectional side view of a portion of the electronic memory device 300, for example, a cross-sectional side view at the SRAM cell array region 310. The cross-sectional side view can be taken along a vertical plane defined by the vertical Z direction and the horizontal X direction. The cross-sectional side view includes a device region 600, in which circuitry (e.g., an SRAM cell array or peripheral circuitry of an SRAM device) is formed by transistors such as FinFETs or gate-all-loop (GAA) devices discussed above. The cross-sectional side view also includes an interconnect structure 610 disposed on the front side of one of the device regions 600, and an interconnect structure 620 disposed on the back side of one of the device regions 600, wherein the back side and the front side are located on opposite sides.

[0053] Interconnect structures 610 and 620 can each be a multi-layer interconnect (MLI) structure, comprising multiple interconnect layers (e.g., a metal-0, metal-1, metal-2, metal-3, etc.) and multiple conductive vias interconnecting the interconnect layers together. The interconnect layers may include multiple metal lines, which can be implemented as elongated conductive strips. The metal lines are configured to route electrical signals, and metal lines from different interconnect layers are interconnected with each other through conductive vias. In various embodiments, the metal lines and / or conductive vias may comprise copper, aluminum, tungsten, cobalt, ruthenium, or combinations thereof. The metal lines and conductive vias are embedded in a dielectric material that provides appropriate electrical isolation for the metal lines and / or conductive vias. In various embodiments, the dielectric material may comprise silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, or a low dielectric constant dielectric material having a dielectric constant lower than that of silicon oxide (e.g., less than about 3.9).

[0054] Please note that although Figure 6 shows four interconnect layers (e.g., metal-0 through metal-3) for the front interconnect structure 610 and one interconnect layer (e.g., back-side metal-0) for the back interconnect structure 620, this configuration is not intended to be limiting unless otherwise required. In other words, the front interconnect structure 610 may have more or fewer than the four interconnect layers shown, and the back interconnect structure 620 may also have more or fewer than the one shown. One or more of these additional interconnect layers (e.g., interconnect layers other than the metal-0 layer of the front interconnect structure 610) may also be used to implement memory signal lines, such as BL signal line 400 and / or BL signal line 410 in other embodiments.

[0055] As described above, referring to Figures 5B to 5C, the 0th metal layer (metal-0) of the interconnect structure 610 of Figure 6 (e.g., one of the metal lines in this interconnect layer) can be used to implement segments 380A to 380C of the BL signal lines of the modified integrated circuit layout designs 510A to 510B. In contrast, the BL signal line 400 of the modified integrated circuit layout design 510A is configured in an upper interconnect layer of the interconnect structure 610, such as in the second metal layer (metal-2) interconnect layer. Note that the first metal layer (metal-1) interconnect layer may not be suitable for implementing the BL signal line 400 because the metal lines in the first metal layer (metal-1) interconnect layer may extend in a vertical direction, as in the metal lines in the 0th metal layer (metal-0) or the second metal layer (metal-2) interconnect layer, thus making it impossible to transmit the bit line (BL) signal to the SRAM cell array in the X direction. Therefore, the BL signal line 400 is disposed two layers above sections 380A to 380C of the BL signal line. At the same time, the BL signal line 410 of the modified integrated circuit layout design 510B is disposed in an interconnect layer of the interconnect structure 620, for example in the back side 0th metal layer (B-metal-0).

[0056] One reason for configuring BL signal lines 400 and 410 in a different interconnect layer than sections 380A to 380C of the BL signal lines is to optimize device performance. For example, BL signal line 400 routes the BL signal directly from the peripheral circuitry of the electronic memory device 300 to section 310B of the SRAM cell array region 310, allowing the BL signal to bypass section 310A of the SRAM cell array region 310. In other words, the BL signal does not have to pass through section 380A of the BL signal line located in section 310A of the SRAM cell array region (which may have some degree of load and / or parasitic effects). That is, the BL signal can hop on the "highway" provided by BL signal line 400 and propagate to section 310B of the SRAM cell array region with lower load and / or parasitic effects. The BL signal line 400 described herein can be analogous to a "highway" in function, not only because its dimension 550 in the X direction is longer than each of the segments 380A to 380C of the BL signal line, but also because its width measured in the Y direction is wider. For example, in the plan view of Figures 5B to 5C, each of the segments 380A to 380C of the BL signal line may have a width 560 (i.e., the dimension measured in the Y direction), while in the plan view of Figures 5B to 5C, the BL signal line 400 has a width 570 (also the dimension measured in the Y direction). According to various embodiments disclosed herein, the width 570 is substantially much larger than the width 560. The larger width 570 essentially results in a reduction in parasitic resistance (because resistance is inversely proportional to width) and better uniformity (because the percentage of variation in width 570 due to process defects is smaller than the total width). In some implementations, the width 570 is between approximately 30 nanometers (nm) and approximately 60 nm, and the width 560 is between approximately 20 nm and approximately 60 nm. This range is specifically configured to ensure that the BL signal line 400 can provide reduced parasitic effects while maintaining sufficient routing flexibility.

[0057] In addition to using a wider width 570 to reduce parasitic resistance, the configuration of the BL signal lines 400 described herein also improves device performance. This is a natural consequence of the larger spacing between adjacent pairs of BL signal lines 400. For example, a distance 565 separates BL signal line segment 380A from the nearest other BL signal line segment 380A (e.g., closest in the Y direction), while BL signal line 400 is spaced 575 from the nearest other BL signal line 400 in the Y direction. According to various embodiments disclosed herein, the distance 575 is substantially much larger than the distance 565. A larger distance 575 can essentially result in a reduction in parasitic capacitance (since capacitance is inversely proportional to the distance between the two conductive plates). In some embodiments, the distance 575 is between about 200 nm and about 500 nm, and the distance 565 is between about 200 nm and about 500 nm. This range is also specifically configured to ensure that the BL signal lines 400 provide reduced parasitic effects while maintaining sufficient routing flexibility.

[0058] Another reason why the BL signal line 400 helps reduce parasitic capacitance is essentially due to its location within the second metal-2 interconnect layer. In other words, the BL signal line 400 is further away from the various microelectronic components of the SRAM cell array than segment 380A of the BL signal line (located in the zero metal-0 layer). Therefore, any parasitic capacitance coupled between the BL signal line 400 and other microelectronic components is substantially less significant, as parasitic capacitance is inversely proportional to the distance between the two conductive plates. Furthermore, due to the greater distance, the bit line (BL) signal propagating on the BL signal line 400 is less susceptible to noise or other interference sources from the underlying SRAM cell array circuitry, which may further improve device performance.

[0059] Referring again to Figures 5B to 5C and Figure 6, the BL signal line 410 functions similarly to the BL signal line 400, except that the BL signal line 410 is configured to carry the BL signal to segment 310C of the SRAM cell array region, rather than segments 310A / 310B of the SRAM cell array region. In other words, the BL signal can hop on a "highway" provided by the BL signal line 410 and propagate to segment 310C of the SRAM cell array region with less load and / or parasitic effects. However, the BL signal line 400 is disposed in the second metal-2 interconnect layer of the front interconnect structure 610, while the BL signal line 410 is disposed in the back-side 0 metal-0 interconnect layer of the back interconnect structure 620.

[0060] As shown in the top view of Figure 5C, the BL signal line 410 here has a dimension 580 in the X direction that is longer than each of the segments 380A to 380C of the BL signal line, and the BL signal line 410 has a width 590 in the Y direction that is wider than the width 560 of each of the segments 380A to 380C of the BL signal line. Similar to the discussion above regarding the BL signal line 400, the longer dimension 580 essentially allows the BL signal line 410 to span and bypass segments 310A and 310B of the SRAM cell array region, while the wider width 590 essentially allows the BL signal line 410 to have reduced parasitic resistance. Furthermore, since the BL signal line 410 is configured to transmit bit line (BL) signals to the farthest region (e.g., segment 310C is farther from the surrounding region than segment 310B), the BL signal line 410 can be implemented with a wider width than the BL signal line 400. In other words, in some embodiments, the width 590 may be greater than the width 570. In some embodiments, the width 590 is between about 30 nm and about 60 nm, and the width 570 is between about 20 nm and about 60 nm. Furthermore, the distance 595 between adjacent pairs of BL signal lines 410 is also greater than the distance 565 between segments 380A of adjacent pairs of BL signal lines, which also helps to reduce parasitic capacitance associated with the BL signal line 410, for reasons similar to those discussed above with respect to the BL signal line 400. In some embodiments, the distance 595 is between about 200 nm and about 500 nm, and the distance 565 is between about 200 nm and about 500 nm. This range is specifically configured to ensure that the BL signal line 410 can provide reduced parasitic effects while maintaining sufficient routing flexibility.

[0061] As shown in Figures 5B to 5C, BL signal line 400 may terminate in intermediate strip region 390, and BL signal line 410 may terminate in intermediate strip region 391. In some embodiments, intermediate strip region 390 may include one or more conductive vias or metal lines to facilitate the establishment of a connection between BL signal line 400 and BL signal line segment 380B in SRAM cell array segment 310B. For example, intermediate strip region 390 may include a conductive via similar to a conductive via 630 in Figure 6 (establishing an electrical connection between metal lines in the second metal layer (metal-2) and the first metal layer (metal-1), a metal line similar to a metal line 640 in the first metal layer (metal-1), and a conductive via similar to a conductive via 650 (establishing an electrical connection between metal lines in the first metal layer (metal-1) and the zero metal layer (metal-0)).

[0062] Similar to the intermediate strip region 390, the intermediate strip region 391 may also include one or more conductive vias or metal lines to facilitate the establishment of a connection between the BL signal line 410 and the BL signal line segment 380C in the segment 310C of the SRAM cell array region. For example, the conductive vias and / or metal lines of the intermediate strip region 391 may be similar to the conductive vias 630, 650, and 640 of FIG. 6, except that the conductive vias and / or metal lines of the intermediate strip region 391 may be configured in the interconnect structure 620 on the back side.

[0063] In the embodiments of Figures 5A to 5C, the original integrated circuit layout design 500 is modified to produce modified integrated circuit layout designs 510A to 510B, which include three segments (segments 310A to 310C) of the SRAM cell array region. However, dividing a single, continuous SRAM cell array region 310 into three segments (segments 310A to 310C) is merely one example, and it is understood that in other embodiments, the SRAM cell array region 310 may be divided into a different number of segments. For example, referring to Figures 7A to 7C, the original integrated circuit layout design 500 is modified to produce modified integrated circuit layout designs 510A to 510C, which include four segments (segments 310A to 310D) of the SRAM cell array region. For simplicity, the original integrated circuit layout design 500 is omitted in Figures 7A to 7C, as it is consistent with that shown in Figure 5A. Furthermore, for consistency and clarity, similar components appearing in Figures 5A to 5C and Figures 7A to 7C are labeled with the same reference numerals.

[0064] As shown in Figures 7A to 7C, the original integrated circuit layout design 500 is modified to produce modified integrated circuit layout designs 510A to 510C. These integrated circuit layout designs are also planar top views of a horizontal plane defined by the X and Y directions, and may include a Graphical Data System (GDS) file. In this embodiment, the SRAM cell array region 310 is divided into four different segments (segment 310A, segment 310B, segment 310C, and segment 310D) separated from each other by intermediate strip regions 390, 391, and 392. Segments 390A to 380D of the BL signal lines (configured in the 0th metal layer (metal-0) of the front interconnect structure) are respectively arranged in the four different segments (segments 310A to 310D) of the SRAM cell array region. As described above, the BL signal line 400 (distributed in the second metal layer (metal-2) of the front interconnect structure) spans segment 310A of the SRAM cell array region and terminates in the intermediate strip region 390 to provide bit line (BL) signals to the SRAM circuitry in segment 310B of the SRAM cell array region, while bypassing segment 310A. The BL signal line 410 (distributed in the back-side 0 metal layer (B-metal-0) of the back interconnect structure) spans from segment 310A to segment 310B of the SRAM cell array region and terminates in the intermediate strip region 391 to provide BL signals to the SRAM circuitry in segment 310C of the SRAM cell array region, while bypassing segment 310A to segment 310B.

[0065] Furthermore, a BL signal line 700 is disposed in the back-side second metal layer (B-metal-2) of the back-side interconnect structure. The back-side second metal layer (B-metal-2) is located two layers below (or above, depending on the reference) the back-side zero metal layer (B-metal-0), similar to how the second metal layer (metal-2) is located two layers above the zero metal layer (metal-0) of the front-side interconnect structure. The BL signal line 700 spans segments 310A to 310C of the SRAM cell array region and terminates in the intermediate strip region 392 to provide bit line (BL) signals to the SRAM circuitry in segment 310D of the SRAM cell array region, while bypassing segments 310A to 310C. In other words, the BL signal line 700 can act as a "highway" for bit line (BL) signals, just like the BL signal lines 400-410 discussed above.

[0066] The BL signal line 700 has a dimension 710 in the X direction that is longer than the dimension 540 of each of segments 380A to 380D of the BL signal line. The BL signal line 700 has a width 720 in the Y direction that is wider than the width 560 of segments 380A to 380D of the BL signal line. In some embodiments, because the BL signal line 700 needs to travel a longer distance than BL signal line 400 or BL signal line 410, the width 720 may be implemented as a width larger than the width 570 of BL signal line 400 or the width 590 of BL signal line 410. This means that increasing the width 720 to reduce the parasitic resistance of the BL signal line 700 may bring more benefits. In some embodiments, the width 720 is between about 30 nm and about 60 nm, and the width 560 is between about 20 nm and about 60 nm. Furthermore, the distance 725 between adjacent pairs of BL signal lines 700 is greater than the distance 565 between segments 380D of adjacent pairs of BL signal lines. This also substantially helps to reduce parasitic capacitance associated with the BL signal lines 700, for reasons similar to those discussed above regarding the BL signal lines 400. In some embodiments, the distance 725 is between about 200 nm and about 500 nm, and the distance 565 is between about 200 nm and about 500 nm. This range is specifically configured to ensure that the BL signal lines 700 can provide reduced parasitic effects while maintaining sufficient routing flexibility.

[0067] The BL signal line 700 may terminate in an intermediate strip region 392, which may also include one or more conductive vias or metal lines to facilitate the establishment of a connection between the BL signal line segment 700 and the BL signal line segment 380D in the segment 310D of the SRAM cell array region. For example, the intermediate strip region 392 may include conductive vias similar to conductive vias 630 and 650 in FIG. 6, except that these conductive vias may be located in the back interconnect structure 620. The intermediate strip region 392 may also include a metal line similar to a metal line 640 of the first metal layer (metal-1), except that this metal line may also be located in the back first metal layer (B-metal-1) of the back interconnect structure 620. In any case, through these conductive vias and / or metal lines, the BL signal line 700 may carry the BL signal directly to the SRAM circuitry in section 310D of the SRAM cell array region, while bypassing section 310A to section 310C.

[0068] Referring to Figures 8A and 8B, a front plan view and a back plan view of a portion of an integrated circuit layout are illustrated, respectively. For example, Figure 8A illustrates the various thin layers of an integrated circuit layout of an SRAM cell 800 from the front, and Figure 8B illustrates the various thin layers of an integrated circuit layout of an SRAM cell 800 from the back. The SRAM cell 800 has a cell height 810 measured in the Y direction. The SRAM cell 800 also includes a plurality of active regions 820, each extending horizontally in the X direction. The active regions 820 may include portions of the fin structure of a FinFET device or portions of the nanostructure of a gate-all-around (GAA) device, as described above with reference to Figures 1A to 1C. The SRAM cell 800 also includes a plurality of gate structures 830, each extending horizontally in the Y direction. The gate structure 830 may also include the gate structure of the FinFET device or the gate all-loop (GAA) device discussed above with reference to Figures 1A to 1C.

[0069] The front side of the SRAM cell 800 shown in Figure 8A includes metal lines, such as metal lines 840, 841, and 842 in the metal-0 layer. In the illustrated embodiment, metal line 840 corresponds to a bit line (BL), metal line 841 corresponds to a word line (WL), and metal line 842 corresponds to a Vcc. Note that there may be some overlap (in the Y direction) between certain metal lines and active regions (e.g., between metal line 840 and active region 820). In some embodiments, metal line 840 may be an embodiment of one of the signal lines 380A to 380D discussed above. Metal line 840 may have a width 850 measured in the Y direction and be spaced apart from metal lines 841 and 842 in the Y direction by distances 851 and 852, respectively. For simplicity, other metal layers, such as the metal-1 layer, the metal-2 layer, etc., are not specifically described herein.

[0070] As shown in Figure 8B, the back side of the SRAM cell 800 also includes an active region 820 and a gate structure 830, as well as metal lines, such as metal lines 860, 861, and 862 in the back-side B-metal-0 layer. In the illustrated embodiment, metal line 860 corresponds to a bit line (BL), metal line 861 corresponds to Vss, and metal line 862 corresponds to Vcc. Note that there may be some overlap (in the Y direction) between certain metal lines and active regions (e.g., between metal line 860 and active region 820). In some embodiments, metal line 860 may be an embodiment of one of the BL signal lines 410 discussed above. Metal line 860 may have a width 870 measured in the Y direction and is spaced apart from metal lines 861 and 862 in the Y direction by distances 871 and 872, respectively. According to various embodiments of this disclosure, width 850 is less than or equal to width 870, which helps to reduce parasitic resistance. For the sake of simplicity, other metal layers, such as the second metal layer on the back side (B-metal-2), are not specifically described in this article.

[0071] Figure 9 illustrates an integrated circuit manufacturing system 900 according to an embodiment of the present disclosure. For example, the integrated circuit manufacturing system 900 can be used to generate or modify an integrated circuit layout design, and to manufacture an integrated circuit device based on the integrated circuit layout design. The integrated circuit manufacturing system 900 includes multiple physical entities (physical entity 902, physical entity 904, physical entity 906, physical entity 908, physical entity 910, physical entity 912, physical entity 914, physical entity 916..., physical entity N), which are connected via a communication network 918. The communication network 918 can be a single network or various different networks, such as intranets and the Internet, and can include wired and wireless communication channels.

[0072] In one embodiment, entity 902 represents a service system for generating collaboration; entity 904 represents a user, such as a product engineer monitoring products of interest; entity 906 represents an engineer, such as a process engineer controlling processes and related formulations, or an equipment engineer monitoring or adjusting the conditions and settings of process tools; entity 908 represents a measurement tool for testing and measuring integrated circuits; entity 910 represents a semiconductor process tool, such as an EUV tool for performing lithography to define active regions; entity 912 represents a virtual measurement module associated with entity 910; entity 914 represents an advanced process control module associated with entity 910 and other process tools; and entity 916 represents a sampling module associated with entity 910.

[0073] Each physical component can interact with other physical components and can provide and / or receive integrated circuit manufacturing, process control, and / or computing capabilities from other physical components. Each physical component may also contain one or more computer systems for performing calculations and implementing automation. For example, the advanced process control module of physical component 914 may contain multiple computer hardware components with encoded software instructions. The computer hardware may include hard drives, flash drives, optical drives, random access memory, display devices (e.g., monitors), and input / output devices (e.g., mice and keyboards). The software instructions can be written in any suitable programming language and can be designed to perform specific tasks.

[0074] The integrated circuit manufacturing system 900 supports interaction between physical components to enable integrated circuit manufacturing and advanced process control in integrated circuit manufacturing. In one embodiment, advanced process control includes adjusting process conditions, settings, and / or recipes applicable to one of the process tools of the relevant wafer based on measurement results.

[0075] In another embodiment, measurement results are obtained from a subset of post-processed wafers based on an optimal sampling rate determined based on process quality and / or product quality. In another embodiment, measurement results are obtained from selected fields / points within a subset of post-processed wafers based on an optimal sampling field / point determined based on various characteristics of process quality and / or product quality.

[0076] One of the functions provided by the integrated circuit process system 900 is to enable collaboration and information access in areas such as design, engineering and process, measurement, and advanced process control. Another function provided by the integrated circuit process system 900 is to integrate the system between devices, such as measurement tools and process tools. Through this integration, the devices can operate in a coordinated manner. For example, integrating measurement tools and process tools allows manufacturing information to be more effectively integrated into the process or APC module, and wafer data can be obtained from online or field measurement operations using measurement tools integrated into the relevant process tools.

[0077] Figure 10 is a flowchart illustrating a method 1000 for manufacturing an electronic memory device. In some embodiments, the electronic memory device includes an SRAM device. Method 1000 includes an operation 1010 to form a non-memory cell circuit in a first region of a substrate and a memory cell circuit in a second region of the substrate. In a plan view, the first region and the second region are disposed adjacent to each other in a first horizontal direction. Method 1000 includes an operation 1020 to form a first interconnect structure on a front side of the substrate in a cross-sectional side view. The first interconnect structure includes at least a first interconnect layer and a second interconnect layer disposed on the first interconnect layer. The first interconnect layer includes a first conductive element configured to route a predefined memory signal to a memory cell circuit located in a first segment of the second region. The second interconnect layer includes a second conductive element configured to route a predefined memory signal to a memory cell circuit located in a second segment of the second region.

[0078] Method 1000 includes an operation 1030 to form a second interconnect structure on a back side of a substrate in a cross-sectional side view. The second interconnect structure includes at least one third interconnect layer. The third interconnect layer includes a third conductive element configured to route predefined memory signals to memory cell circuitry located in a third segment of a second region. Both the third segment and the second segment are further away from the first region than the first segment.

[0079] In some embodiments, in a plan view, the formation of the first interconnect structure and the second interconnect structure is such that the second conductive element and the third conductive element are wider than the first conductive element in a second horizontal direction perpendicular to the first horizontal direction.

[0080] In some embodiments, the third segment is further away from the first region than the second segment, and the formation of the first interconnect structure and the second interconnect structure makes the third conductive element wider than the second conductive element in the second horizontal direction.

[0081] Understandably, method 1000 may include additional operations performed before, during, or after operations 1010 to 1030. For example, method 1100 may include an operation that operates the electronic memory device at least in part by generating a bit-line (BL) signal as a predefined memory signal. For simplicity, these additional operations are not discussed in detail herein.

[0082] Figure 11 is a flowchart illustrating a method 1100 for modifying an integrated circuit layout design according to an embodiment of the present disclosure. Method 1100 includes an operation 1110 to access a first integrated circuit layout design of an electronic memory device. The first integrated circuit layout design includes: a non-memory cell region, a memory cell region located adjacent to the non-memory cell region in a first horizontal direction, and a first signal line extending from the non-memory cell region to the memory cell region in the first horizontal direction. The first signal line extends in the first horizontal direction through a large portion of the memory cell region.

[0083] Method 1100 includes an operation 1120 to modify a first integrated circuit layout design to a second integrated circuit layout design. The modification operation includes providing at least one second signal line and one third signal line, the at least one second signal line and the third signal line being configured to carry a signal of the same type as one of the first signal lines, such that the second signal line and the third signal line extend in a first horizontal direction from a non-memory cell region to different portions of a memory cell region. The second signal line and the third signal line are configured on a different interconnect layer than the first signal line.

[0084] In some embodiments, the layout design of the first integrated circuit is modified such that, in a second horizontal direction, both the second signal line and the third signal line have a width greater than that of the first signal line. The second horizontal direction differs from the first horizontal direction.

[0085] In some embodiments, in the first integrated circuit layout design and the second integrated circuit layout design, the first signal line is disposed in a first interconnect layer of a front interconnect structure of the electronic memory device. In the second integrated circuit layout design, the second signal line is disposed in a second interconnect layer of a front interconnect structure different from the first interconnect layer, and the third signal line is disposed in a third interconnect layer of a back interconnect structure of the electronic memory device.

[0086] In some embodiments, the layout design of the first integrated circuit is modified such that the third signal line has a larger dimension than the second signal line in the first horizontal direction.

[0087] In some embodiments, the modified first integrated circuit layout design further includes configuring one or more strip regions in the memory cell region, the one or more strip regions being configured to route electrical signals from a second signal line or a third signal line to a first signal line.

[0088] In some embodiments, the electronic memory device includes an SRAM device, and the first signal line, the second signal line, and the third signal line are all configured to carry a bit line (BL) signal for the SRAM device.

[0089] Understandably, method 1100 may include additional operations performed before, during, or after operations 1110-1120. For example, method 1100 may include an operation of manufacturing an electronic memory device according to a second integrated circuit layout design. For simplicity, these additional operations are not discussed in detail herein.

[0090] The advanced lithography processes, methods, and materials described above can be used in many applications, including FinFETs. For example, fins can be patterned to create relatively tight spacing between features, and the above disclosures are well-suited for this purpose. Furthermore, the spacers (also called mandrels) used to form the fins of the FinFET can be fabricated according to the above disclosures. It is also understood that the embodiments of this disclosure discussed above may be applicable to multichannel devices, such as gate-all-around (GAA) devices. In the context of this disclosure relating to fin structures or FinFET devices, such discussions may also apply to GAA devices.

[0091] In summary, this disclosure implements additional memory device signal lines (e.g., BL signal lines) located in other interconnect layers to assist in routing specific memory device signals (e.g., BL signals) to different regions of an SRAM cell array. For example, the SRAM cell array region may be divided into three regions: a near region, an intermediate region, and a far region, relative to a peripheral circuit region that generates the specified memory device signal. In some embodiments, a metal line from a first metal layer (metal-0) of a front interconnect structure is used to route the specific memory signal to the near region, a metal line from a second metal layer (metal-2) of the front interconnect structure is used to route the specific memory signal to the intermediate region, and a metal line from a back-side first metal layer (metal-0) of a back interconnect structure is used to route the specific memory signal to the far region.

[0092] This type of implementation may have certain advantages. However, it is understood that not all advantages are discussed herein, different embodiments may provide different advantages, and no particular advantage is required in any embodiment. One advantage is reduced load. For example, a BL signal line extending through a long SRAM cell array (e.g., greater than 128 bits) may cause load problems. By dividing the long BL signal line into multiple smaller segments, load problems can be reduced. Another advantage is reduced parasitic resistance. For example, BL signal lines configured in the second metal layer (metal-2) of the front interconnect structure or the back-side 0 metal layer (B-metal-0) of the back interconnect structure have a width wider than the BL signal lines in the 0 metal layer (metal-0) of the front interconnect structure. Since the width of a metal line is inversely proportional to its parasitic resistance, the wider width of these additional BL signal lines may substantially result in lower parasitic resistance. Another advantage is reduced parasitic capacitance. For example, BL signal lines in the second metal layer (metal-2) of the front interconnect structure or in the back-side zero metal layer (B-metal-0) of the back interconnect structure may be further away from the BL signal lines closest to them in that thin layer, and since the spacing between two metal lines is inversely proportional to their parasitic capacitance, the larger spacing between these BL signal lines may substantially result in lower parasitic capacitance. Furthermore, the location of these BL signal lines (e.g., not in the zero metal layer (metal-0) of the front interconnect structure) substantially results in a larger spacing between the BL signal lines and other conductive elements in the SRAM array circuitry, which also helps to reduce parasitic capacitance. Due to the reduction in parasitic effects, device performance (such as speed and / or power consumption) may be improved. Other advantages may include compatibility with existing processes (including FinFET and Gate All-Round (GAA) processes), and a simple and low-cost implementation.

[0093] It is understood that although the embodiments disclosed herein are discussed using electronic memory devices as examples, these embodiments are not limited to electronic memory devices unless otherwise required. The concept of providing additional signal lines in various interconnect layers to assist in routing electronic signals is also applicable to other suitable integrated circuit applications.

[0094] One aspect of this disclosure relates to an electronic memory device. The electronic memory device includes a non-memory cell region including a non-memory cell circuit at least partially formed in a substrate; a memory cell region including a memory cell circuit at least partially formed in the substrate, wherein the memory cell region includes at least a first segment, a second segment, and a third segment, wherein in a top view, the first segment is closest to the non-memory cell region, and wherein in the top view, the second and third segments are both further away from the non-memory cell region than the first segment; and a first interconnect structure, in a cross-sectional side view, disposed on a first side of the substrate, wherein the first interconnect structure includes at least a first... An interconnect layer and a second interconnect layer, wherein the first interconnect layer is configured to route a specific type of memory signal from a non-memory cell region to a first segment of a memory cell region, and wherein the second interconnect layer is configured to route the specific type of memory signal from the non-memory cell region to a second segment of a memory cell region; and a second interconnect structure, in a cross-sectional side view, disposed on a second side of a substrate, wherein the second side is different from the first side, wherein the second interconnect structure includes at least one third interconnect layer, wherein the third interconnect layer is configured to route the specific type of memory signal from the non-memory cell region to a third segment of a memory cell region.

[0095] In some embodiments, the electronic memory device includes a static random access memory (SRAM) device; and a specific type of memory signal includes a bit-line signal of the SRAM device. In some embodiments, in a top view, the third segment is further away from the non-memory cell region than the second segment. In some embodiments, the memory cell region further includes a fourth segment; in a top view, the fourth segment is further away from the non-memory cell region than the third segment; the second interconnect structure further includes a fourth interconnect layer; and the fourth interconnect layer is configured to route the specific type of memory signal from the non-memory cell region to the fourth segment of the memory cell region. In some embodiments, the first interconnect layer includes a first conductive element configured to route a specific type of memory signal from a non-memory cell region to a first segment of the memory cell region; the second interconnect layer includes a second conductive element configured to route the specific type of memory signal from the non-memory cell region to a second segment of the memory cell region; the third interconnect layer includes a third conductive element configured to route the specific type of memory signal from the non-memory cell region to a third segment of the memory cell region; and in a top view, the third conductive element has a larger lateral dimension than the second conductive element. In some embodiments, in a top view, the first, second, and third conductive elements all extend along a first direction; in the top view, in the first direction, the second conductive element has a larger dimension than the first conductive element; and in the top view, in the first direction, the third conductive element has a larger dimension than the second conductive element. In some embodiments, in a top view, in a second direction perpendicular to the first direction, both the second and third conductive elements have a larger dimension than the first conductive element. In some embodiments, the first interconnect layer further includes a fourth conductive element located in a second segment of the memory cell region and a fifth conductive element located in a third segment of the memory cell region; the memory cell region further includes a first strip region located between the first and second segments of the memory cell region and a second strip region located between the second and third segments of the memory cell region; the first strip region includes one or more first conductive vias facilitating a routing operation that routes a specific type of memory signal from a second conductive element of the second interconnect layer to a fourth conductive element of the first interconnect layer; and the second strip region includes one or more second conductive vias facilitating a routing operation that routes a specific type of memory signal from a third conductive element of the third interconnect layer to a fifth conductive element of the first interconnect layer. In some embodiments, in a cross-sectional side view, the first interconnect structure further includes an additional interconnect layer disposed between the first and second interconnect layers; and the additional interconnect layer does not include a plurality of conductive elements for routing specific type of memory signals. In some embodiments, the non-memory cell region includes an input / output circuit that serves as a non-memory cell circuit of an electronic memory device.

[0096] One aspect of this disclosure relates to a method for manufacturing an electronic memory device. A non-memory cell circuit is formed in a first region of a substrate, and a memory cell circuit is formed in a second region of the substrate. In a planar top view, the first region and the second region are adjacent to each other in a first horizontal direction. In a cross-sectional side view, a first interconnect structure is formed on a front side of the substrate. The first interconnect structure includes at least one first interconnect layer and a second interconnect layer disposed on the first interconnect layer. The first interconnect layer includes a first conductive element configured to route a predefined memory signal to a memory cell circuit located in a first segment of the second region. The second interconnect layer includes a second conductive element configured to route a predefined memory signal to a memory cell circuit located in a second segment of the second region. In a cross-sectional side view, a second interconnect structure is formed on a back side of the substrate. The second interconnect structure includes at least one third interconnect layer. The third interconnect layer includes a third conductive element configured to route a predefined memory signal to a memory cell circuit located in a third segment of the second region. Both the third segment and the second segment are farther away from the first region than the first segment.

[0097] In some embodiments, in a plan view, the formation of the first and second interconnect structures such that, in a second horizontal direction perpendicular to the first horizontal direction, the second and third conductive elements are wider than the first conductive element. In some embodiments, the third segment is further away from the first region than the second segment; and the formation of the first and second interconnect structures such that, in the second horizontal direction, the third conductive element is wider than the second conductive element. In some embodiments, the electronic memory device is operated at least in part by generating a bit-line signal as a predefined memory signal.

[0098] Another aspect of this disclosure relates to a method for modifying an integrated circuit layout design. Accessing a first integrated circuit layout design of an electronic memory device, wherein the first integrated circuit layout design includes a non-memory cell region; a memory cell region disposed adjacent to the non-memory cell region in a first horizontal direction; and a first signal line extending from the non-memory cell region to the memory cell region in the first horizontal direction, wherein the first signal line extends through a large portion of the memory cell region in the first horizontal direction; and performing a modification operation to modify the first integrated circuit layout design into a second integrated circuit layout design, wherein the modification operation includes configuring at least one second signal line and one third signal line such that, in the first horizontal direction, the second signal line and the third signal line extend from the non-memory cell region to different portions of the memory cell region, wherein the second signal line and the third signal line are configured to carry a signal of the same type as that of the first signal line, and the second signal line and the third signal line are configured on multiple interconnect layers different from the first signal line.

[0099] In some embodiments, modifications to the first integrated circuit layout design are performed such that, in a second horizontal direction, both the second and third signal lines are configured to have a width greater than the first signal line, wherein the second horizontal direction differs from the first horizontal direction. In some embodiments, in both the first and second integrated circuit layout designs, the first signal line is disposed in a first interconnect layer of a front interconnect structure of one of the electronic memory devices; and in the second integrated circuit layout design, the second signal line is disposed in a second interconnect layer of a front interconnect structure different from the first interconnect layer, and the third signal line is disposed in a third interconnect layer of a back interconnect structure of one of the electronic memory devices. In some embodiments, modifications to the first integrated circuit layout design are performed such that, in the first horizontal direction, the third signal line has a larger dimension than the second signal line. In some embodiments, modifications to the first integrated circuit layout design further include configuring one or more strip regions in the memory cell region, the one or more strip regions being configured to route multiple electrical signals from the second or third signal line to the first signal line. In some embodiments, the electronic memory device includes a static random access memory device; and the first signal line, the second signal line, and the third signal line are all configured to carry a bit line signal for the static random access memory device.

[0100] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily utilize this disclosure as a basis for designing or modifying other processes and structures to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0101] The foregoing outlines features of several embodiments. Those skilled in the art will understand that they can readily utilize this disclosure as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0102] 90: Integrated circuit device 110:Substrate 120,10: Protrusion structure / fin structure 122,20: Source / Drain Characteristics 130: Isolation Structure 140,830: Gate structure 5: Integrated circuit devices / Gate-All-Around (GAA) devices 91: Gate spacer 30, 31, 32, 33: Channels 40: Interface Layer 50: Gate dielectric layer 60: Work function metal layer 80: Filler metal 95: Internal spacers 96: Source / drain contact 97A, 97B: Barrier Layer 98: Silicon layer 99: Interlayer dielectric layer 200: Single-port SRAM cell BL: Bitline BLB: Reverse Position Line Vcc: Power supply voltage Vss: Voltage WL: Character Line PU1, PU2: Pull-up transistors PD1, PD2: Pull-down transistors PG1, PG2: Transmission transistors SN1, SNB1: Storage nodes 300: Electronic Memory Device 310: SRAM cell array area 320: Input / Output (I / O) Area 340: Control Circuit Area 330: Character line driver area 380: Memory Signal Cable / BL Signal Cable 310A, 310B, 310C, 310D: Sections 390, 391, 392: Intermediate band-shaped area 380A, 380B, 380C, 380D: Sections 400, 410, 700: BL signal lines 500: Original Integrated Circuit Layout Design 510A, 510B, 510C: Modified Integrated Circuit Layout Design 520, 530, 540, 550, 580, 710: Size 560, 570, 590, 720, 850: Width 565,575,595,725,851,852,870,871,872: Distance 600: Device Area 610, 620: Interconnection structure 630, 650: Conductive vias 640, 840, 841, 842, 860, 861, 862: Metal wire 800: SRAM cell 810: Altitude 820: Active Area 900: Integrated Circuit Manufacturing System 902,904,906,908,910,912,914,916,918,N: Solid components 1000, 1100: Method 1010, 1020, 1030, 1110, 1120: Operations

Claims

1. An electronic memory device, comprising: A non-memory cell region includes a non-memory cell circuit at least partially formed in a substrate; a memory cell region includes a memory cell circuit at least partially formed in the substrate, wherein the memory cell region includes at least a first segment, a second segment and a third segment, wherein in a top view, the first segment is closest to the non-memory cell region, and wherein in the top view, the second segment and the third segment are both further away from the non-memory cell region than the first segment; A first interconnect structure, in a cross-sectional side view, is disposed on a first side of the substrate, wherein the first interconnect structure includes at least a first interconnect layer and a second interconnect layer, wherein the first interconnect layer is configured to route a specific type of memory signal from the non-memory cell region to a first segment of the memory cell region, wherein the second interconnect layer is configured to route the specific type of memory signal from the non-memory cell region to a second segment of the memory cell region; and a second interconnect structure, in the cross-sectional side view, is disposed on a second side of the substrate, wherein the second side is different from the first side, wherein the second interconnect structure includes at least a third interconnect layer, wherein the third interconnect layer is configured to route the specific type of memory signal from the non-memory cell region to a third segment of the memory cell region.

2. The electronic memory device as described in claim 1, wherein: The electronic memory device includes a static random access memory device; and the specific type of memory signal includes a bit line signal of the static random access memory device.

3. The electronic memory device as claimed in claim 1, wherein: in the top view, the third segment is further away from the non-memory cell region than the second segment; the memory cell region further includes a fourth segment; in the top view, the fourth segment is further away from the non-memory cell region than the third segment; the second interconnect structure further includes a fourth interconnect layer; the fourth interconnect layer is configured to route a specific type of memory signal from the non-memory cell region to the fourth segment of the memory cell region; in the cross-sectional side view, the first interconnect structure further includes an additional interconnect layer disposed between the first interconnect layer and the second interconnect layer; the additional interconnect layer does not include a plurality of conductive elements for routing the specific type of memory signal; and the non-memory cell region includes an input / output circuit as the non-memory cell circuit of the electronic memory device.

4. The electronic memory device as described in claim 1, wherein: The first interconnect layer includes a first conductive element configured to route a specific type of memory signal from the non-memory cell region to the first segment of the memory cell region; the second interconnect layer includes a second conductive element configured to route the specific type of memory signal from the non-memory cell region to the second segment of the memory cell region; the third interconnect layer includes a third conductive element configured to route the specific type of memory signal from the non-memory cell region to the third segment of the memory cell region; in the top view, the third conductive element has a larger lateral dimension than the second conductive element; in the top view, the first conductive element, the second conductive element, and the third conductive element all extend along a first direction; in the top view, in the first direction, the second conductive element has a larger dimension than the first conductive element; In the top view, in the first direction, the third conductive element has a larger size than the second conductive element; and in the top view, in a second direction perpendicular to the first direction, both the second conductive element and the third conductive element have a larger size than the first conductive element.

5. The electronic memory device as described in claim 4, wherein: The first interconnect layer further includes a fourth conductive element located in the second segment of the memory cell region and a fifth conductive element located in the third segment of the memory cell region; the memory cell region further includes a first strip region located between the first segment and the second segment of the memory cell region and a second strip region located between the second segment and the third segment of the memory cell region; the first strip region includes one or more first conductive vias facilitating a routing operation that routes a specific type of memory signal from the second conductive element of the second interconnect layer to the fourth conductive element of the first interconnect layer; and the second strip region includes one or more second conductive vias facilitating a routing operation that routes a specific type of memory signal from the third conductive element of the third interconnect layer to the fifth conductive element of the first interconnect layer.

6. A method for manufacturing an electronic memory device, comprising: A non-memory cell circuit is formed in a first region of a substrate, and a memory cell circuit is formed in a second region of the substrate, wherein in a planar top view, the first region and the second region are arranged adjacent to each other in a first horizontal direction; In a cross-sectional side view, a first interconnect structure is formed on a front side of the substrate, wherein the first interconnect structure includes at least a first interconnect layer and a second interconnect layer disposed on the first interconnect layer, wherein the first interconnect layer includes a first conductive element configured to route a predefined memory signal to a memory cell circuit located in a first segment of a second region, wherein the second interconnect layer includes a second conductive element configured to route the predefined memory signal to a memory cell circuit located in a second segment of a second region; and in the cross-sectional side view, a second interconnect structure is formed on a back side of the substrate, wherein the second interconnect structure includes at least a third interconnect layer, wherein the third interconnect layer includes a third conductive element configured to route the predefined memory signal to a memory cell circuit located in a third segment of a second region, wherein the third segment and the second segment are both further away from the first region than the first segment.

7. A method of manufacturing an electronic memory device as claimed in claim 6, wherein: in the plan view, the first interconnect structure and the second interconnect structure are formed such that, in a second horizontal direction perpendicular to the first horizontal direction, the second conductive element and the third conductive element are wider than the first conductive element; the third segment is further away from the first region than the second segment; and the first interconnect structure and the second interconnect structure are formed such that, in the second horizontal direction, the third conductive element is wider than the second conductive element.

8. A method for modifying integrated circuit layout design, comprising: A first integrated circuit layout design for accessing an electronic memory device, wherein the first integrated circuit layout design includes: a non-memory cell region; a memory cell region disposed adjacent to the non-memory cell region in a first horizontal direction; a first signal line extending from the non-memory cell region to the memory cell region in the first horizontal direction, wherein the first signal line extends through a large portion of the memory cell region in the first horizontal direction; and a modification operation performing a modification of the first integrated circuit layout design to a second integrated circuit layout design, wherein the modification operation includes configuring at least a second signal line and a third signal line such that, in the first horizontal direction, the second signal line and the third signal line extend from the non-memory cell region to different portions of the memory cell region, wherein the second signal line and the third signal line are configured to carry a signal of the same type as that of the first signal line, and the second signal line and the third signal line are disposed on a plurality of interconnect layers different from the first signal line.

9. A method for modifying an integrated circuit layout design as described in claim 8, wherein: the modification operation performed on the first integrated circuit layout design is such that, in a second horizontal direction, both the second signal line and the third signal line are configured to have a width greater than that of the first signal line, wherein the second horizontal direction is different from the first horizontal direction; the modification operation performed on the first integrated circuit layout design is such that, in the first horizontal direction, the third signal line has a larger size than that of the second signal line; and the modification operation of the first integrated circuit layout design further includes configuring one or more strip regions in the memory cell region, the one or more strip regions being configured to route multiple electrical signals from the second signal line or the third signal line to the first signal line.

10. A method for modifying the layout design of integrated circuits as described in claim 8, wherein: In the first integrated circuit layout design and the second integrated circuit layout design, the first signal line is disposed in a first interconnect layer of the front interconnect structure of one of the electronic memory devices; and in the second integrated circuit layout design, the second signal line is disposed in a second interconnect layer of the front interconnect structure, which is different from the first interconnect layer, and the third signal line is disposed in a third interconnect layer of the back interconnect structure of one of the electronic memory devices.

Images