Semiconductor structure in memory device

Abstract

A method, device, and system for managing a layout of a semiconductor structure in a memory device are provided. In an aspect, the memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first memory bank and a second memory bank. The second semiconductor structure includes a first memory bank circuit and a second memory bank circuit arranged along a first direction. The first memory bank circuit is coupled to the first memory bank, and the second memory bank circuit is coupled to the second memory bank. The first memory bank circuit includes a first driver circuit on a boundary of the first memory bank circuit, and the second memory bank circuit includes a second driver circuit on a boundary of the second memory bank circuit. At least a portion of the first driver circuit is adjacent to and overlaps with at least a portion of the second driver circuit along a second direction perpendicular to the first direction.

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