Non-volatile memory and programming method thereof

Abstract

The present invention provides a non-volatile memory and a programming method thereof. The non-volatile memory may be a three-dimensional NAND flash memory with high capacity and high performance. The non-volatile memory includes a memory cell array and a control circuit. During a programming period for programming multiple memory cells of a current word line, the control circuit reads at least one threshold voltage of at least one neighboring word line adjacent to the current word line. The control circuit checks the at least one threshold voltage of the at least one neighboring word line to generate a check result. According to the inspection result, the control circuit adjusts a programming verification voltage used to verify the current word line during the programming period.

Description

Technical Field

[0001] This invention relates to a memory device, and more particularly to a non-volatile memory (e.g., a three-dimensional inverse and gate-type flash memory) and a method for programming the same. Prior Technology

[0002] Integrated circuit memory (ICM) incorporating high-capacity and high-performance 3D NAND flash memory continues to evolve. To overcome the challenges of size reduction, the NAND flash memory industry has transitioned from planar architectures to 3D architectures. The storage capacity of 3D vertical NAND flash memory has increased steadily over the past decade to meet the needs of various industries, including mobile and data centers. The increase in the number of stacked word lines (WLs) has played a key role in achieving higher storage capacity or bit density. This paradigm shift allows for increased storage density through the vertical stacking of storage cells, rather than solely relying on cell miniaturization. Charge-trap technology uses continuous silicon nitride layers as storage nodes (SNs). Compared to floating gate technology, charge-trap technology is widely used in 3D NAND flash memory arrays due to its simpler manufacturing process and higher vertical scaling capabilities. However, as the number of stacked layers increases, the read VT window becomes increasingly poor. Tightening the critical voltage distribution width of triple-level cells (TLC) or quad-level cells (QLC) in the threshold voltage (VT) distribution map has become one of the many technical issues in 3D NAND. Summary of the Invention

[0003] This invention provides a non-volatile memory and its programming method.

[0004] In one embodiment of the invention, the aforementioned non-volatile memory includes a memory cell array and a control circuit. The memory cell array has a plurality of memory cells. Each of a plurality of word lines is coupled to a plurality of memory cells in a corresponding column. Each of a plurality of bit lines is coupled to a plurality of memory cells in a corresponding row. The control circuit is coupled to the memory cell array. During programming of the plurality of memory cells for the current word line among these word lines, the control circuit reads at least one threshold voltage (VT) of at least one adjacent word line adjacent to the current word line. The control circuit checks the at least one threshold voltage of the at least one adjacent word line to generate a check result. Based on the check result, the control circuit adjusts the programming verification voltage used to verify the current word line during programming.

[0005] In one embodiment of the present invention, the above-described programming method is applicable to non-volatile memory. The programming method includes: during programming of a plurality of first memory cells of a current word line, reading at least one critical voltage of at least one neighboring word line adjacent to the current word line; checking the at least one critical voltage of the at least one neighboring word line to generate a check result; and adjusting the programming verification voltage used to verify the current word line during programming based on the check result.

[0006] Based on the above, the control circuit described in the embodiments of the present invention can read the critical voltage state of the memory cells of adjacent word lines during the programming of the memory cells of the current word line. The control circuit determines whether to adjust the programming verification voltage used to verify the current word line during programming based on the magnitude of the critical voltage of the memory cells of adjacent word lines. For example, in response to the critical voltage of an adjacent word line being determined to be high, the control circuit selects a low verification voltage as the programming verification voltage for the current word line. Conversely, in response to the critical voltage of an adjacent word line being determined to be low, the control circuit selects a high verification voltage as the programming verification voltage for the current word line. Through the adjustment of the programming verification voltage, the control circuit effectively tightens the critical voltage distribution width of the memory cells, thereby improving its data retention.

[0007] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0008] Figure 1 is a schematic diagram of a circuit block of a non-volatile memory according to an embodiment of the present invention. Figure 2 is a three-dimensional schematic diagram of a string of memory cells in a non-volatile memory according to an embodiment of the present invention. Figure 3 is a schematic diagram illustrating the distribution of multiple threshold voltages (VT) using a three-level memory cell (TLC) as an example, according to an embodiment of the present invention. Figure 4 is a schematic diagram illustrating the critical voltage distribution of the current word line affected by the neighboring word line, using a three-level memory cell (TLC) as an example, according to an embodiment of the present invention. Figure 5 is a flowchart of a programming method for non-volatile memory according to an embodiment of the present invention. Figure 6 is a schematic diagram of the critical voltage distribution of word lines, using a three-level memory cell (TLC) as an example, according to another embodiment of the present invention. Figure 7 is a flowchart of a programming method for non-volatile memory according to another embodiment of the present invention. Figure 8 is a waveform diagram of character lines and bit lines according to an embodiment of the present invention. Figure 9 is a waveform diagram of character lines and bit lines according to another embodiment of the present invention. Figure 10 is a flowchart of a programming method for non-volatile memory according to another embodiment of the present invention. Implementation

[0009] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout this specification (including the claims) are used to name elements or distinguish different embodiments or scopes, and are not intended to limit the upper or lower limit of the number of elements, nor to limit the order of elements. Furthermore, wherever possible, elements / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.

[0010] Figure 1 is a schematic circuit block diagram of a non-volatile memory 100 according to an embodiment of the present invention. The non-volatile memory 100 includes a memory cell array 110 and a control circuit 120. The control circuit 120 is coupled to the memory cell array 110. Depending on the design, in some embodiments, the control circuit 120 may be implemented as hardware circuitry. In other embodiments, the control circuit 120 may be implemented as a combination of hardware, firmware, and software (i.e., programs).

[0011] In terms of hardware, the control circuit 120 described above can be implemented as logic circuitry on an integrated circuit. For example, the functions of the control circuit 120 can be implemented in various logic blocks, modules, and circuits within one or more hardware controllers, microcontrollers, hardware processors, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), central processing units (CPUs), and / or other processing units. The functions of the control circuit 120 can be implemented as hardware circuitry, such as various logic blocks, modules, and circuits in an integrated circuit, using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages.

[0012] In software and / or firmware form, the functions of the control circuit 120 can be implemented as programming codes. For example, the control circuit 120 can be implemented using general programming languages ​​(such as C, C++, or assembly languages) or other suitable programming languages. The programming code can be recorded / stored in a non-transitory machine-readable storage medium. In some embodiments, the non-transitory machine-readable storage medium includes, for example, semiconductor memory and / or storage devices. An electronic device (e.g., a CPU, hardware controller, microcontroller, hardware processor, or microprocessor) can read and execute the programming code from the non-transitory machine-readable storage medium to implement the functions of the control circuit 120.

[0013] Figure 1 illustrates the equivalent circuitry of a 3D inverse gate NAND flash memory in a three-dimensional (3D) manner. The memory cell array 110 has multiple memory cells (e.g., memory cell M'). The multiple memory cells in the memory cell array 110 shown in Figure 1 are arranged in a 3D manner in the XYZ coordinate system. However, this does not mean that the circuitry of the memory cell array 110 is limited to a 3D configuration. In one example, the memory cell array 110 can be divided into four sub-blocks Sub0, Sub1, Sub2, and Sub3. The control circuitry 120 can independently control the operation of each sub-block (e.g., sub-block Sub0).

[0014] Each memory cell string shown in Figure 1 (e.g., memory cell strings 101, 102, or 103) comprises multiple memory cells (e.g., memory cells M') connected in series along the Z direction. The memory cell array 110 includes multiple word lines (WL), such as WL1, ..., WLi, WLi+1, ..., WLn-1, WLn, ..., WLm shown in Figure 1. One word line (e.g., word line WLn) may correspond to one layer in the XY plane. Each of the word lines WL1 to WLm is coupled to multiple memory cells in a corresponding row of these memory cells. Multiple memory cells in each memory cell string (e.g., memory cell string 101) correspond to one word line (e.g., word line WLi+1). Memory cell M can be configured as a string select transistor coupled to a string select line (SSL, such as SSL0, SSL1, SSL2, and SSL3), and another memory cell can be configured as a ground select transistor coupled to a ground select line (GSL). The string select transistor and the ground select transistor are located on opposite sides of each memory cell string (e.g., memory cell string 101). In this example, multiple memory cell strings (e.g., memory cell strings 101, 102, etc.) coupled to the same string select line (e.g., string select line SSL0) on the same plane (e.g., the plane defined by the X and Z directions) can be defined as a subblock (e.g., subblock Sub0).

[0015] Each of the multiple bit lines (BLs) is coupled to multiple memory cells in a corresponding column of these memory cells. That is, each memory cell string (e.g., memory cell string 101, 102, or 103) is connected to the corresponding bit line (e.g., bit line BL1, BLn, or BLm) via a corresponding string select transistor on a string select line (e.g., string select line SSL0). Memory cell strings (e.g., memory cell string 101) in the same column of different sub-blocks (e.g., sub-blocks Sub0, Sub1, etc.) along the Y direction are connected to the corresponding bit line (e.g., bit line BL1). The string select line (e.g., string select line SSL0) can be a conductive line or conductive layer formed above the topmost word line layer (e.g., word line WL1). Each memory cell string (e.g., memory cell string 101, 102, or 103) can be connected to the same common source line (CSL) via a corresponding ground select transistor on the ground select line GSL. The ground select line (GSL) can be a conductive line or conductive layer formed below the bottommost character line layer (e.g., character line WLm). The common source line (CSL) can be a conductive layer formed above the substrate of the non-volatile memory 100. The serial select lines (e.g., serial select lines SSL0~SSL3) in the memory cell array 110 can be on the same conductive layer, but divided into independent lines. Each independent line (serial select line) can independently control the operation of the corresponding sub-block (e.g., sub-blocks Sub0, Sub1, etc.) in the memory cell array 110.

[0016] In one example, in a single-level cell (SLC) configuration, multiple memory cells (including memory cell M') coupled to the same word line or word line layer (e.g., word line WLn) within a sub-region (e.g., sub-region Sub0) can be defined as a page. In another example, in a triple-level cell (TLC) configuration, multiple memory cells (including memory cell M') coupled to the same word line or word line layer (e.g., word line WLn) within a sub-region (e.g., sub-region Sub0) can be defined as three pages. In the TLC configuration, these three pages include a high page, a middle page, and a low page. Memory cells M' located on the same word line (e.g., word line WLn) are subjected to the same voltage. Each word line (e.g., word line WLn) can be connected to a driver circuit, such as an X-decoder (or scan driver).

[0017] In one example, one or more dummy lines or layers (not shown) may be provided between the string select lines (e.g., string select lines SSL0~SSL3) and the character line layer (e.g., character line WL1), and between the ground select line GSL and the bottommost character line layer (e.g., character line WLm). In another example, one or more dummy lines or layers (not shown) may be provided in the middle portion of each memory cell string (e.g., memory cell string 101, 102, or 103). The non-volatile memory 100 also includes control circuitry 120 for implementing corresponding operations on the memory cell array 110.

[0018] This embodiment does not limit the specific implementation of each memory cell string (e.g., memory cell string 101, 102, or 103) in the memory cell array 110. For example, FIG2 is a perspective view of a memory cell string 200 in a non-volatile memory according to an embodiment of the present invention. The memory cell string 200 shown in FIG2 can be one of many implementation examples of each memory cell string (e.g., memory cell string 101, 102, or 103) in the memory cell array 110 shown in FIG1.

[0019] The memory cell string 200 includes a channel pillar structure 210 and multiple word lines WL0~WLm formed by multiple metal layers. Figure 2 shows multiple memory cells (e.g., memory cells M') located at the intersection of the channel pillar structure 210 and each word line layer (gate layer) WL0~WLm in the 3D NAND storage device (non-volatile memory 100). Multiple memory cells M' are connected in series along the channel pillar structure 210 in the Z direction. The channel pillar structure 210 includes a dielectric core 211, a channel layer 212, a tunneling layer 213, and a charge trapping layer 214. The dielectric core 211 is, for example, an oxide-filled pillar or other dielectric material. The dielectric core 211 is surrounded by the channel layer 212. The channel layer 212 is, for example, a polysilicon channel layer or other material.

[0020] The channel layer 212 is surrounded by a multilayer dielectric material. This multilayer dielectric material includes a tunneling layer 213 (e.g., oxide), a charge trapping layer (e.g., nitride) 214, and a blocking layer (e.g., oxide) 215. The charge trapping layer 214 surrounds the channel layer 212. The dielectric core 211, the channel layer 212, and the charge trapping layer 214 extend along the Z-direction, forming a channel pillar structure 210. Memory cells within the same channel pillar structure 210 can form a memory cell string 200. The blocking layer 215 surrounds the outer surface of the charge trapping layer 214. The blocking layer 215 is located between the charge trapping layer 214 and the word line layers (gate layers) WL0~WLm.

[0021] Figure 3 is a schematic diagram illustrating the distribution of multiple threshold voltages (VT) according to an embodiment of the present invention, using a three-level memory cell (TLC) as an example. The horizontal axis of Figure 3 represents voltage, while the vertical axis represents the number or probability of memory cells. Figure 3 presents the threshold voltage distribution of multiple memory cells after programming operations. These threshold voltage distributions can be distinguished into an erased state S0 and potential states S1, S2, S3, S4, S5, S6, and S7. Potential states S1 to S7 can be programmed using reference voltages (programming verification voltages) AV, BV, CV, DV, EV, FV, and GV. The distribution curves PD31, PD32, PD33, PD34, PD35, PD36, and PD37 shown in Figure 3 represent the threshold voltage distribution of potential states S1 to S7.

[0022] The read window width of a current character line (e.g., character line WLn) is closely related to the data pattern of at least one adjacent character line (e.g., character line WLn-1). Due to charge lateral spreading, a low threshold voltage (VT) of memory cells on adjacent character lines (e.g., WLn-1 or WLn+1) leads to more charge loss in memory cells on the current character line (e.g., character line WLn), resulting in a lower threshold voltage (VT) for memory cells on the current character line. Conversely, a high threshold voltage (VT) of memory cells on adjacent character lines leads to less charge loss in memory cells on the current character line, resulting in a higher threshold voltage (VT) for memory cells on the current character line.

[0023] Figure 4 is a schematic diagram illustrating the critical voltage (VT) distribution of a current word line (e.g., word line WLn) affected by neighboring word lines (e.g., WLn-1 or WLn+1) according to an embodiment of the present invention, using a three-level memory cell (TLC) as an example. The horizontal axis of Figure 4 represents voltage, while the vertical axis represents the number or probability of memory cells. Figure 4 presents the critical voltage distribution curves PD41, PD42, PD43, PD44, PD45, PD46, and PD47 for the potential states S1 to S7 of multiple memory cells after programmed operations.

[0024] The read window width of a current character line (e.g., character line WLn) is closely related to the data pattern of at least one adjacent character line (e.g., character line WLn-1). When the memory cell on an adjacent character line (e.g., WLn-1 or WLn+1) has a low threshold voltage (VT), the adjacent character line will cause the memory cell on the current character line (e.g., character line WLn) to have a lower threshold voltage (VT), as shown by the threshold voltage distribution curves PD41L, PD42L, PD43L, PD44L, PD45L, PD46L and PD47L in Figure 4. When a memory cell on a neighboring word line (e.g., WLn-1 or WLn+1) has a high critical voltage (VT), the neighboring word line will cause a higher critical voltage (VT) for the memory cell on the current word line (e.g., word line WLn), as shown in the critical voltage distribution curves PD41H, PD42H, PD43H, PD44H, PD45H, PD46H, and PD47H in Figure 4. Therefore, the width of the critical voltage distribution curves PD41 to PD47 increases. The following embodiments will illustrate how to adjust the programming verification voltages AV to GV used to verify the current word line during programming to tighten the critical voltage (VT) distribution width in the critical voltage distribution diagram.

[0025] Figure 5 is a flowchart of a programming method for a non-volatile memory according to an embodiment of the present invention. The programming method described in Figure 5 can be implemented using the non-volatile memory 100 of Figure 1. The programming method described in Figure 5 can be applied to memory devices with different memory cell forms. The multiple memory cells in the memory cell array 110 shown in Figure 1 can be of a multi-level type. The aforementioned multi-level type can be one of a multi-level cell (MLC) type, a three-level cell (TLC) type, and a four-level cell (QLC) type. Referring to Figures 1 and 5, during the programming of multiple memory cells for the current word line (e.g., word line WLn), the control circuit 120 reads at least one critical voltage of at least one adjacent word line (step S510). In step S520, the control circuit 120 checks the at least one critical voltage of the at least one adjacent word line to generate a check result. Based on the inspection results, the control circuit 120 adjusts the programming verification voltage used to verify the current character line during programming (step S530).

[0026] Figure 6 is a schematic diagram illustrating the critical voltage (VT) distribution of word lines, using a three-level memory cell (TLC) as an example, according to another embodiment of the present invention. The horizontal axis of Figure 6 represents voltage, while the vertical axis represents the number or probability of memory cells. Figure 6 presents the critical voltage distribution curves PD61, PD62, PD63, PD64, PD65, PD66, and PD67 for the potential states S1 to S7 of multiple memory cells after programmed operation. When a memory cell on a neighboring word line (e.g., WLn-1 or WLn+1) is determined to have a low critical voltage (VT), the control circuit 120 selects a high verification voltage as the programmed verification voltage AV to GV for the current word line (e.g., WLn). As shown in Figure 6, the critical voltage distribution curves PD61L, PD62L, PD63L, PD64L, PD65L, PD66L, and PD67L are shifted to the right (compared to the critical voltage distribution curves PD41L to PD47L shown in Figure 4).

[0027] When the memory cell on an adjacent word line (e.g., WLn-1 or WLn+1) has a high threshold voltage (VT), the control circuit 120 selects a low verification voltage as the programmed verification voltage AV~GV for the current word line (e.g., WLn). As shown in Figure 6, the threshold voltage distribution curves PD61H, PD62H, PD63H, PD64H, PD65H, PD66H, and PD67H are shifted to the left (compared to the threshold voltage distribution curves PD41H~PD47H shown in Figure 4). Therefore, compared to the threshold voltage distribution curves PD41~PD47 shown in Figure 4, the width of the threshold voltage distribution curves PD61~PD67 shown in Figure 6 is effectively narrowed.

[0028] In summary, during the programming of memory cells for the current character line, the control circuit 120 can read the critical voltage state of memory cells of adjacent character lines. The control circuit 120 determines whether to adjust the programming verification voltage used to verify the current character line during programming based on the magnitude of the critical voltage (VT) of the memory cells of adjacent character lines. For example, in response to the critical voltage of an adjacent character line being determined to be high, the control circuit 120 selects a low verification voltage as the programming verification voltage for the current character line. Conversely, in response to the critical voltage of an adjacent character line being determined to be low, the control circuit 120 selects a high verification voltage as the programming verification voltage for the current character line. Through the adjustment of the programming verification voltage, the control circuit 120 effectively tightens the critical voltage distribution width of the memory cells, thereby improving its data retention.

[0029] Figure 7 is a flowchart of a programming method for a non-volatile memory according to another embodiment of the present invention. The programming method described in Figure 7 can be implemented using the non-volatile memory 100 of Figure 1. The programming method described in Figure 7 can be applied to memory devices of different memory cell types, such as multilevel memory (MLC), three-level memory (TLC), or four-level memory (QLC). Referring to Figures 1 and 7, the control circuit 120 programs the memory cell of the current word line (e.g., word line WLn) during programming. Generally, programming includes multiple programming loops to perform increment-step-pulse programming (ISPP) operations. Each programming loop includes a programming stage (step S710) and a programming verification stage (step S770). The control circuit 120 selects one of these programmed loops to perform steps S720, S730, S740, S750, and S760. That is, during programming, the control circuit 120 only reads the critical voltage of the adjacent word line in the selected programmed loop.

[0030] In a selected programming loop among multiple programming loops during programming, control circuit 120 programs multiple memory cells of the current word line (e.g., word line WLn) (step S710). In the selected programming loop that programs multiple memory cells of the current word line, control circuit 120 reads at least one threshold voltage of at least one adjacent word line (e.g., WLn-1 or WLn+1) adjacent to the current word line (step S720). In step S730, control circuit 120 checks the at least one threshold voltage of the at least one adjacent word line. In the selected programming loop, and in other programming loops following the selected programming loop, control circuit 120 can adjust the programming verification voltage used to verify the current word line based on the check result. That is, in other programming loops following the selected programming loop, control circuit 120 does not need to read the threshold voltage of the adjacent word line adjacent to the current word line again.

[0031] If the threshold voltage of a neighboring character line (e.g., WLn-1) is determined to be low (the determination result of step S740 is "No"), then the control circuit 120 selects a high verification voltage as the programmed verification voltage for the current character line (e.g., character line WLn) (step S750). Then, the control circuit 120 uses the programmed verification voltage selected in step S750 to verify the memory cell of the current character line (step S770). Conversely, if the threshold voltage of a neighboring character line (e.g., WLn-1) is determined to be high (the determination result of step S740 is "Yes"), then the control circuit 120 selects a low verification voltage as the programmed verification voltage for the current character line (e.g., character line WLn) (step S760). Then, the control circuit 120 uses the programmed verification voltage selected in step S760 to verify the memory cell of the current character line (step S770).

[0032] For example, control circuit 120 compares the critical voltage of a neighboring word line (e.g., WLn-1) with a certain threshold to generate a check result. The threshold can be defined according to the actual design and application. For example, the threshold can be the reference voltage (programmed verification voltage) DV shown in Figure 3. In response to the critical voltage of a neighboring word line (e.g., WLn-1) being less than the threshold, control circuit 120 sets the programmed verification voltage used to verify the current word line (e.g., word line WLn) to a first verification voltage level (the first verification voltage level is greater than a second verification voltage level) in step S750. In response to the critical voltage of a neighboring word line (e.g., WLn-1) being greater than the threshold, control circuit 120 sets the programmed verification voltage used to verify the current word line (e.g., word line WLn) to a second verification voltage level (the second verification voltage level is less than the first verification voltage level) in step S760.

[0033] Figure 8 is a waveform diagram of word lines and bit lines according to an embodiment of the present invention. During programming, the control circuit 120 programs the memory cell of the current word line (e.g., word line WLn) using PGMPD8. PGMPD8 includes multiple programming loops during programming. Each programming loop includes a programming stage (e.g., programming stage PGM8 shown in Figure 8) and a programming verification stage (e.g., programming verification stage PV8 shown in Figure 8). The control circuit 120 selects one of these programming loops as the selected programming loop, such as programming loop PGMLOOP8 shown in Figure 8. The control circuit 120 adds an additional read stage RD8 only to the selected programming loop PGMLOOP8 to read the threshold voltage of adjacent word lines (e.g., word line WLn-1). Figure 8 also shows the waveform of the unselected word line Unsel-WL for comparison. The programmed voltage VPGM and through voltage VPASSR shown in Figure 8 can be defined according to the actual design and application. The bit line BL8 shown in Figure 8 can be a bit line of the non-volatile memory 100, such as bit lines BL1, BLn, or BLm.

[0034] In the programming phase PGM8 of the selected programming loop PGMLOOP8, the control circuit 120 programs multiple memory cells of the current word line WLn. In the read phase RD8 of the selected programming loop PGMLOOP8, the control circuit 120 checks / reads the critical voltage of the adjacent word line WLn-1 adjacent to the current word line WLn. In the programming verification phase PV8 of the selected programming loop PGMLOOP8 and subsequent programming loops, the control circuit 120 adjusts the programming verification voltage used to verify the current word line WLn based on the critical voltage (check result) of the adjacent word line WLn-1. In other programming loops after the selected programming loop PGMLOOP8, the control circuit 120 does not need to read the critical voltage of the adjacent word line WLn-1 again.

[0035] When the threshold voltage of the adjacent word line WLn-1 is determined to be low, the control circuit 120 selects a high verification voltage as the programmed verification voltage for the current word line WLn. Then, the control circuit 120 uses the high verification voltage to verify the memory cell of the current word line WLn. Conversely, when the threshold voltage of the adjacent word line WLn-1 is determined to be high, the control circuit 120 selects a low verification voltage as the programmed verification voltage for the current word line WLn. Then, the control circuit 120 uses the low verification voltage to verify the memory cell of the current word line.

[0036] For example, each of the programmed verification voltages AV to GV has a high voltage level (the original voltage level) and a low voltage level (a lower voltage level). In response to the threshold voltage of the adjacent word line WLn-1 being determined to be low, the control circuit 120 selects the high voltage level of the programmed verification voltages corresponding to the unverified potential states S1 to S7 (e.g., the programmed verification voltages EV, FV, and GV shown in Figure 8). Conversely, in response to the threshold voltage of the adjacent word line WLn-1 being determined to be high, the control circuit 120 selects the low voltage level of the unverified programmed verification voltages EV, FV, and GV.

[0037] Figure 9 is a waveform diagram of word lines and bit lines according to another embodiment of the present invention. During programming, control circuit 120 programs the memory cell of the current word line (e.g., word line WLn) using PGMPD9. Programming during PGMPD9 includes multiple programming loops. Each programming loop includes a programming stage (e.g., programming stage PGM9 shown in Figure 9) and a programming verification stage (e.g., programming verification stage PV9 shown in Figure 9). Control circuit 120 selects one of these programming loops as the selected programming loop, such as programming loop PGMLOOP9 shown in Figure 9. The programming verification stage PV9 of the selected programming loop PGMLOOP9 includes a read period RDP9 and a programming verification period PVP9. Control circuit 120 adds an additional read period RDP9 only to the programming verification stage PV9 of the selected programming loop PGMLOOP9 to read the threshold voltage of the adjacent word line (e.g., word line WLn-1). Figure 9 also shows the waveform of the unselected word line Unsel-WL for comparison. The programmed voltage VPGM and through voltage VPASSR shown in Figure 9 can be defined according to the actual design and application. The bit line BL9 shown in Figure 9 can be a bit line of the non-volatile memory 100, such as bit lines BL1, BLn, or BLm.

[0038] In the programming phase PGM9 of the selected programming loop PGMLOOP9, the control circuit 120 programs multiple memory cells of the current word line WLn. During the read phase RDP9 of the programming verification phase PV9 of the selected programming loop PGMLOOP9, the control circuit 120 checks / reads the critical voltage of the adjacent word line WLn-1 adjacent to the current word line WLn. During the programming verification phase PVP9 of the programming verification phase PV9 of the selected programming loop PGMLOOP9, and during the programming verification phases of other programming loops following the selected programming loop PGMLOOP9, the control circuit 120 can adjust the programming verification voltage used to verify the current word line WLn based on the critical voltage (check result) of the adjacent word line WLn-1. In other programming loops following the selected programming loop PGMLOOP9, the control circuit 120 does not need to read the critical voltage of the adjacent word line WLn-1 again.

[0039] When the threshold voltage of the adjacent word line WLn-1 is determined to be low, the control circuit 120 selects a high verification voltage as the programmed verification voltage for the current word line WLn. Then, the control circuit 120 uses the high verification voltage to verify the memory cell of the current word line WLn. Conversely, when the threshold voltage of the adjacent word line WLn-1 is determined to be high, the control circuit 120 selects a low verification voltage as the programmed verification voltage for the current word line WLn. Then, the control circuit 120 uses the low verification voltage to verify the memory cell of the current word line. For example, when the threshold voltage of the adjacent word line WLn-1 is determined to be low, the control circuit 120 selects the higher voltage level (original voltage level) of the programmed verification voltages corresponding to the potential states S1~S7 that have not yet passed verification (e.g., the programmed verification voltages EV, FV, and GV shown in Figure 8). Conversely, if the threshold voltage of the adjacent character line WLn-1 is judged to be high, the control circuit 120 selects the lower voltage level (lower voltage level) of the programmed verification voltages EV, FV and GV, which have not yet been verified.

[0040] Figure 10 is a flowchart of a programming method for a non-volatile memory according to another embodiment of the present invention. The programming method described in Figure 10 can be implemented using the non-volatile memory 100 of Figure 1. The programming method described in Figure 10 can be applied to memory devices of different memory cell types, such as multilevel memory (MLC), three-level memory (TLC), or four-level memory (QLC). Steps S1010, S1020, S1030, and S1080 shown in Figure 10 can be deduced from the relevant descriptions of steps S710, S720, S730, and S770 shown in Figure 7, and will not be repeated here. Compared to the embodiment shown in Figure 7, the embodiment shown in Figure 10 determines the programming verification voltage of the current word line (e.g., word line WLn) based on the critical voltages of multiple adjacent word lines (e.g., WLn-1 and WLn+1).

[0041] Referring to Figures 1 and 10, in a selected programming loop among multiple programming loops during programming, control circuit 120 programs multiple memory cells of the current word line (e.g., word line WLn) (step S1010). In the selected programming loop that programs multiple memory cells of the current word line, control circuit 120 reads the threshold voltages of multiple adjacent word lines (e.g., WLn-1 and WLn+1) adjacent to the current word line (step S1020). In step S1030, control circuit 120 checks the threshold voltages of adjacent word lines WLn-1 and WLn+1. For example, control circuit 120 compares the threshold voltage of adjacent word line WLn-1, the threshold voltage of adjacent word line WLn+1, and a threshold to generate a check result. The threshold can be defined according to the actual design and application. For example, the threshold can be the reference voltage Vref shown in Figure 3. Based on practical design and application, the reference voltage Vref can be any voltage between S0 and S7.

[0042] If the threshold voltage of the adjacent character line WLn-1 is less than a threshold, and the threshold voltage of the adjacent character line WLn+1 is less than a threshold (the judgment result of step S1040 is "the threshold voltages of both adjacent character lines are low"), then the control circuit 120 sets the programmed verification voltage of the current character line WLn to the first verification voltage level (the first verification voltage level is greater than the second and third verification voltage levels) (step S1050). For example, the control circuit 120 selects a high verification voltage as the programmed verification voltage of the current character line WLn. Then, the control circuit 120 uses the high programmed verification voltage selected in step S1050 to verify the memory cell of the current character line WLn (step S1080).

[0043] If the critical voltage of the adjacent character line WLn-1 is less than a threshold, and the critical voltage of the adjacent character line WLn+1 is greater than a threshold (the judgment result of step S1040 is "the critical voltages of the two adjacent character lines are one high and one low"), then the control circuit 120 sets the programmed verification voltage of the current character line WLn to the second verification voltage level (the second verification voltage level is less than the first verification voltage level and greater than the third verification voltage level) (step S1060). For example, the control circuit 120 selects an intermediate verification voltage as the programmed verification voltage of the current character line WLn. Then, the control circuit 120 uses the intermediate programmed verification voltage selected in step S760 to verify the memory cell of the current character line WLn (step S1080).

[0044] If the critical voltage of the adjacent character line WLn-1 is greater than the threshold, and the critical voltage of the adjacent character line WLn+1 is less than the threshold (the judgment result of step S1040 is "the critical voltages of the two adjacent character lines are one high and one low"), then the control circuit 120 sets the programmed verification voltage of the current character line WLn to the second verification voltage level (step S1060).

[0045] If the threshold voltage of the adjacent character line WLn-1 is greater than a threshold, and the threshold voltage of the adjacent character line WLn+1 is also greater than a threshold (the judgment result of step S1040 is "the threshold voltages of both adjacent character lines are high"), then the control circuit 120 sets the programmed verification voltage of the current character line WLn to the third verification voltage level (the third verification voltage level is lower than the first verification voltage level and the second verification voltage level) (step S1070). For example, the control circuit 120 selects a low verification voltage as the programmed verification voltage of the current character line WLn. Then, the control circuit 120 uses the low programmed verification voltage selected in step S760 to verify the memory cell of the current character line WLn (step S1080).

[0046] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0047] 100: Non-volatile memory 101, 102, 103, 200: Memory cell string 110: Memory Cell Array 120: Control Circuit 210: Channel Column Structure 211: Dielectric core 212: Channel Layer 213: Tunneling Layer 214: Charge trapping layer 215: Barrier Layer AV, BV, CV, DV, EV, FV, GV: Programmed Verification Voltages BL1, BL8, BL9, BLm, BLn: Bit lines CSL: Common Source Pole Line GSL: Grounding Selection Line M, M': Memory cells PD31, PD32, PD33, PD34, PD35, PD36, PD37, PD41, PD41H, PD41L, PD42, PD42H, PD42L, PD43, PD43H, PD43L, PD44, PD44H, PD44L, PD45, PD45H, PD45L, PD46, PD46H, PD46L, PD47, PD47H, PD47L, PD61, PD61H, PD61L, PD62, PD62H, PD62L, PD63, PD63H, PD63L, PD64, PD64H, PD64L, PD65, PD65H, PD65L, PD66, PD66H, PD66L, PD67, PD67H, PD67L: Critical Voltage Distribution Curve PGM8, PGM9: Programming Stage PGMLOOP8, PGMLOOP9: Select the programmatic loop PGMPD8, PGMPD9: Programming Period PV8, PV9: Programmatic Verification Phase PVP9: During procedural verification RD8: Reading Phase RDP9: During Reading S0: Erasure state S1, S2, S3, S4, S5, S6, S7: Potential states S510, S520, S530, S710, S720, S730, S740, S750, S760, S770, S1010, S1020, S1030, S1040, S1050, S1060, S1070, S1080: Steps SSL0, SSL1, SSL2, SSL3: Serial select lines Sub0, Sub1, Sub2, Sub3: Sub-blocks Unsel-WL: Unselected character line VPASSR: Through voltage VPGM: Programmed Voltage Vref: Reference voltage WL1, WLi, WLi+1, WLn-1, WLn, WLm: Character lines X, Y, Z: Direction

Claims

1. A non-volatile memory, comprising: A memory cell array having a plurality of memory cells, wherein each of a plurality of word lines is coupled to a plurality of memory cells in a corresponding column of the memory cells, and each of a plurality of bit lines is coupled to a plurality of memory cells in a corresponding row of the memory cells. A control circuit coupled to the memory cell array, wherein, during a programming process of multiple memory cells programming a current character line among the character lines, the control circuit reads at least one critical voltage of at least one adjacent character line adjacent to the current character line; the control circuit checks the at least one critical voltage of the at least one adjacent character line to generate a check result; based on the check result, the control circuit adjusts a programming verification voltage used to verify the current character line during the programming process; the programming process includes multiple programming loops; the control circuit reads the at least one critical voltage of the at least one adjacent character line in a selected programming loop among the programming loops; and in the selected programming loop, and in other programming loops after the selected programming loop, the control circuit adjusts the programming verification voltage used to verify the current character line based on the check result.

2. The non-volatile memory as claimed in claim 1, wherein during the programming period, the control circuit reads the at least one threshold voltage of the at least one adjacent word line only in the selected programming cycle.

3. The non-volatile memory as claimed in claim 1, wherein the selected programming cycle includes a programming phase, a read phase, and a programming verification phase, wherein the control circuit programs the memory cells of the current character line in the programming phase, the control circuit reads the at least one threshold voltage of the at least one adjacent character line in the read phase, and the control circuit adjusts the programming verification voltage used to verify the current character line based on the check result in the programming verification phase.

4. The non-volatile memory as claimed in claim 1, wherein the selected programming cycle includes a programming phase and a programming verification phase, the programming verification phase including a read period and a programming verification period, the control circuit programming the memory cells of the current character line in the programming phase, the control circuit reading the at least one threshold voltage of the at least one adjacent character line in the read period of the programming verification phase, and the control circuit adjusting the programming verification voltage used to verify the current character line based on the check result in the programming verification period of the programming verification phase.

5. The non-volatile memory as claimed in claim 1, wherein the at least one adjacent word line includes a first adjacent word line, the control circuit compares a first threshold voltage of the first adjacent word line with a threshold to generate the check result; in response to the first threshold voltage being less than the threshold, the control circuit sets the programmed verification voltage used to verify the current word line to a first verification voltage level; and in response to the first threshold voltage being greater than the threshold, the control circuit sets the programmed verification voltage used to verify the current word line to a second verification voltage level less than the first verification voltage level.

6. The non-volatile memory as claimed in claim 1, wherein the at least one adjacent word line includes a first adjacent word line and a second adjacent word line, the control circuit compares a first threshold voltage of the first adjacent word line, a second threshold voltage of the second adjacent word line, and a threshold to generate the check result; in response to the first threshold voltage being less than the threshold and in response to the second threshold voltage being less than the threshold, the control circuit sets the programmed verification voltage used to verify the current word line to a first verification voltage level; in response to the first threshold voltage being less than the threshold and in response to the second threshold voltage being greater than the threshold, the control circuit sets the programmed verification voltage used to verify the current word line to a second verification voltage level lower than the first verification voltage level; In response to the first threshold voltage being greater than the threshold and in response to the second threshold voltage being less than the threshold, the control circuit sets the programmed verification voltage used to verify the current character line to the second verification voltage level; and in response to the first threshold voltage being greater than the threshold and in response to the second threshold voltage being greater than the threshold, the control circuit sets the programmed verification voltage used to verify the current character line to a third verification voltage level that is less than the second verification voltage level.

7. A programming method applicable to a non-volatile memory, the programming method comprising: During a programming process that programs a plurality of first memory cells of a current character line, at least one threshold voltage of at least one adjacent character line is read; the at least one threshold voltage of the at least one adjacent character line is checked to generate a check result; based on the check result, a programming verification voltage used to verify the current character line during the programming process is adjusted, wherein the programming process includes a plurality of programming loops; in a selected programming loop of the programming loops, the at least one threshold voltage of the at least one adjacent character line is read; and in the selected programming loop and in other programming loops following the selected programming loop, the programming verification voltage used to verify the current character line is adjusted based on the check result.

8. The programming method as described in claim 7, wherein during the programming period, the at least one critical voltage of the at least one adjacent word line is read only in the selected programming cycle.

9. The programming method as described in claim 7, wherein the selected programming loop includes a programming phase, a reading phase, and a programming verification phase, the programming method further comprising: In this programming phase, these memory cells of the current character line are programmed; In the read phase, the at least one critical voltage of the at least one adjacent character line is read; and in the programmable verification phase, the programmable verification voltage used to verify the current character line is adjusted based on the check result.

10. The programming method as described in claim 7, wherein the selected programming loop includes a programming phase and a programming verification phase, the programming verification phase including a read period and a programming verification period, the programming method further including: The programmable phase programs the memory cells of the current character line; the programmable verification phase reads the at least one critical voltage of the at least one adjacent character line during the read phase; and the programmable verification phase adjusts the programmable verification voltage used to verify the current character line based on the check result during the programmable verification phase.

11. The programming method as described in claim 7, wherein the at least one adjacent character line includes a first adjacent character line, the programming method further comprising: The check result is generated by comparing a first threshold voltage of the first adjacent character line with a threshold; in response to the first threshold voltage being less than the threshold, the programmed verification voltage used to verify the current character line is set to a first verification voltage level; and in response to the first threshold voltage being greater than the threshold, the programmed verification voltage used to verify the current character line is set to a second verification voltage level less than the first verification voltage level.

12. The programming method as described in claim 7, wherein the at least one neighboring character line includes a first neighboring character line and a second neighboring character line, the programming method further comprising: The check result is generated by comparing a first threshold voltage of the first adjacent character line, a second threshold voltage of the second adjacent character line, and a threshold. In response to the first threshold voltage being less than the threshold and the second threshold voltage being less than the threshold, the programmed verification voltage used to verify the current character line is set to a first verification voltage level. In response to the first threshold voltage being less than the threshold and the second threshold voltage being greater than the threshold, the programmed verification voltage used to verify the current character line is set to a second verification voltage level lower than the first verification voltage level. In response to the first threshold voltage being greater than the threshold and the second threshold voltage being less than the threshold, the programmed verification voltage used to verify the current character line is set to the second verification voltage level. And in response to the first threshold voltage being greater than the threshold and the second threshold voltage being greater than the threshold, the programmed verification voltage used to verify the current character line is set to a third verification voltage level lower than the second verification voltage level.

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