Semiconductor memory devices

Abstract

According to an embodiment, in a semiconductor memory device, a first select gate line is connected to the gate of a first select transistor and the gate of a third select transistor. A second select gate line is connected to the gate of a second select transistor and the gate of a fourth select transistor. A plurality of word lines correspond to a plurality of first memory cell transistors. A plurality of word lines correspond to a plurality of second memory cell transistors. The plurality of word lines are respectively connected to the gate of the corresponding first memory cell transistor and the gate of the corresponding second memory cell transistor. The states of the first select transistor, the second select transistor, the third select transistor, and the fourth select transistor can be set between three or more levels.

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