Capacitance design and method of forming the same

Abstract

A capacitor design and method of forming thereof are provided. The capacitor design includes: a substrate, including a silicon nitride layer, a first silicon oxide layer, a silicon layer and a second silicon oxide layer from top to bottom along the vertical direction; an opening in the silicon nitride layer, the first silicon oxide layer, the silicon layer and the second silicon oxide layer; and an insulator-shape capacitor conformally on a surface of the opening. The opening includes a trench in the silicon nitride layer, the first silicon oxide layer, the silicon layer and the second silicon oxide layer along the vertical direction; and a first toroidal cavity and a second toroidal cavity respectively in the first silicon oxide layer and the second silicon oxide layer along a horizontal direction perpendicular to the vertical direction from the trench.

Description

Technical Field

[0001] This invention relates to a capacitor design, and more particularly to a capacitor design and a method of forming the same. Prior Technology

[0002] As semiconductor manufacturing processes strive for higher density, capacitors also require higher capacitance values ​​within the same layout area. This has led to the development of various capacitor manufacturing technologies, such as deep trench capacitors (DTC).

[0003] However, there is still room for improvement in the capacitance value of these capacitor components. Summary of the Invention

[0004] To address the aforementioned problems, this invention proposes a capacitor design and its formation method to improve capacitance value.

[0005] An embodiment of the present invention provides a capacitor design, comprising: a substrate comprising, from top to bottom along a vertical direction, a silicon nitride layer, a first silicon oxide layer, a silicon layer, and a second silicon oxide layer; an opening located in the silicon nitride layer, the first silicon oxide layer, the silicon layer, and the second silicon oxide layer, wherein the opening comprises: a trench located in the silicon nitride layer, the second silicon oxide layer, the silicon layer, and the first silicon oxide layer along a vertical direction; a first annular cavity and a second annular cavity located in the first silicon oxide layer and the second silicon oxide layer respectively from the trench along a horizontal direction perpendicular to the vertical direction; and an insulator-shaped capacitor conformally located on the surface of the opening.

[0006] In some embodiments, the substrate further includes an etch stop layer located below the second silicon oxide layer.

[0007] In some embodiments, the bottom of the opening exposes an etch stop layer.

[0008] In some embodiments, the insulator capacitor includes: a lower electrode layer conformally located on the surface of the opening; a dielectric layer conformally located on the lower electrode layer; and an upper electrode layer conformally located on the dielectric layer.

[0009] In some embodiments, the insulator capacitor comprises a stacked structure of metal / dielectric layer / metal.

[0010] In some embodiments, the insulator capacitor comprises a TiN-ZAZ-TiN stacked structure or a TAN / ZAZ / TAN stacked structure.

[0011] In some embodiments, the invention further includes: an insulator-shaped capacitor located on the top surface of the silicon nitride layer; and a lower electrode and an upper electrode located on the insulator-shaped capacitor of the silicon nitride layer, wherein the lower electrode is electrically connected to the lower electrode layer and the upper electrode is electrically connected to the upper electrode layer.

[0012] In some embodiments, the system further includes: an additional silicon oxide layer and an additional silicon nitride layer, located between the first silicon oxide layer and the silicon layer; wherein the opening is also located in the additional silicon oxide layer and the additional silicon nitride layer, wherein the opening includes: a trench, located in the additional silicon nitride layer and the additional silicon oxide layer in a vertical direction; and a third annular cavity, located in the trench in a horizontal direction in the additional silicon oxide layer.

[0013] An embodiment of the present invention provides a method for forming a capacitor design, comprising: providing a substrate comprising, from top to bottom along a vertical direction, a silicon nitride layer, a first silicon oxide layer, a silicon layer, and a second silicon oxide layer; forming an opening in the silicon nitride layer, the first silicon oxide layer, the silicon layer, and the second silicon oxide layer, wherein forming the opening comprises: forming a trench along a vertical direction in the silicon nitride layer, the first silicon oxide layer, the silicon layer, and the second silicon oxide layer; removing a portion of the first silicon oxide layer and a portion of the second silicon oxide layer from the trench along a horizontal direction perpendicular to the vertical direction to form a first annular cavity and a second annular cavity in the first silicon oxide layer and the second silicon oxide layer, respectively; and conformally forming an insulator-shaped capacitor on the surface of the opening.

[0014] In some embodiments, the substrate further includes an etch stop layer located below the second silicon oxide layer.

[0015] In some embodiments, the bottom of the opening exposes an etch stop layer.

[0016] In some embodiments, forming the first annular cavity and the second annular cavity includes an isotropic etching process or an anisotropic etching process.

[0017] In some embodiments, forming the first annular cavity and the second annular cavity includes forming them simultaneously using an isotropic etching process or an anisotropic etching process.

[0018] In some embodiments, forming an insulator-shaped capacitor includes: conformally forming a lower electrode layer on the surface of an opening; conformally forming a dielectric layer on the lower electrode layer; and conformally forming an upper electrode layer on an insulating layer.

[0019] In some embodiments, the insulator capacitor comprises a stacked structure of metal / dielectric layer / metal.

[0020] In some embodiments, the insulator capacitor comprises a TiN-ZAZ-TiN stacked structure or a TAN / ZAZ / TAN stacked structure.

[0021] In some embodiments, the method further includes: forming an insulator-shaped capacitor on the top surface of the silicon nitride layer; and forming a lower electrode and an upper electrode on the insulator-shaped capacitor of the silicon nitride layer, wherein the lower electrode is electrically connected to the lower electrode layer and the upper electrode is electrically connected to the upper electrode layer.

[0022] In some embodiments, the method further includes: forming an additional silicon nitride layer and an additional silicon oxide layer between the first silicon oxide layer and the silicon layer, and wherein an opening is formed in the additional silicon nitride layer and the additional silicon oxide layer, wherein forming the opening includes: forming a trench in the additional silicon nitride layer and the additional silicon oxide layer in a vertical direction; and removing a portion of the additional silicon oxide layer in a horizontal direction from the trench to form a third annular cavity in the additional silicon oxide layer.

[0023] In some embodiments, forming the first annular cavity, the second annular cavity, and the third annular cavity includes an isotropic etching process or an isotropic etching process.

[0024] In some embodiments, forming the first annular cavity, the second annular cavity, and the third annular cavity includes forming them simultaneously using an isotropic etching process or an anisotropic etching process.

[0025] Based on the above, the present invention provides a capacitor design and its formation method. By utilizing the characteristic that different material layers inside the trench have a relatively large etch selectivity, several annular cavities are formed by further lateral expansion in a special material inside the trench through etching. This gives the subsequently formed capacitor an insulator-like shape, thereby increasing the surface area of ​​the capacitor under the same layout area or the same trench aspect ratio, and thus increasing the capacitance value of the capacitor while maintaining the stacking density of the semiconductor device.

[0026] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0027] Figures 1A to 1E are schematic cross-sectional views of the method for forming a capacitor design according to Embodiment 1 of the present invention. Figure 2 is a cross-sectional schematic diagram of the capacitor design according to Embodiment 2 of the present invention. Figures 3A and 3B are cross-sectional schematic diagrams of the method for forming a multi-wafer stacked structure according to Embodiment 3 of the present invention. Implementation

[0028] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. Furthermore, the drawings are for illustrative purposes only and are not drawn to their original dimensions. For ease of understanding, the same elements will be labeled with the same symbols, and will not be repeated in the following paragraphs.

[0029] The terms "contains," "includes," and "has" used in the text are all open-ended, meaning they "include but are not limited to."

[0030] Furthermore, directional terms used in this document, such as "up," "down," "top," and "bottom," are merely for reference in the illustrations and are not intended to limit the invention. Therefore, it should be understood that "up" and "down" can be used interchangeably, as can "top" and "bottom"; and when a layer or film is placed "on" another element, the element can be placed directly on the other element, or there may be an intermediate element. Conversely, when an element is said to be placed "directly" on another element, there is no intermediate element between them.

[0031] As used herein, “about,” “approximately,” or “substantially” includes the average of the mentioned value and a specific value that can be determined by someone of ordinary skill in the art, within an acceptable range of deviations, taking into account the measurement under discussion and a specific number of errors associated with the measurement (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the use of “about,” “approximately,” or “substantially” herein may be chosen based on the optical, etched, or other properties to select a more acceptable range of deviations or standard deviations, and may not require a single standard deviation to apply to all properties.

[0032] The terminology used herein is for illustrative purposes only and is not intended to limit the scope of this disclosure. In this context, the singular form includes the plural form unless the context otherwise requires.

[0033] The various formation steps described below include deposition processes, removal processes, and patterning processes.

[0034] The deposition process refers to the process of forming one material onto another material, which may include, but is not limited to, techniques such as spin coating, sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PE-CVD), atomic layer deposition (ALD), molecular beam deposition (MBD), pulsed laser deposition (PLD), and liquid source misted chemical deposition (LSMCD).

[0035] The removal process may include wet etching, dry etching, chemical mechanical planarization (CMP), etc., but is not limited to these.

[0036] The patterning process may include steps such as coating photoresist according to the desired pattern, then exposing the photoresist to react, then exposing and developing the photoresist to pattern it, then using etching to transfer the shape of the photoresist onto the material, removing the material and photoresist to be removed, and finally cleaning, but is not limited to these steps.

[0037] For the capacitor design, multi-wafer stacking structure and its formation method of the present invention, please refer to the following Examples 1 to 3, and refer to Figures 1A to 3B for further understanding.

[0038] [Example] [1]

[0039] Figures 1A to 1E are schematic cross-sectional views of the method for forming a capacitor design according to Embodiment 1 of the present invention.

[0040] First, referring to Figure 1A, a substrate S is provided, which includes a silicon nitride layer 10, a first silicon oxide layer 20, a silicon layer 30 and a second silicon oxide layer 40 from top to bottom along the vertical direction Z.

[0041] In some embodiments, the silicon nitride layer 10 may include materials such as silicon oxynitride, but is not limited thereto.

[0042] In some embodiments, the first silicon oxide layer 20 may include materials such as tetraethoxysilane (TEOS), but is not limited thereto.

[0043] In some embodiments, the silicon layer 30 may include, but is not limited to, a silicon material.

[0044] In some embodiments, the second silicon oxide layer 40 may include materials such as silicon oxide fillers that form STI, but is not limited thereto.

[0045] In some embodiments, the substrate S may further include an etch stop layer 50 below the second silicon oxide layer 40, as shown in FIG1A.

[0046] In some embodiments, the substrate S may further include an etch stop layer 50, an interlayer dielectric layer 60 and a metal layer 70 below the second silicon oxide layer 40, wherein the etch stop layer 50 may be located on the interlayer dielectric layer 60, as shown in FIG1A, or the etch stop layer 50 may be located in the interlayer dielectric layer 60 (not shown).

[0047] In some embodiments, the etch stop layer 50 may include materials such as silicon nitride, but is not limited thereto.

[0048] In some embodiments, the metal layer 70 may include various conductive materials, such as copper (Cu), tungsten (W), aluminum (Al), titanium (Ti), nickel (Ni), platinum (Pt), ruthenium (Ru), cobalt (Co), or alloys thereof, or other suitable and future conductive materials, but not limited thereto.

[0049] Then, referring to Figure 1A, trenches 100 are formed along the vertical direction Z in the silicon nitride layer 10, the first silicon oxide layer 20, the silicon layer 30 and the second silicon oxide layer 40.

[0050] In some embodiments, various patterning processes may be used, such as photolithography and etching processes, to form the trench 100.

[0051] In some embodiments, the bottom 100B of the formed trench 100 may expose a second silicon oxide layer 40, as shown in FIG1A; or, the bottom 100B of the formed trench 100 may expose an etch stop layer 50 (not shown).

[0052] Next, referring to FIG1B, after forming the above-mentioned trench 100, a portion of the first silicon oxide layer 20 and a portion of the second silicon oxide layer 40 are removed from the trench 100 along the horizontal direction X perpendicular to the vertical direction Z, so as to form a first annular cavity 102 and a second annular cavity 104 in the first silicon oxide layer 20 and the second silicon oxide layer 40, respectively, so that the opening 110 includes the trench 100, the first annular cavity 102 and the second annular cavity 104, and this opening 110 is formed in the silicon nitride layer 10, the first silicon oxide layer 20, the silicon layer 30 and the second silicon oxide layer 40.

[0053] In some embodiments, an isotropic etching process or anisotropic etching process can be used to remove a portion of the first silicon oxide layer 20 and a portion of the second silicon oxide layer 40 from the trench 100 along the horizontal direction X perpendicular to the vertical direction Z, so as to form a first annular cavity 102 and a second annular cavity 104, respectively.

[0054] In some embodiments, forming the first annular cavity 102 and the second annular cavity 104 may include forming them simultaneously using an isotropic etching process or an anisotropic etching process.

[0055] Since the first silicon oxide layer 20, silicon layer 30 and second silicon oxide layer 40 have an etch selectivity difference of about 100 to 1000:1 relative to the silicon oxide layer 10 and silicon layer 30, after etching the trench 100 with an appropriate etchant and etching method, the first silicon oxide layer 20 and second silicon oxide layer 40 in the trench 100 will be removed to a certain extent, while the silicon oxide layer 10 and silicon layer 30 will be retained, so that the first annular cavity 102 and the second annular cavity 104 are formed in the first silicon oxide layer 20 and the second silicon oxide layer 40 respectively along the horizontal direction X perpendicular to the vertical direction Z.

[0056] Furthermore, as shown in Figures 1A and 1B, the bottom 100B of the trench 100 may also be affected by the etching of the second annular cavity 104, causing the second silicon oxide layer 40 to be removed further downwards. Finally, the bottom 110B of the formed opening 110 moves towards the etching stop layer 50 compared to the bottom 100B of the trench 100, and may even expose the etching stop layer 50, as shown in Figure 1B.

[0057] Next, referring to FIG1C, an insulator capacitor 200 is conformally formed on the surface of the opening 110 including the first annular cavity 102 and the second annular cavity 104.

[0058] In some embodiments, before the insulator capacitor 200 is conformally formed on the surface of the opening 110 including the first annular cavity 102 and the second annular cavity 104, a liner (not shown) may be conformally formed on the surface of the opening 110 including the first annular cavity 102 and the second annular cavity 104. This liner may include, but is not limited to, an oxide layer.

[0059] The aforementioned insulator refers to an insulator used in overhead transmission lines for electrical insulation and mechanical fixing, which has a special shape with umbrella-shaped insulators repeatedly arranged in the same direction on a columnar insulator. The insulator-shaped capacitor 200 of the present invention conformally forms along the surface of the opening 110 including the groove 100, the first annular cavity 102 and the second annular cavity 104, and has a similar shape to the insulator, hence the name.

[0060] In some embodiments, the aforementioned insulator capacitor 200 may include a metal / insulator / metal (MIM) stacked structure, such as a TiN-ZAZ-TiN stacked structure or a TAN / ZAZ / TAN stacked structure, but is not limited thereto; the insulator capacitor 200 may also include a general capacitor structure, but is not limited thereto.

[0061] In some embodiments, the aforementioned insulator capacitor 200 may include: conformally forming a lower electrode layer 210 on the surface of the opening 110; conformally forming a dielectric layer 220 on the lower electrode layer 210; and conformally forming an upper electrode layer 230 on the dielectric layer 220, as shown in FIG1C.

[0062] In some embodiments, as shown in FIG1C, the aforementioned barrier capacitor 200 may be further formed on the top surface of the silicon nitride layer 10.

[0063] Then, as shown in Figure 1D, an insulating layer 300 is deposited on the insulator capacitor 200 to fill the opening 110 and is located above the silicon nitride layer 10.

[0064] Next, as shown in FIG1E, a lower electrode 410 and an upper electrode 430 are formed on the barrier capacitor 200 of the silicon nitride layer 10, wherein the lower electrode 410 is electrically connected to the lower electrode layer 210 and the upper electrode 430 is electrically connected to the upper electrode layer 230.

[0065] In other words, this invention utilizes the characteristic that different material layers inside the trench have a relatively large etch selectivity to further expand laterally in a special material inside the trench by etching, thereby forming several annular cavities. This gives the capacitor formed subsequently an insulator-like shape, increasing the surface area of ​​the capacitor while maintaining the same layout area or trench aspect ratio, and thus increasing the capacitance value while maintaining the stacking density of the semiconductor device.

[0066] [Example] [2]

[0067] Figure 2 is a cross-sectional schematic diagram of the capacitor design according to Embodiment 2 of the present invention, which is similar to the capacitor design shown in Figure 1E of Embodiment 1. The method of forming the capacitor design in Embodiment 2 is similar to the method of forming the capacitor design in Embodiment 1. Therefore, the following only describes the differences.

[0068] As shown in Figure 2, the capacitor design, for example, the capacitor design shown in Figure 1E, has an additional silicon nitride layer 12 and an additional silicon oxide layer 22 between the first silicon oxide layer 20 and the silicon layer 30. Therefore, the trench 100 of the capacitor design in Example 2 is formed along the vertical direction Z in the silicon nitride layer 10, the first silicon oxide layer 20, the additional silicon nitride layer 12, the additional silicon oxide layer 22, the silicon layer 30 and the second silicon oxide layer 40.

[0069] Please continue referring to Figure 2. After forming the trench 100, a portion of the first silicon oxide layer 20, a portion of the additional silicon oxide layer 22, and a portion of the second silicon oxide layer 40 are removed from the trench 100 along the horizontal direction X, which is perpendicular to the vertical direction Z, to form a first annular cavity 102, a third annular cavity 106, and a second annular cavity 104 in the first silicon oxide layer 20, the additional silicon oxide layer 22, and the second silicon oxide layer 40, respectively. The opening 120 includes the trench 100, the first annular cavity 102, the third annular cavity 106, and the second annular cavity 104, and this opening 120 is formed in the silicon nitride layer 10, the first silicon oxide layer 20, the additional silicon nitride layer 12, the additional silicon oxide layer 22, the silicon layer 30, and the second silicon oxide layer 40.

[0070] In some embodiments, an isotropic etching process or anisotropic etching process can be used to remove a portion of the first silicon oxide layer 20, a portion of the additional silicon oxide layer 22, and a portion of the second silicon oxide layer 40 from the trench 100 along the horizontal direction X perpendicular to the vertical direction Z, so as to form a first annular cavity 102, a third annular cavity 106, and a second annular cavity 104, respectively.

[0071] In some embodiments, forming the first annular cavity 102, the third annular cavity 106, and the second annular cavity 104 may include forming them simultaneously using an isotropic etching process or an anisotropic etching process.

[0072] Next, referring to Figure 2 again, an insulator capacitor 200 is conformally formed on the surface of the opening 120 including the first annular cavity 102, the third annular cavity 106 and the second annular cavity 104.

[0073] Please refer to both the capacitor design in Figure 1E and the capacitor design in Figure 2. Since an additional silicon nitride layer 12 and an additional silicon oxide layer 22 are added between the first silicon oxide layer 20 and the silicon layer 30 in Embodiment 2, after the formation steps of the opening 120 and the insulator capacitor 200, a larger surface area of ​​the insulator capacitor 200 than that in Embodiment 1 is obtained, thus achieving a higher capacitance value in the capacitor design of Embodiment 2.

[0074] Therefore, the concept of the capacitor design formation method in Example 2 can be used to form an array of silicon oxide layers and silicon nitride layers, so that the opening forms a shape including several annular cavities, thereby increasing the capacitance of the capacitor subsequently formed.

[0075] [Example] [3]

[0076] Figures 3A and 3B are schematic cross-sectional views of a method for forming a multi-wafer stacked structure according to Embodiment 3 of the present invention. This multi-wafer stacked structure and its formation method incorporate the capacitor design from Embodiment 1 into the multi-wafer stacked structure. However, the concept of the present invention is not limited to this; the capacitor design from Embodiment 2 and similar capacitor designs formed using this concept can also be incorporated into the multi-wafer stacked structure. Furthermore, the multi-wafer stacked structures in Figures 3A and 3B are merely examples to clearly illustrate various multi-wafer stacked structures, and the application of the capacitor design of the present invention is not limited to this.

[0077] First, referring to Figure 3A, a bottom wafer structure 600 is provided, including a bottom wafer 610; a top wafer structure 700 is provided, including a top wafer 710 and a top dielectric layer 730; the top wafer structure 700 and the bottom wafer structure 600 are joined in the vertical direction Z such that the top wafer 710 and the bottom wafer 610 are far apart from each other.

[0078] In some embodiments, the bottom wafer structure 600 further includes a bottom element 620 and a bottom dielectric layer 630 on the bottom wafer 610, a bottom first interlayer dielectric layer 640 and a bottom contact plug 650 on the bottom element 620 and the bottom dielectric layer 630, and a stack of a bottom first metal layer 660 and a bottom second interlayer dielectric layer 670 sequentially on the bottom first interlayer dielectric layer 640 and the bottom contact plug 650, as shown in FIG3A, but is not limited thereto.

[0079] In some embodiments, the top wafer structure 700 further includes a top element 720 and a top dielectric layer 730 on the top wafer 710, an etch stop layer 735 on the top element 720 and the top dielectric layer 735, a top first interlayer dielectric layer 740 and a top contact plug 750 on the etch stop layer 735, and a stack of a top first metal layer 760 and a top second interlayer dielectric layer 770 sequentially on the top first interlayer dielectric layer 740 and the top contact plug 750, as shown in FIG3A, but is not limited thereto.

[0080] In some embodiments, the top wafer structure 700 and the bottom wafer structure 600 are joined at the bonding interface BL along the vertical direction Z with the top wafer 710 and the bottom wafer 610 being far apart from each other, as shown in FIG3A, but not limited thereto.

[0081] In some embodiments, through silicon vias (TSVs) 800 are also located in the bottom wafer structure 600 and the top wafer structure 700, as shown in FIG3A, but are not limited thereto.

[0082] Next, as shown in Figure 3B, after chemical mechanical polishing (CMP) grinding to reduce the thickness of the top wafer 710 to about 3 to 10 micrometers, a side insulating layer 900 is formed on the exposed upper surface of the bottom wafer 610 and the sidewalls of the top wafer structure 700 and the bottom wafer structure 600, as shown in Figure 3B.

[0083] In some embodiments, the side insulation layer 900 may include an insulating material such as TEOS, but is not limited thereto.

[0084] Next, a first silicon oxide layer 20 is formed on the top wafer 710; then a silicon nitride layer 10 is formed on the first silicon oxide layer 20.

[0085] Next, following the formation steps of the capacitor design in Example 1 as shown in Figures 1A-1E, the top wafer structure 700, the bottom wafer structure 600 in Figure 3B, and the second silicon oxide layer 40 and silicon nitride layer 10 formed subsequently on the top wafer 710 are considered as the substrate S described in Example 1. In particular, the silicon nitride layer 10, the first silicon oxide layer 20, the top wafer 710, and the top dielectric layer 730 in Figure 3B are considered to correspond to the silicon nitride layer 10, the first silicon oxide layer 20, the silicon layer 30, and the second silicon oxide layer 40 in Figures 1A-1E. The opening 110 is formed with the silicon nitride layer 10 and the first silicon oxide layer 40. In layer 20, top wafer 710 and top dielectric layer 730, forming opening 110 includes: forming trench 100 along the vertical direction Z in silicon nitride layer 10, first silicon oxide layer 20, top wafer 710 and top dielectric layer 730; removing a portion of first silicon oxide layer 20 and a portion of top dielectric layer 730 from trench 100 along horizontal direction X perpendicular to vertical direction Z to form first annular cavity 102 and second annular cavity 104 in first silicon oxide layer 20 and top dielectric layer 730 respectively; and conformally forming barrier capacitor 200 on the surface of opening 110.

[0086] In addition to corresponding the silicon nitride layer 10, the first silicon oxide layer 20, the top wafer 710, and the top dielectric layer 730 in Figure 3B to the silicon nitride layer 10, the first silicon oxide layer 20, the silicon layer 30, and the second silicon oxide layer 40 in Figures 1A-1E, in some embodiments, the etch stop layer 735, the top first interlayer dielectric layer 740, and the top first metal layer 760 in Figures 3A and 3B can also correspond to the etch stop layer 50, the interlayer dielectric layer 60, and the metal layer 70 in Figures 1A-1E.

[0087] Then, the formation of the multi-wafer stacked structure of Embodiment 3 can be completed using the capacitor design formation method of Embodiment 1 of the present invention.

[0088] As described above, the present invention provides a capacitor design and its formation method. By utilizing the characteristic that different material layers inside the trench have a relatively large etch selectivity, several annular cavities are formed by further lateral expansion in a special material inside the trench through etching. This gives the subsequently formed capacitor an insulator-like shape, thereby increasing the surface area of ​​the capacitor while maintaining the same layout area or the same trench aspect ratio, and thus increasing the capacitance value of the capacitor while maintaining the integration density of the semiconductor device.

[0089] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0090] 10: Silicon nitride layer 12: Additional silicon nitride layer 20: First silicon oxide layer 22: Additional silicon oxide layer 30: Silicon layer 40: Second silicon oxide layer 50, 735: Etching stop layer 60: Interlayer dielectric layer 70: Metal layer 100: Trench 100B, 110B, 120B: Bottom 102: First annular cavity 104: Second annular cavity 106: Third annular cavity 110, 120: Opening 200: Insulator capacitor 210: Lower electrode layer 220: Dielectric layer 230: Upper electrode layer 300: Insulation layer 410: Lower electrode 430: Upper electrode 600: Bottom wafer structure 610: Bottom wafer 620: Bottom Component 630: Bottom dielectric layer 640: Bottom first interlayer dielectric layer 650: Bottom contact plug 660: Bottom First Metal Layer 670: Bottom second interlayer dielectric layer 700: Top wafer structure 710: Top wafer 720: Top Component 730: Top Dielectric Layer 740: Top first interlayer dielectric layer 750: Top contact plug 760: Top First Metal Layer 770: Top second interlayer dielectric layer 800:Through silicon via 900: Side insulation layer BL: Interface S:Substrate X: Horizontal direction Z: Vertical direction

Claims

1. A capacitor design, comprising: A substrate, comprising, from top to bottom in a vertical direction, a silicon nitride layer, a first silicon oxide layer, a silicon layer, a second silicon oxide layer, and an etch stop layer; an opening located in the silicon nitride layer, the first silicon oxide layer, the silicon layer, and the second silicon oxide layer, wherein the opening includes: a trench located in the silicon nitride layer, the second silicon oxide layer, the silicon layer, and the first silicon oxide layer in the vertical direction; The first annular cavity and the second annular cavity are located in the first silicon oxide layer and the second silicon oxide layer respectively from the trench along a horizontal direction perpendicular to the vertical direction; and the insulator-shaped capacitor is conformally located on the surface of the opening.

2. The capacitor design as described in claim 1, wherein the bottom of the opening exposes the etch stop layer.

3. The capacitor design as claimed in claim 1, wherein the insulator capacitor comprises: a lower electrode layer conformally disposed on the surface of the opening; a dielectric layer conformally disposed on the lower electrode layer; and an upper electrode layer conformally disposed on the dielectric layer.

4. The capacitor design as described in claim 1, wherein the insulator capacitor comprises a stacked structure of metal / dielectric layer / metal.

5. The capacitor design as claimed in claim 1, wherein the insulator capacitor comprises a TiN-ZAZ-TiN stacked structure or a TAN / ZAZ / TAN stacked structure.

6. The capacitor design as claimed in claim 3 further includes: the insulator-shaped capacitor located on the top surface of the silicon nitride layer; and a lower electrode and an upper electrode located on the insulator-shaped capacitor of the silicon nitride layer, wherein the lower electrode is electrically connected to the lower electrode layer and wherein the upper electrode is electrically connected to the upper electrode layer.

7. The capacitor design as claimed in claim 1 further includes: an additional silicon oxide layer and an additional silicon nitride layer, located between the first silicon oxide layer and the silicon layer; wherein the opening is further located in the additional silicon oxide layer and the additional silicon nitride layer, wherein the opening includes: the trench, located in the additional silicon nitride layer and the additional silicon oxide layer along the vertical direction; and a third annular cavity located in the trench in the additional silicon oxide layer in the horizontal direction.

8. A method for forming a capacitor design, comprising: A substrate is provided, comprising, from top to bottom in a vertical direction, a silicon nitride layer, a first silicon oxide layer, a silicon layer, a second silicon oxide layer, and an etch stop layer; an opening is formed in the silicon nitride layer, the first silicon oxide layer, the silicon layer, and the second silicon oxide layer, wherein forming the opening includes: forming a trench in the silicon nitride layer, the first silicon oxide layer, the silicon layer, and the second silicon oxide layer along the vertical direction; and removing a portion of the first silicon oxide layer and a portion of the second silicon oxide layer from the trench in a horizontal direction perpendicular to the vertical direction to form a first annular cavity and a second annular cavity in the first silicon oxide layer and the second silicon oxide layer, respectively; And conformally form an insulator-shaped capacitor on the surface of the opening.

9. A method of forming a capacitor design as described in claim 8, wherein the bottom of the opening exposes the etch stop layer.

10. A method of forming a capacitor design as claimed in claim 8, wherein forming the first annular cavity and the second annular cavity includes an isotropic etching process or an anisotropic etching process.

11. A method of forming a capacitor design as claimed in claim 8, wherein forming the first annular cavity and the second annular cavity comprises forming them simultaneously using an isotropic etching process or an anisotropic etching process.

12. A method of forming a capacitor design as described in claim 8, wherein forming the insulator-shaped capacitor includes: conformally forming a lower electrode layer on the surface of the opening; conformally forming a dielectric layer on the lower electrode layer; and conformally forming an upper electrode layer on the dielectric layer.

13. A method of forming a capacitor design as described in claim 8, wherein the insulator capacitor comprises a stacked structure of metal / dielectric layer / metal.

14. A method of forming a capacitor design as described in claim 8, wherein the insulator capacitor comprises a TiN-ZAZ-TiN stacked structure or a TAN / ZAZ / TAN stacked structure.

15. The method of forming a capacitor design as claimed in claim 12, further comprising: forming the insulator-shaped capacitor on the top surface of the silicon nitride layer; and forming a lower electrode and an upper electrode on the insulator-shaped capacitor of the silicon nitride layer, wherein the lower electrode is electrically connected to the lower electrode layer and wherein the upper electrode is electrically connected to the upper electrode layer.

16. The method of forming a capacitor design as claimed in claim 8, further comprising: forming an additional silicon nitride layer and an additional silicon oxide layer between a first silicon oxide layer and the silicon layer, and wherein forming the opening is further comprising: forming a trench in the additional silicon nitride layer and the additional silicon oxide layer along the vertical direction; and removing a portion of the additional silicon oxide layer from the trench along the horizontal direction to form a third annular cavity in the additional silicon oxide layer.

17. A method of forming a capacitor design as claimed in claim 16, wherein forming the first annular cavity, the second annular cavity, and the third annular cavity comprises an isotropic etching process or an anisotropic etching process.

18. The method of forming a capacitor design as claimed in claim 14, wherein forming the first annular cavity, the second annular cavity, and the third annular cavity comprises forming them simultaneously using an isotropic etching process or an anisotropic etching process.

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