Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate, an active layer, a gate electrode, a source electrode, a drain electrode, and a heat dissipation structure. The substrate has a top surface and a bottom surface opposite the top surface. The substrate includes a first base portion and a plurality of first protruding portions disposed on the first base portion. The active layer is disposed on the top surface of the substrate. The gate electrode is disposed on the active layer. The source electrode and the drain electrode are respectively disposed on the active layer and respectively disposed on opposite sides of the gate electrode. The heat dissipation structure is disposed on the bottom surface of the substrate, and is disposed on the first base portion and the plurality of first protruding portions.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more particularly to semiconductor devices including heat dissipation structures. Prior Technology

[0002] Gallium nitride (GaN) materials are widely used due to their wide bandgap and strong polarization effect. For example, GaN semiconductors are currently widely used in power devices, such as high electron mobility transistors (HEMTs) with heterojunction structures.

[0003] However, high-electron-mobility transistors may exhibit problems such as excessive thermal resistance, leading to insufficient heat dissipation, excessive operating temperature, and / or an increase in on-resistance as thermal resistance rises. Therefore, although existing semiconductor devices have gradually met their intended applications, they are not yet completely satisfactory in all aspects. Consequently, some issues regarding semiconductor devices still need to be overcome. Summary of the Invention

[0004] The semiconductor device disclosed herein may include a heat dissipation structure, and the heat dissipation structure and the active layer may be respectively disposed on opposite surfaces of a substrate to reduce the thermal resistance of the semiconductor device. Specifically, when the thermal resistance of a semiconductor device is too high, the operating temperature will increase accordingly, leading to an increase in both on-resistance and heat loss. Furthermore, as the operating temperature increases, the thermal resistance will further increase, thereby exacerbating the increase in on-resistance and heat loss. Therefore, reducing thermal resistance based on a heat dissipation structure can prevent the semiconductor device from falling into the aforementioned vicious cycle, improving heat dissipation efficiency, reducing operating temperature, and / or reducing on-resistance, thereby giving the semiconductor device improved electrical properties and / or reliability. For example, this disclosure allows for adjustments to the shape, density, material, and electrical connection method of the heat dissipation structure to reduce the thermal resistance of the semiconductor device.

[0005] In some embodiments, a semiconductor device is provided. The semiconductor device includes a substrate, an active layer, a gate electrode, a source electrode, a drain electrode, and a heat dissipation structure. The substrate has a top surface and a bottom surface, with the bottom surface opposite to the top surface. The substrate includes a first base and a plurality of first protrusions, wherein the plurality of first protrusions are disposed on the first base. The active layer is disposed on the top surface of the substrate. The gate electrode is disposed on the active layer. The source electrode and drain electrode are respectively disposed on the active layer and respectively disposed on opposite sides of the gate electrode. The heat dissipation structure is disposed on the bottom surface of the substrate and is disposed on the first base and the plurality of first protrusions.

[0006] The semiconductor device disclosed herein can be applied to various types of semiconductor devices. To make the components and advantages of this disclosure more apparent and understandable, various embodiments are described below in detail with reference to the accompanying drawings. Simple Explanation of the Diagram

[0007] This disclosure will be more fully understood when read in conjunction with the drawings, from the following detailed description. It is worth noting that, in accordance with industry standard practice, the components are not drawn to scale. In fact, for clarity, the dimensions of the components may be arbitrarily enlarged or reduced. Figure 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Figure 2 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Figure 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Figures 4 and 5 are respectively a cross-sectional view and a top view of a semiconductor device according to an embodiment of the present disclosure. Figures 6 and 7 are a cross-sectional view and a top view of a semiconductor device according to an embodiment of the present disclosure, respectively. Figure 8 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Figure 9 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Figure 10 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Implementation

[0008] The semiconductor devices of various embodiments of this disclosure are described in detail below. It should be understood that the following description provides many different embodiments for implementing various forms of some embodiments of this disclosure. The specific elements and arrangements described below are merely for simple and clear description of some embodiments of this disclosure. Of course, these are only examples and not limitations of this disclosure. Furthermore, similar and / or corresponding element symbols may be used in different embodiments to identify similar and / or corresponding elements for clear description of this disclosure. However, the use of these similar and / or corresponding element symbols is only for simple and clear description of some embodiments of this disclosure and does not represent any relationship between the different embodiments and / or structures discussed.

[0009] It should be understood that relative terms, such as "lower," "bottom," "higher," or "top," may be used in various embodiments to describe the relative relationship of one element to another in the diagram. It is understood that if the arrangement in the diagram is flipped so that it is upside down, an element depicted on the "lower" side will become an element on the "higher" side. The embodiments disclosed herein should be understood in conjunction with the drawings, which are also considered part of the disclosure.

[0010] Furthermore, when it is stated that a first material layer is on or over a second material layer, this may include situations where the first and second material layers are in direct contact, or situations where the first and second material layers are not in direct contact, meaning that there may be one or more other material layers between the first and second material layers. However, if the first material layer is directly on the second material layer, it indicates that the first and second material layers are in direct contact.

[0011] Furthermore, it should be understood that the ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify elements, are not intended to imply any prior ordinal number for that (or those) element, nor to indicate the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another with the same name. The claims and specification may not use the same terminology; for example, the first element in the specification may be the second element in the claims.

[0012] In some embodiments disclosed herein, terms such as "connect," "interconnect," and "bond," unless specifically defined, may refer to two structures being in direct contact, or to two structures not being in direct contact, with other structures disposed between them. Furthermore, these terms may include situations where both structures are movable or both are fixed. Additionally, the terms "electrical connection" or "electrical coupling" include any direct or indirect electrical connection means.

[0013] In this text, the terms "approximately," "about," and "substantially" typically indicate a range within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. The given quantity is an approximate quantity; that is, even without specific mention of "approximately," "about," or "substantially," the meaning of "approximately," "about," or "substantially" is implied. The phrases "range between the first value and the second value" or "first value ~ second value" indicate that the range includes the first value, the second value, and other values ​​in between. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies an error between the first and second values ​​that may be within approximately 10%, 5%, 3%, 2%, 1%, or 0.5%.

[0014] Throughout this disclosure and in the claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements that function identically but have different names. In the following description and claims, the terms "comprise," "containing," and "having" are open-ended terms and should therefore be interpreted as "containing but not limited to...". Thus, when the terms "comprise," "containing," and / or "having" are used in the description of this disclosure, they specify the presence of the corresponding component, area, step, operation, and / or element, but do not exclude the presence of one or more of the corresponding component, area, step, operation, and / or element.

[0015] It should be understood that, without departing from the spirit of this disclosure, components in multiple different embodiments can be replaced, reorganized, or combined to complete other embodiments. Components in each embodiment can be arbitrarily combined and used as long as they do not violate the spirit of the invention or conflict with it.

[0016] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It is understood that these terms, for example, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0017] In this disclosure, the directions are not limited to the three axes of a Cartesian coordinate system such as the X-axis, Y-axis, and Z-axis, and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For ease of explanation, in the following text, the X-axis direction is the first direction D1 (width direction), the Y-axis direction is the second direction D2 (length direction), and the Z-axis direction is the third direction D3 (thickness direction). In some embodiments, the cross-sectional view described herein is a schematic diagram of the XZ plane (the plane formed by the first direction D1 and the third direction D3), and the top view described herein is a schematic diagram of the XY plane (the plane formed by the first direction D1 and the second direction D2).

[0018] Referring to Figure 1, which is a schematic cross-sectional view of a semiconductor device 1 according to an embodiment of the present disclosure. As shown in Figure 1, in some embodiments, a substrate 100 may be provided. In some embodiments, the substrate 100 may include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like. The SOI substrate includes a semiconductor layer formed on an insulator. For example, the insulating layer may include silicon oxide, silicon nitride, polycrystalline silicon, or combinations thereof, and the semiconductor substrate may include silicon, aluminum nitride (AlN), or the like. In some embodiments, the substrate 100 may be an undoped or doped substrate, such as a substrate doped with p-type or n-type dopants. In some embodiments, the substrate 100 may include a multilayer substrate or a gradient substrate. In some embodiments, the substrate 100 may include a semiconductor substrate or a ceramic substrate, such as a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, an aluminum nitride substrate, or a sapphire substrate. In some embodiments, the substrate 100 may be a silicon substrate.

[0019] As shown in Figure 1, in some embodiments, on the third direction D3, the substrate 100 may have a top surface 100TS and a bottom surface 100BS, with the top surface 100TS relative to the bottom surface 100BS. In some embodiments, on the third direction D3, the substrate 100 may have a thickness 100t, and the thickness 100t may be greater than or equal to 100 μm. For example, the thickness 100t may be 100 μm, 150 μm, 200 μm, 250 μm or greater, but this disclosure is not limited thereto.

[0020] As shown in Figure 1, in some embodiments, an etching process can be performed on the bottom surface 100BS of the substrate 100 to remove a portion of the substrate 100 and form a plurality of trenches 130 on the bottom surface 100BS. In other words, since the bottom surface 100BS of the substrate 100 can be referred to as the back surface, back surface etching can be performed on the substrate 100 to form microstructures such as trenches 130 on the back surface. In some embodiments, the top surface 100TS of the substrate 100 can be a flat surface, and the bottom surface 100BS of the substrate 100 can be an uneven surface.

[0021] As shown in Figure 1, in some embodiments, the substrate 100 may include a first base 110 and a plurality of first protrusions 120 disposed on the first base 110. Each of the plurality of first protrusions 120 may be staggered with each of the plurality of grooves 130. In some embodiments, the plurality of first protrusions 120 may be spaced apart on the first base 110 in a first direction D1. In some embodiments, the plurality of first protrusions 120 may extend toward a direction away from the top surface 100TS of the substrate 100. In some embodiments, the number of first protrusions 120 may be greater than or equal to 3. For example, the number of first protrusions 120 may be 3, 4, 5, 6, 7, 8, 9, 10, 20, 30 or greater. Accordingly, the first protrusions 120 of the substrate 100 may serve as first heat dissipation fins to increase the contact area and reduce thermal resistance.

[0022] As shown in Figure 1, in some embodiments, the first protrusion 120 may be an equilateral triangle, an inverted triangle, a rectangle, a regular trapezoid, an inverted trapezoid, an island shape, a bullet shape, a teardrop shape, or other suitable shapes. In some embodiments, on the third direction D3, the first base 110 may have a thickness 110t, and the thickness 110t may be greater than or equal to 50 μm. For example, the thickness 110t may be 50 μm, 100 μm, 150 μm, 200 μm, or greater, but this disclosure is not limited thereto. In some embodiments, the ratio of the thickness 110t of the first base 110 to the thickness 100t of the substrate 100 (thickness 110t / thickness 100t) may be greater than or equal to 0.4. For example, the ratio may be 0.4, 0.45, 0.5, 0.55, 0.6, or greater, but this disclosure is not limited thereto. In some embodiments, on the third-direction D3, the first protrusion 120 may have a thickness of 120t, and the thickness 120t may be greater than or equal to 50 μm. For example, the thickness 120t may be 50 μm, 100 μm, 150 μm, 200 μm or greater, but this disclosure is not limited thereto. Accordingly, the profile of the substrate can be adjusted by adjusting the shape and size of the first protrusion 120, thereby reducing thermal resistance while maintaining the structural strength of the substrate 100.

[0023] As shown in Figure 1, in some embodiments, an active layer 200 may be formed on the top surface 100TS of the substrate 100. In some embodiments, the active layer 200 may include multiple layers. In some embodiments, the active layer 200 may include a channel layer and a barrier layer, and the active layer 200 may further include a nucleation layer, a buffer layer, or other functional layers.

[0024] As shown in Figure 1, in some embodiments, a buffer layer 210 may be formed on the top surface 100TS of the substrate 100 to improve the compatibility between the substrate 100 and other components disposed on the substrate 100, such as reducing differences in thermal expansion coefficients and / or reducing differences in lattice constants. In some embodiments, the buffer layer 210 may include a III-V compound semiconductor material, such as a group III nitride. For example, the buffer layer 210 may include gallium nitride, aluminum nitride, aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), the like, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the buffer layer 210 may be formed by a deposition process. For example, the deposition process may be chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), similar processes, or combinations thereof, but this disclosure is not limited thereto.

[0025] In some embodiments, a nucleation layer may be further disposed between the substrate 100 and the buffer layer 210 to reduce the lattice difference between the substrate 100 and other layers disposed on the substrate 100, thereby improving epitaxial quality and reliability. In some embodiments, the nucleation layer may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), the like or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the nucleation layer may be formed by a deposition process. In other embodiments, the nucleation layer may be omitted.

[0026] As shown in Figure 1, in some embodiments, a channel layer 220 may be formed on the buffer layer 210. In some embodiments, the channel layer 220 may include a III-V compound semiconductor material, such as a group III nitride, but this disclosure is not limited thereto. For example, the channel layer 220 may include gallium nitride, aluminum gallium nitride, indium aluminum nitride, indium gallium nitride (InGaN), indium aluminum gallium nitride (InAlGaN), the likes thereof, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the channel layer 220 may be gallium nitride. In some embodiments, the channel layer 220 may be formed by a deposition process.

[0027] As shown in Figure 1, in some embodiments, a barrier layer 230 may be formed on the channel layer 220. In some embodiments, the barrier layer 230 may include a III-V compound semiconductor material, such as a III-nitride, but this disclosure is not limited thereto. For example, the barrier layer may include aluminum nitride, aluminum gallium nitride, aluminum indium nitride, indium aluminum gallium nitride, the like, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the barrier layer 230 may be aluminum gallium nitride. In some embodiments, the barrier layer 230 may be formed by a deposition process. Due to the heterogeneous interface between the channel layer 220 and the barrier layer 230, and the difference in lattice constant between the channel layer 220 and the barrier layer 230, a two-dimensional electron gas (2DEG) 222 may be formed near the top surface of the channel layer 220 and serve as a current path.

[0028] As shown in Figure 1, in some embodiments, a gate electrode 240 may be formed on the active layer 200 to make the semiconductor device 1 normally on. In some embodiments, a source electrode 250 and a drain electrode 260 may be formed on the active layer 200, and the source electrode 250 and the drain electrode 260 may be respectively disposed on opposite sides of the gate electrode 240. In some embodiments, the gate electrode 240, the source electrode 250, and the drain electrode 260 may each comprise a conductive material. In some embodiments, the conductive material may comprise a metal, an alloy, a conductive metal nitride, a conductive metal oxide, a semiconductor material, the like, or a combination thereof, but this disclosure is not limited thereto. In some embodiments, the metal may comprise gold (Au), silver (Ag), nickel (Ni), titanium (Ti), platinum (Pt), palladium (Pd), iridium (Ir), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), the like, or a combination thereof. In some embodiments, the conductive metal nitride may comprise titanium nitride (TiN), tantalum nitride (TaN), the like, or a combination thereof. In some embodiments, the conductive metal oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), the like, or combinations thereof. In some embodiments, the semiconductor material may include polycrystalline silicon or polycrystalline germanium, the like, or combinations thereof. In some embodiments, the conductive material may be formed by chemical vapor deposition, sputtering, resistance heating evaporation, electron beam evaporation, similar processes, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, a plurality of first protrusions 120 of the substrate 100 may be located below the gate electrode 240, the source electrode 250, and the drain electrode 260, and may be located between the source electrode 250 and the drain electrode 260. Accordingly, the plurality of first protrusions 120 of the substrate 100 may reduce thermal resistance in the region between the source electrode 250 and the drain electrode 260.

[0029] As shown in Figure 1, in some embodiments, a heat dissipation structure 300 may be formed on the bottom surface 100BS of the substrate 100 to obtain the semiconductor device 1. In some embodiments, the substrate 100 may be located between the gate electrode 240 and the heat dissipation structure 300. That is, in the third direction D3, the heat dissipation structure 300 may be located below the substrate 100. In some embodiments, the heat dissipation structure 300 may be formed by chemical vapor deposition, sputtering, resistance heating evaporation, electron beam evaporation, similar processes, or combinations thereof. In some embodiments, the heat dissipation structure 300 may include a heat dissipation material. In some embodiments, the heat dissipation material may include metals, alloys, conductive metal nitrides, conductive metal oxides, the like, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the heat dissipation structure 300 may include gold (Au), silver (Ag), nickel (Ni), titanium (Ti), or alloys thereof. In some embodiments, the heat dissipation structure 300 may be grounded, connected to a base, or located at the lowest potential. In some embodiments, the heat dissipation structure 300 may include a single layer or multiple layers.

[0030] As shown in Figure 1, in some embodiments, the heat dissipation structure 300 may have a top surface 300TS and a bottom surface 300BS opposite to each other, and the top surface 300TS of the heat dissipation structure 300 may contact the bottom surface 100BS of the substrate 100. In some embodiments, the heat dissipation structure 300 may be disposed on a first base 110 and a plurality of first protrusions 120 of the substrate 100, and may directly contact the first base 110 and the plurality of first protrusions 120. In some embodiments, the top surface 300TS of the heat dissipation structure 300 may be a surface with unevenness, and the bottom surface 300BS of the heat dissipation structure 300 may be a flat surface (e.g., semiconductor devices 1-5) or a surface with unevenness (e.g., semiconductor devices 6-8).

[0031] As shown in Figure 1, in some embodiments, the heat dissipation structure 300 may include a second base 310 and a plurality of second protrusions 320 disposed on the second base 310. Each of the plurality of second protrusions 320 may be staggered with each of the plurality of first protrusions 120. In some embodiments, in a first direction D1, the plurality of second protrusions 320 may be spaced apart on the second base 310. In some embodiments, the plurality of second protrusions 320 may extend toward the top surface 100TS of the substrate 100. In some embodiments, the number of second protrusions 320 may correspond to the number of first protrusions 120. In some embodiments, the number of second protrusions 320 may be greater than or equal to 3. For example, the number of second protrusions 320 may be 3, 4, 5, 6, 7, 8, 9, 10, 20, 30 or greater, but this disclosure is not limited thereto. Accordingly, the second protrusions 320 of the heat dissipation structure 300 may serve as second heat dissipation fins to increase the contact area and reduce thermal resistance.

[0032] As shown in Figure 1, in some embodiments, the shape of the second protrusion 320 may correspond to the shape of the first protrusion 120. In some embodiments, the second base 310 on the third direction D3 may have a thickness 310t, and the thickness 310t may be greater than or equal to 1 μm. For example, the thickness 310t may be 1 μm, 2 μm, 2.5 μm, 5 μm, 10 μm or greater, but this disclosure is not limited thereto. In some embodiments, the second protrusion 320 on the third direction D3 may have a thickness 320t, and the thickness 320t of the second protrusion 320 may be substantially the same as the thickness 120t of the first protrusion 120. Accordingly, the profile of the heat dissipation structure can be adjusted by adjusting the shape and size of the second protrusion to reduce thermal resistance.

[0033] In the following text, the same or similar component symbols and descriptions may be omitted.

[0034] Referring to Figure 2, which is a schematic cross-sectional view of a semiconductor device 2 according to an embodiment of the present disclosure. In some embodiments, in the semiconductor device 2, the first spacing p1 between a plurality of second protrusions 320 between the gate electrode 240 and the source electrode 250 may be greater than the second spacing p2 between a plurality of second protrusions 320 between the gate electrode 240 and the drain electrode 260. That is, the density (number / fixed area) of the second protrusions 320 located in the first region R1 may be less than the density between the second protrusions 320 located in the second region R2, wherein the first region R1 may correspond to the gate-to-source (GS) region, and the second region R2 may correspond to the gate-to-drain (GD) region. In some embodiments, the ratio of the first spacing p1 to the second spacing p2 (first spacing p1 / second spacing p2) may be greater than or equal to 1.2, but the present disclosure is not limited thereto. For example, the ratio may be 1.2, 1.5, 1.8, 2, 3, 4, 5 or greater, but the present disclosure is not limited thereto. In some embodiments, the first spacing p1 between the plurality of first protrusions 120 between the gate electrode 240 and the source electrode 250 may be greater than the second spacing p2 between the plurality of first protrusions 120 between the gate electrode 240 and the drain electrode 260. That is, the density of the first protrusions 120 in the first region R1 may be less than the density of the first protrusions 120 in the second region R2.

[0035] Accordingly, by providing protrusions with different spacing or density in different regions of the semiconductor device, the thermal resistance of different regions can be adjusted separately to reduce thermal resistance while maintaining structural strength, reliability, process margin, and process cost. Specifically, since the drain electrode 260 can be connected to a high potential, the operating temperature of the second region R2 between the gate electrode 240 and the drain electrode 260 is typically higher than that of the first region R1 between the gate electrode 240 and the source electrode 250. Therefore, this disclosure can reduce the spacing (or increase the number or density) of the second protrusions 320 provided in the second region R2 to further reduce thermal resistance at relatively high temperatures in the semiconductor device.

[0036] Referring to Figure 3, which is a schematic cross-sectional view of a semiconductor device 3 according to an embodiment of the present disclosure. In some embodiments, in the semiconductor device 3, the heat dissipation structure 300 may include a first metal layer 301, a second metal layer 302, and a third metal layer 303. In some embodiments, the first metal layer 301 may be compliantly disposed on a first base 110 and a plurality of first protrusions 120, the second metal layer 302 may be compliantly disposed on the first metal layer 301, and the third metal layer 303 may be blanket-distributed on the second metal layer 302. In some embodiments, the first metal layer 301 may serve as a buffer layer between the substrate 100 and the second metal layer 302, and the second metal layer 302 may serve as a buffer layer between the first metal layer 301 and the third metal layer 303. In some embodiments, the first metal layer 301 may be Ti, the second metal layer 302 may be Ni, and the third metal layer 303 may be Ag or Au. In other embodiments, the first metal layer 301 and / or the second metal layer 302 may be omitted. In some embodiments, the ratio of the thickness of the first metal layer 301 to the thickness of the second metal layer 302 (thickness of the first metal layer 301 / thickness of the second metal layer 302) may be greater than or equal to 0.7, but this disclosure is not limited thereto. In some embodiments, the ratio of the thickness of the first metal layer 301 to the thickness of the third metal layer 303 (thickness of the first metal layer 301 / thickness of the third metal layer 303) may be greater than or equal to 0.01, but this disclosure is not limited thereto. Accordingly, thermal resistance can be reduced by adjusting the composition of the heat dissipation structure.

[0037] Referring to Figures 4 and 5, which are respectively a cross-sectional view and a top view of a semiconductor device 4 according to an embodiment of the present disclosure, Figure 4 shows a cross-sectional view taken along line segment A-A' in Figure 5. As shown in Figure 4, in some embodiments, a source via 252 may be formed in the semiconductor device 4 before the gate electrode 240, source electrode 250, and drain electrode 260 are formed. In some embodiments, the material and formation method of the source via 252 may be the same as or different from that of the source electrode 250. In some embodiments, the source via 252 may penetrate the substrate 100 and the active layer 200, and the source via 252 may connect the source electrode 250 and the heat dissipation structure 300. In some embodiments, since the heat dissipation structure 300 is grounded and the source electrode 250 is connected to the heat dissipation structure 300, the source electrode 250 may be grounded. In some embodiments, since the drain electrode 260 may be connected to a high potential, the drain electrode 260 is electrically isolated from the heat dissipation structure 300.

[0038] As shown in Figure 5, in some embodiments, in a top view, there may be a plurality of source vias 252, and the plurality of source vias 252 may be connected together to the connection portion 254. For example, source vias 252a and 252b may both be connected to the same side of the connection portion 254. In some embodiments, the material and forming method of the connection portion 254 may be the same as or different from that of the source electrode 250. In some embodiments, the connection portion 254 may be formed in the same process as the source vias 252. In some embodiments, in a top view, the extending direction of the source vias 252 (e.g., a second direction D2) may be different from the extending direction of the connection portion 254 (e.g., a first direction D1). For example, in a top view, the extending direction of the source vias 252 may be perpendicular to the extending direction of the connection portion 254. In some embodiments, in a top view, the gate electrode 240 may surround the source vias 252. In some embodiments, in a top view, the gate electrode 240 may surround at least three sides of the connection portion 254. Accordingly, since a plurality of source vias 252 are connected together to the connection portion 254, the volume and contact area of ​​the heat dissipation material can be increased to further reduce thermal resistance.

[0039] Referring to Figures 6 and 7, which are respectively a cross-sectional view and a top view of a semiconductor device 5 according to an embodiment of the present disclosure. Figure 6 shows a cross-sectional view taken along line segment A-A' in Figure 7. As shown in Figure 6, in some embodiments, a gate via 242 may be formed in the semiconductor device 5 before the gate electrode 240, source electrode 250, and drain electrode 260 are formed. In some embodiments, the material and formation method of the gate via 242 may be the same as or different from that of the gate electrode 240. In some embodiments, the gate via 242 may penetrate the substrate but not the active layer 200 (as shown in Figure 6, the gate via 242 is only a dashed line), and the gate via 242 may connect the gate electrode 240 and the heat dissipation structure 300. Accordingly, since the gate via 242 electrically connects the gate electrode 240 to the heat dissipation structure 300, the gate electrode 240 can be grounded. Therefore, the semiconductor device 5 is more suitable for use in cascode elements. In detail, the semiconductor device 5 can be a high electron mobility transistor, so when the gate electrode 240 of the high electron mobility transistor is grounded, the wiring to connect the gate electrode 240 to the source electrode of other transistors can be omitted.

[0040] As shown in Figure 7, in some embodiments, the gate via 242 may be spaced apart from the active layer 200 in the top view. In some embodiments, in the top view, the projection range of the gate via 242 onto the substrate 100 does not overlap with the projection range of the active layer 200 onto the substrate 100. This avoids short circuits between the gate via 242 and the active layer 200. Furthermore, since the gate electrode 240 has a larger number of hot carriers during semiconductor device operation, its temperature is higher than that of the source electrode 250. Therefore, improving the heat dissipation efficiency of the gate electrode 240 can more significantly improve the overall heat dissipation efficiency of the semiconductor device than improving the heat dissipation efficiency of the source electrode 250.

[0041] Referring to Figures 8 through 10, which are schematic cross-sectional views of semiconductor devices 6-8 according to an embodiment of the present disclosure. As shown in Figures 8 through 10, in some embodiments, a heat dissipation structure 300 may be conformally disposed on the bottom surface 100BS of a substrate 100. In some embodiments, a first metal layer 301 may be compliantly disposed on a first base 110 and a plurality of first protrusions 120, a second metal layer 302 may be compliantly disposed on the first metal layer 301, and a third metal layer 303 may be compliantly disposed on the second metal layer 302. In some embodiments, the heat dissipation structure 300 may have a thickness 300t on the third direction D3, and the thickness 300t may be greater than or equal to 1 μm. For example, the thickness 300t may be 1 μm, 2 μm, 2.5 μm, 5 μm, 10 μm or greater, but the present disclosure is not limited thereto. Accordingly, thermal resistance can be reduced while maintaining structural strength, reliability, process margin, and process cost.

[0042] In some embodiments, the semiconductor devices 1-8 disclosed herein can be used in any combination and can serve as high electron mobility transistors. In other embodiments, any of the semiconductor devices 1-8 can be further processed to form a high electron mobility transistor.

[0043] The semiconductor device disclosed herein includes a heat dissipation structure disposed on the back side of a substrate to reduce the thermal resistance of the semiconductor device, thereby improving heat dissipation efficiency, reducing operating temperature, and / or reducing on-resistance. Thus, the semiconductor device disclosed herein can have improved electrical properties and / or reliability. For example, the heat dissipation structure may include a plurality of protrusions disposed on the substrate to increase the surface area of ​​the heat dissipation structure, thereby reducing the thermal resistance of the semiconductor device. For example, the plurality of protrusions may have different densities in different regions of the semiconductor device to correspond to different heat dissipation efficiencies in different regions. For example, the heat dissipation structure may be electrically connected to the source electrode, so that the source electrode and the heat dissipation structure dissipate heat together, thereby further reducing the thermal resistance of the semiconductor device. For example, the heat dissipation structure may be electrically connected to the gate electrode to facilitate application in cascode components and eliminate the need for additional wiring to the gate electrode. Furthermore, the present disclosure allows for adjustment of the source via arrangement to further reduce the thermal resistance of the semiconductor device. The present disclosure also allows for adjustment of the gate via arrangement to prevent the gate via from interfering with the switching of the semiconductor device.

[0044] The scope of protection of this disclosure is not limited to the processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps described in the specific embodiments of the specification. Any process, machine, manufacturing method, material composition, apparatus, method, and step that is currently or will be developed can be understood from the content of this disclosure, and can be used according to this disclosure as long as it can perform substantially the same function or obtain substantially the same result in the embodiments described herein. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps. No embodiment or claim of this disclosure needs to achieve all the purposes, advantages, and / or features described in this disclosure.

[0045] The above outlines several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments disclosed herein. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments disclosed herein to achieve the same purpose and / or advantages as the embodiments herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of this disclosure.

[0046] 1, 2, 3, 4, 5, 6, 7, 8: Semiconductor devices 100:Substrate 100BS, 300BS: Bottom surface 100TS, 300TS: Top surface 100t, 110t, 120t, 300t, 310t, 320t: Thickness 110: First base 120: First convex part 130: Trench 200: Active Layer 210: Buffer layer 220: Channel Layer 222: Two-dimensional electron gas 230: Barrier Layer 240: Gate electrode 242: Gate via 250: Source electrode 252, 252a, 252b: Source vias 254: Connecting part 260: Drain electrode 300: Heat dissipation structure 301: First metal layer 302: Second metal layer 303: Third metal layer 310: Second base 320: Second convex part A-A': Line segment D1: First Direction D2: Second Direction D3: Third direction p1: First spacing p2: Second spacing R1: First Region R2: Second Region

Claims

1. A semiconductor device, comprising: A substrate has a top surface and a bottom surface opposite the top surface, and includes: a first base; and a plurality of first protrusions disposed on the first base; an active layer disposed on the top surface of the substrate; a gate electrode disposed on the active layer; a source electrode and a drain electrode respectively disposed on the active layer and respectively disposed on opposite sides of the gate electrode; and a heat dissipation structure disposed on the bottom surface of the substrate and on the first base and the plurality of first protrusions, wherein the heat dissipation structure further includes: a second base; and a plurality of second protrusions disposed on the second base, wherein the plurality of second protrusions of the heat dissipation structure are alternately disposed with the plurality of first protrusions of the substrate, wherein a first spacing between the plurality of second protrusions between the gate electrode and the source electrode is greater than a second spacing between the plurality of second protrusions between the gate electrode and the drain electrode.

2. The semiconductor device as claimed in claim 1, wherein the plurality of first protrusions are located between the source electrode and the drain electrode.

3. The semiconductor device as described in claim 1, further comprising: A source electrode via penetrates the substrate and the active layer, and connects the source electrode to the heat dissipation structure.

4. The semiconductor device as described in claim 3, wherein, In a top view, there are multiple source vias, and all of the multiple source vias are connected to a connection portion.

5. The semiconductor device as described in claim 1, further comprising: A gate via penetrates the substrate and connects the gate electrode to the heat dissipation structure.

6. The semiconductor device as described in claim 5, wherein, In a top view, the gate via is spaced a distance from the active layer.

7. The semiconductor device as claimed in claim 1, wherein the heat dissipation structure is conformally disposed on the bottom surface of the substrate.

8. The semiconductor device as claimed in claim 1, wherein the heat dissipation structure further comprises: A first metal layer is disposed on the first base and the plurality of first protrusions; a second metal layer is disposed on the first metal layer; and a third metal layer is disposed on the second metal layer.

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