Transistor structure

Abstract

A transistor structure including a substrate, a gate, a first doped region, a second doped region, a gate dielectric layer, and a dipole layer is provided. The substrate includes an active region. The active region comprises a first edge and a second edge opposite to each other. The gate is located on the substrate in the active region. The gate overlaps the first edge and the second edge. The first doped region and the second doped region are located in the substrate in the active region at two sides of the gate. The gate dielectric layer is located between the gate and the substrate. The dipole layer is located between the gate and the gate dielectric layer. The dipole layer includes a first opening and a second opening. The first opening overlaps the first edge. The second opening overlaps the second edge.

Description

[Technical Field]

[0001] This invention relates to a semiconductor structure, and more particularly to a transistor structure. [Previous Technology]

[0002] In integrated circuits, transistor elements are one of the main components. A transistor element includes a gate and source and drain regions located in the substrate on both sides of the gate. However, in some transistor elements, compared to the central region of the active region, the absolute value of the threshold voltage (Vt) in the edge region of the active region is lower, which easily leads to a current double-hump effect, thus adversely affecting the electrical performance of the transistor element. [Summary of the Invention]

[0003] The present invention provides a transistor structure that can effectively reduce the current bipeak effect, thereby avoiding the adverse effects of the current bipeak effect on the electrical properties of the transistor structure.

[0004] This invention proposes a transistor structure, including a substrate, a gate, a first doped region, a second doped region, a gate dielectric layer, and a dipole layer. The substrate includes an active region. The active region includes a first edge and a second edge opposite to each other. The gate is located on the substrate of the active region. The gate overlaps the first edge and the second edge. The first doped region and the second doped region are located in the substrate of the active region on both sides of the gate. The gate dielectric layer is located between the gate and the substrate. The dipole layer is located between the gate and the gate dielectric layer. The dipole layer includes a first opening and a second opening. The first opening overlaps the first edge. The second opening overlaps the second edge.

[0005] According to one embodiment of the present invention, in the above-described transistor structure, the dipole layer may extend from the first edge to the second edge. The dipole layer may overlap the first edge and the second edge.

[0006] According to an embodiment of the present invention, in the above-described transistor structure, the first opening and the second opening can be aligned with each other in the direction from the first edge to the second edge.

[0007] According to an embodiment of the present invention, in the above-described transistor structure, the first opening and the second opening are not aligned with each other in the direction from the first edge to the second edge.

[0008] According to an embodiment of the present invention, in the above-described transistor structure, in the direction from the first doped region toward the second doped region, the first opening extends through the dipole layer, and the second opening extends through the dipole layer, thereby dividing the dipole layer into a plurality of parts that are separate from each other.

[0009] According to an embodiment of the present invention, in the above-described transistor structure, the dipole layer may include a plurality of first openings and a plurality of second openings. The plurality of first openings may overlap at a first edge. The plurality of second openings may overlap at a second edge.

[0010] According to an embodiment of the present invention, in the above-described transistor structure, the dipole layer may be a negative polarity dipole (n-dipole) layer or a positive polarity dipole (p-dipole) layer.

[0011] According to an embodiment of the present invention, in the above-described transistor structure, the material of the negative polarity dipole layer is, for example, lanthanum oxide (La₂O₃).

[0012] According to an embodiment of the present invention, in the above-described transistor structure, the material of the positive polarity dipole layer is, for example, aluminum oxide (Al₂O₃).

[0013] According to one embodiment of the present invention, in the above-described transistor structure, the gate may be a metal gate. The gate dielectric layer may include a high dielectric constant dielectric layer.

[0014] According to one embodiment of the present invention, the above-described transistor structure may further include an isolation structure. The isolation structure is located in the substrate. The isolation structure may define an active region. A first opening may overlap the isolation structure. A second opening may overlap the isolation structure.

[0015] This invention proposes another transistor structure, including a substrate, a gate, a first doped region, a second doped region, a gate dielectric layer, a first island dipole layer, and a second island dipole layer. The substrate includes an active region. The active region includes a first edge and a second edge opposite to each other. The gate is located on the substrate of the active region. The gate overlaps the first edge and the second edge. The first doped region and the second doped region are located in the substrate of the active region on both sides of the gate. The gate dielectric layer is located between the gate and the substrate. The first island dipole layer and the second island dipole layer are located between the gate and the gate dielectric layer and are separated from each other. The first island dipole layer overlaps the first edge. The second island dipole layer overlaps the second edge.

[0016] According to another embodiment of the present invention, in the above-described transistor structure, the first island dipole layer and the second island dipole layer can be aligned with each other in the direction from the first edge to the second edge.

[0017] According to another embodiment of the present invention, in the above-described transistor structure, the first island dipole layer and the second island dipole layer are not aligned with each other in the direction from the first edge to the second edge.

[0018] According to another embodiment of the present invention, in the above-described transistor structure, in the direction from the first doped region toward the second doped region, the first island dipole layer may extend to the two opposite edges of the gate, and the second island dipole layer may extend to the two opposite edges of the gate.

[0019] According to another embodiment of the present invention, the transistor structure described above may include a plurality of first island-shaped dipole layers and a plurality of second island-shaped dipole layers. The plurality of first island-shaped dipole layers may overlap at a first edge. The plurality of second island-shaped dipole layers may overlap at a second edge.

[0020] According to another embodiment of the present invention, in the above-described transistor structure, the first island dipole layer and the second island dipole layer may be positive polarity dipole layers.

[0021] According to another embodiment of the present invention, in the above-described transistor structure, the first island dipole layer and the second island dipole layer may be negative polarity dipole layers.

[0022] According to another embodiment of the present invention, in the above-described transistor structure, the gate may be a metal gate. The gate dielectric layer may include a high dielectric constant dielectric layer.

[0023] According to another embodiment of the present invention, the above-described transistor structure may further include an isolation structure. The isolation structure is located in the substrate. The isolation structure may define an active region. A first island dipole layer may be superimposed on the isolation structure. A second island dipole layer may be superimposed on the isolation structure.

[0024] Based on the above, in the transistor structure proposed in some embodiments of the present invention, the dipole layer is located between the gate and the gate dielectric layer. The dipole layer includes a first opening and a second opening. The first opening overlaps with the first edge of the active region, and the second opening overlaps with the second edge of the active region. Therefore, the absolute value of the critical voltage of the transistor structure in the edge region adjacent to the first edge of the active region can be increased, and the absolute value of the critical voltage of the transistor structure in the edge region adjacent to the second edge of the active region can also be increased. In this way, the current bimodal effect can be effectively reduced, thereby avoiding the adverse effects of the current bimodal effect on the electrical properties of the transistor structure.

[0025] Furthermore, in some embodiments of the transistor structure proposed in this invention, the first island dipole layer and the second island dipole layer are located between the gate and the gate dielectric layer and are separated from each other. The first island dipole layer overlaps the first edge of the active region, and the second island dipole layer overlaps the second edge of the active region. Therefore, the absolute value of the critical voltage of the transistor structure in the edge region adjacent to the first edge of the active region can be increased, and the absolute value of the critical voltage of the transistor structure in the edge region adjacent to the second edge of the active region can also be increased. In this way, the current bimodal effect can be effectively reduced, thereby avoiding the adverse effects of the current bimodal effect on the electrical properties of the transistor structure.

[0026] In order to make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are given in conjunction with the accompanying drawings.

Implementation Method

[0027] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. For ease of understanding, the same components will be designated with the same symbols in the following description. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. Additionally, the features in the top view are not drawn to the same scale as those in the sectional view. In fact, for clarity of explanation, the dimensions of various features can be arbitrarily increased or decreased.

[0028] FIG1 is a top view of a transistor structure according to some embodiments of the present invention. FIG2 is a cross-sectional view along section lines I-I' and II-II' in FIG1. ​​In FIG1, some components in FIG2 are omitted to clearly illustrate the arrangement relationship between the components in FIG1. ​​FIG3 is a top view of a transistor structure according to other embodiments of the present invention. FIG4 is a top view of a transistor structure according to other embodiments of the present invention. FIG5 is a top view of a transistor structure according to other embodiments of the present invention.

[0029] Referring to Figures 1 and 2, the transistor structure 10 includes a substrate 100, a gate 102, a doped region 104, a doped region 106, a gate dielectric layer 108, and a dipole layer 110. The transistor structure 10 can be an N-type metal oxide semiconductor (NMOS) transistor structure or a P-type metal oxide semiconductor (PMOS) transistor structure.

[0030] The substrate 100 includes an active region AA1. The active region AA1 includes edges E1 and E2 opposite to each other. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. In some embodiments, the transistor structure 10 may further include an isolation structure 112. The isolation structure 112 is located in the substrate 100. The isolation structure 112 may define the active region AA1. In some embodiments, the isolation structure 112 is, for example, a shallow trench isolation structure. In some embodiments, the material of the isolation structure 112 is, for example, silicon oxide.

[0031] Gate 102 is located on substrate 100 of active region AA1. Gate 102 overlaps edges E1 and E2. Gate 102 may extend from edge E1 to edge E2. In some embodiments, gate 102 may overlap with isolation structure 112. Gate 102 may be a single-layer structure or a multi-layer structure. In some embodiments, gate 102 may be a metallic gate. In some embodiments, the material of gate 102 is, for example, W, TiN, TaN, WN, Ti, Ag, TaAlC, TiAlN, or combinations thereof.

[0032] Doped regions 104 and 106 are located in the substrate 100 of the active region AA1 on both sides of the gate 102. In some embodiments, doped regions 104 and 106 can be used as source / drain regions.

[0033] The gate dielectric layer 108 is located between the gate 102 and the substrate 100. The gate dielectric layer 108 may be a single-layer structure or a multi-layer structure. In some embodiments, the gate dielectric layer 108 may include a high-dielectric-constant dielectric layer 114. The high-dielectric-constant dielectric layer 114 is located between the gate 102 and the substrate 100. In some embodiments, the material of the high-dielectric-constant dielectric layer 114 is, for example, a metal oxide. In some embodiments, the gate dielectric layer 108 may further include an interface layer 116. The interface layer 116 is located between the high-dielectric-constant dielectric layer 114 and the substrate 100. In some embodiments, the material of the interface layer 116 is, for example, silicon oxide.

[0034] The transistor structure 10 may further include a metal silicate layer 118 and a metal silicate layer 120. The metal silicate layer 118 is located on the doped region 104. The metal silicate layer 120 is located on the doped region 106. In some embodiments, the materials of the metal silicate layer 118 and the metal silicate layer 120 are, for example, cobalt silicate (CoSi) or nickel silicate (NiSi). The transistor structure 10 may further include a spacer wall 122. The spacer wall 122 is located on the sidewall of the gate 102. The spacer wall 122 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the spacer wall 122 is, for example, silicon oxide, silicon nitride, or a combination thereof. The transistor structure 10 may further include a dielectric layer 124. The dielectric layer 124 is located on the isolation structure 112, the metal silicate layer 118, and the metal silicate layer 120. In some embodiments, the dielectric layer 124 is made of materials such as silicon oxide, silicon nitride, or combinations thereof. The transistor structure 10 may further include a termination layer 126. The termination layer 126 is located between the dielectric layer 124 and the spacer wall 122, between the dielectric layer 124 and the isolation structure 112, between the dielectric layer 124 and the metal silicide layer 118, and between the dielectric layer 124 and the metal silicide layer 120. In some embodiments, the termination layer 126 is made of materials such as silicon oxide, silicon nitride, or combinations thereof.

[0035] The dipole layer 110 is located between the gate 102 and the gate dielectric layer 108. The dipole layer 110 may extend from edge E1 to edge E2. The dipole layer 110 may overlap edge E1 and edge E2. In some embodiments, the dipole layer 110 may overlap the isolation structure 112. In some embodiments, the dipole layer 110 may be a negative dipole layer or a positive dipole layer 110. In some embodiments, the material of the negative dipole layer is, for example, lanthanum oxide. In some embodiments, the material of the positive dipole layer is, for example, aluminum oxide. In some embodiments, when the transistor structure 10 is an NMOS transistor structure and the dipole layer 110 is a negative dipole layer, the dipole layer 110 may reduce the absolute value of the threshold voltage of the transistor structure 10. In some embodiments, when the transistor structure 10 is a PMOS transistor structure and the dipole layer 110 is a positive dipole layer, the dipole layer 110 may reduce the absolute value of the threshold voltage of the transistor structure 10.

[0036] The dipole layer 110 includes openings OP1 and OP2. In some embodiments, openings OP1 and OP2 may expose the gate dielectric layer 108. In some embodiments, a gate 102 may be filled into openings OP1 and OP2 and may be connected to the gate dielectric layer 108. In some embodiments, opening OP1 may overlap with the isolation structure 112. Opening OP2 may overlap with the isolation structure 112. Opening OP1 overlaps with edge E1. Opening OP2 overlaps with edge E2. When the transistor structure 10 is an NMOS transistor structure and the dipole layer 110 is a negative polarity dipole layer, since the dipole layer 110 has opening OP1 overlapping with edge E1 and opening OP2 overlapping with edge E2, the absolute value of the critical voltage of the transistor structure 10 in the edge region adjacent to edge E1 of the active region AA1 can be increased, and the absolute value of the critical voltage of the transistor structure 10 in the edge region adjacent to edge E2 of the active region AA1 can be increased. Furthermore, when the transistor structure 10 is a PMOS transistor structure and the dipole layer 110 is a positive dipole layer, since the dipole layer 110 has an opening OP1 overlapping edge E1 and an opening OP2 overlapping edge E2, the absolute value of the critical voltage of the transistor structure 10 in the edge region adjacent to edge E1 of the active region AA1 can be increased, and the absolute value of the critical voltage of the transistor structure 10 in the edge region adjacent to edge E2 of the active region AA1 can also be increased.

[0037] In some embodiments, in the direction D1 from edge E1 to edge E2, opening OP1 may have a width W1, opening OP2 may have a width W2, and active area AA1 may have a width W3. In some embodiments, width W1 may be 5% to 30% of width W3. In some embodiments, width W2 may be 5% to 30% of width W3.

[0038] In this embodiment, as shown in FIG1, openings OP1 and OP2 may be aligned with each other in direction D1 from edge E1 to edge E2, but the present invention is not limited thereto. In some other embodiments, as shown in FIG3, openings OP1 and OP2 are not aligned with each other in direction D1 from edge E1 to edge E2.

[0039] In this embodiment, as shown in FIG1, openings OP1 and OP2 can be surrounded by the dipole layer 110, but the present invention is not limited thereto. In this embodiment, as shown in FIG1, in the direction D2 from the doped region 104 to the doped region 106, opening OP1 does not penetrate the dipole layer 110, and opening OP2 does not penetrate the dipole layer 110. In other embodiments, as shown in FIG4, in the direction D2 from the doped region 104 to the doped region 106, opening OP1 extends through the dipole layer 110, and opening OP2 extends through the dipole layer 110, thus dividing the dipole layer 110 into multiple separate parts.

[0040] In this embodiment, as shown in FIG1, the number of openings OP1 and OP2 in the dipole layer 110 is one, but the present invention is not limited thereto. In other embodiments, as shown in FIG5, the dipole layer 110 may include multiple openings OP1 and multiple openings OP2. Multiple openings OP1 may overlap at edge E1. Multiple openings OP2 may overlap at edge E2. Furthermore, when the dipole layer 110 includes multiple openings OP1 and multiple openings OP2, the number of multiple openings OP1 and the number of multiple openings OP2 are not limited to the numbers shown in FIG5. Furthermore, the top view shape of openings OP1 and OP2 is not limited to the shapes shown in the figure.

[0041] Furthermore, in Figures 1 to 5, the same or similar components are represented by the same symbols and their descriptions are omitted.

[0042] Based on the above embodiments, in the transistor structure 10, the dipole layer 110 is located between the gate 102 and the gate dielectric layer 108. The dipole layer 110 includes an opening OP1 and an opening OP2. The opening OP1 overlaps with the edge E1 of the active region AA1, and the opening OP2 overlaps with the edge E2 of the active region AA1. Therefore, the absolute value of the critical voltage of the transistor structure 10 in the edge region adjacent to the edge E1 of the active region AA1 can be increased, and the absolute value of the critical voltage of the transistor structure 10 in the edge region adjacent to the edge E2 of the active region AA1 can also be increased. In this way, the current biphasic effect can be effectively reduced, thereby avoiding the adverse effects of the current biphasic effect on the electrical properties of the transistor structure 10.

[0043] FIG6 is a top view of a transistor structure according to some embodiments of the present invention. FIG7 is a cross-sectional view along section lines III-III' and IV-IV' in FIG6. FIG8 is a top view of a transistor structure according to some embodiments of the present invention. FIG9 is a top view of a transistor structure according to some embodiments of the present invention. FIG10 is a top view of a transistor structure according to some embodiments of the present invention.

[0044] Referring to Figures 6 and 7, the transistor structure 20 includes a substrate 200, a gate 202, a doped region 204, a doped region 206, a gate dielectric layer 208, an island dipole layer 210, and an island dipole layer 212. The transistor structure 10 can be an NMOS transistor structure or a PMOS transistor structure.

[0045] The substrate 200 includes an active region AA2. The active region AA2 includes opposing edges E3 and E4. In some embodiments, the substrate 200 may be a semiconductor substrate, such as a silicon substrate. In some embodiments, the transistor structure 10 may further include an isolation structure 214. The isolation structure 214 is located in the substrate 200. The isolation structure 214 may define the active region AA2. In some embodiments, the isolation structure 214 is, for example, a shallow trench isolation structure. In some embodiments, the material of the isolation structure 214 is, for example, silicon oxide.

[0046] Gate 202 is located on substrate 200 of active region AA2. Gate 202 overlaps edges E3 and E4. Gate 202 may extend from edge E3 to edge E4. In some embodiments, gate 202 may overlap with isolation structure 214. Gate 202 may be a single-layer structure or a multi-layer structure. In some embodiments, gate 202 may be a metallic gate. In some embodiments, the material of gate 202 is, for example, W, TiN, TaN, WN, Ti, Ag, TaAlC, TiAlN, or combinations thereof.

[0047] Doped regions 204 and 206 are located in the substrate 200 of the active region AA2 on both sides of the gate 202. In some embodiments, doped regions 204 and 206 can be used as source / drain regions.

[0048] The gate dielectric layer 208 is located between the gate 202 and the substrate 200. The gate dielectric layer 208 may be a single-layer structure or a multi-layer structure. In some embodiments, the gate dielectric layer 208 may include a high-dielectric-constant dielectric layer 216. The high-dielectric-constant dielectric layer 216 is located between the gate 202 and the substrate 200. In some embodiments, the material of the high-dielectric-constant dielectric layer 216 is, for example, a metal oxide. In some embodiments, the gate dielectric layer 208 may further include an interface layer 218. The interface layer 218 is located between the high-dielectric-constant dielectric layer 216 and the substrate 200. In some embodiments, the material of the interface layer 218 is, for example, silicon oxide.

[0049] The transistor structure 20 may further include a metal silicate layer 220 and a metal silicate layer 222. The metal silicate layer 220 is located on the doped region 204. The metal silicate layer 222 is located on the doped region 206. In some embodiments, the materials of the metal silicate layer 220 and the metal silicate layer 222 are, for example, cobalt silicate (CoSi) or nickel silicate (NiSi). The transistor structure 20 may further include a spacer wall 224. The spacer wall 224 is located on the sidewall of the gate 202. The spacer wall 224 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the spacer wall 224 is, for example, silicon oxide, silicon nitride, or a combination thereof. The transistor structure 20 may further include a dielectric layer 226. The dielectric layer 226 is located on the isolation structure 214, the metal silicate layer 220, and the metal silicate layer 222. In some embodiments, the dielectric layer 226 is made of materials such as silicon oxide, silicon nitride, or combinations thereof. The transistor structure 20 may further include a termination layer 228. The termination layer 228 is located between the dielectric layer 226 and the spacer wall 224, between the dielectric layer 226 and the isolation structure 214, between the dielectric layer 226 and the metal silicide layer 220, and between the dielectric layer 226 and the metal silicide layer 222. In some embodiments, the termination layer 228 is made of materials such as silicon oxide, silicon nitride, or combinations thereof.

[0050] Island dipole layers 210 and 212 are located between the gate 202 and the gate dielectric layer 208 and are separated from each other. Island dipole layer 210 overlaps at edge E3. Island dipole layer 212 overlaps at edge E4. Island dipole layer 210 may overlap with isolation structure 214. Island dipole layer 212 may overlap with isolation structure 214. In some embodiments, island dipole layers 210 and 212 may be positive dipole layers. In some embodiments, the material of the positive dipole layer is, for example, alumina. In some embodiments, island dipole layers 210 and 212 may be negative dipole layers. In some embodiments, the material of the negative dipole layer is, for example, lanthanum oxide. In some embodiments, when the transistor structure 20 is an NMOS transistor structure and the island dipole layer 210 and island dipole layer 212 are positive dipole layers, the absolute value of the critical voltage of the transistor structure 20 in the edge region adjacent to edge E3 of the active region AA2 can be increased, and the absolute value of the critical voltage of the transistor structure 20 in the edge region adjacent to edge E4 of the active region AA2 can also be increased. In some embodiments, when the transistor structure 20 is a PMOS transistor structure and the island dipole layer 210 and island dipole layer 212 are negative dipole layers, the absolute value of the critical voltage of the transistor structure 20 in the edge region adjacent to edge E3 of the active region AA2 can also be increased, and the absolute value of the critical voltage of the transistor structure 20 in the edge region adjacent to edge E4 of the active region AA2 can also be increased.

[0051] In some embodiments, the island dipole layer 210 may have a width W4, the island dipole layer 212 may have a width W4, and the active region AA2 may have a width W6 in the direction D3 from edge E3 to edge E4. In some embodiments, the width W4 may be 5% to 30% of the width W6. In some embodiments, the width W5 may be 5% to 30% of the width W6.

[0052] In this embodiment, as shown in FIG6, the island dipole layer 210 and the island dipole layer 212 may be aligned with each other in the direction D3 from edge E3 to edge E4, but the present invention is not limited thereto. In some other embodiments, as shown in FIG8, the island dipole layer 210 and the island dipole layer 212 are not aligned with each other in the direction D3 from edge E3 to edge E4.

[0053] In this embodiment, as shown in FIG6, in the direction D4 from the doped region 204 to the doped region 206, the island dipole layer 210 and the island dipole layer 212 do not extend to the two opposite edges of the gate 202 (e.g., edge E5 and edge E6), but the present invention is not limited thereto. In some other embodiments, as shown in FIG9, in the direction D4 from the doped region 204 to the doped region 206, the island dipole layer 210 may extend to the two opposite edges of the gate 202 (e.g., edge E5 and edge E6), and the island dipole layer 212 may extend to the two opposite edges of the gate 202 (e.g., edge E5 and edge E6).

[0054] In this embodiment, as shown in FIG6, the number of island dipole layers 210 is one example, and the number of island dipole layers 212 is one example, but the present invention is not limited thereto. In some other embodiments, as shown in FIG10, the transistor structure 20 may include multiple island dipole layers 210 and multiple island dipole layers 212. Multiple island dipole layers 210 may overlap at edge E3. Multiple island dipole layers 212 may overlap at edge E4. Furthermore, when the transistor structure 20 includes multiple island dipole layers 210 and multiple island dipole layers 212, the number of multiple island dipole layers 210 and the number of multiple island dipole layers 212 are not limited to the numbers shown in FIG10. Furthermore, the top view shape of the island dipole layers 210 and the top view shape of the island dipole layers 212 are not limited to the shapes shown in the figure.

[0055] Furthermore, in Figures 6 to 10, the same or similar components are represented by the same symbols, and their descriptions are omitted.

[0056] Based on the above embodiments, in the transistor structure 20, the island dipole layer 210 and the island dipole layer 212 are located between the gate 202 and the gate dielectric layer 208 and are separated from each other. The island dipole layer 210 overlaps with the edge E3 of the active region AA2, and the island dipole layer 212 overlaps with the edge E4 of the active region AA2. Therefore, the absolute value of the critical voltage of the transistor structure 20 in the edge region adjacent to the edge E3 of the active region AA2 can be increased, and the absolute value of the critical voltage of the transistor structure 20 in the edge region adjacent to the edge E4 of the active region AA2 can also be increased. In this way, the current biphasic effect can be effectively reduced, thereby avoiding the adverse effects of the current biphasic effect on the electrical properties of the transistor structure 20.

[0057] In summary, in the transistor structure of some embodiments of the present invention, the dipole layer is located between the gate and the gate dielectric layer. The dipole layer includes a first opening and a second opening. The first opening overlaps with the first edge of the active region, and the second opening overlaps with the second edge of the active region. Therefore, the absolute value of the critical voltage of the transistor structure in the edge region adjacent to the first edge of the active region can be increased, and the absolute value of the critical voltage of the transistor structure in the edge region adjacent to the second edge of the active region can also be increased. In this way, the current bimodal effect can be effectively reduced, thereby avoiding the adverse effects of the current bimodal effect on the electrical properties of the transistor structure.

[0058] In some embodiments of the transistor structure of the present invention, the first island dipole layer and the second island dipole layer are located between the gate and the gate dielectric layer and are separated from each other. The first island dipole layer overlaps the first edge of the active region, and the second island dipole layer overlaps the second edge of the active region. Therefore, the absolute value of the critical voltage of the transistor structure in the edge region adjacent to the first edge of the active region can be increased, and the absolute value of the critical voltage of the transistor structure in the edge region adjacent to the second edge of the active region can also be increased. In this way, the current biphasic effect can be effectively reduced, thereby avoiding the adverse effects of the current biphasic effect on the electrical properties of the transistor structure.

[0059] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0060] Figure 1 is a top view of a transistor structure according to some embodiments of the present invention. Figure 2 is a cross-sectional view along section lines I-I' and II-II' in Figure 1. Figure 3 is a top view of a transistor structure according to other embodiments of the present invention. Figure 4 is a top view of a transistor structure according to other embodiments of the present invention. Figure 5 is a top view of a transistor structure according to other embodiments of the present invention. Figure 6 is a top view of a transistor structure according to other embodiments of the present invention. Figure 7 is a cross-sectional view along section lines III-III' and IV-IV' in Figure 6. Figure 8 is a top view of a transistor structure according to other embodiments of the present invention. Figure 9 is a top view of a transistor structure according to other embodiments of the present invention. Figure 10 is a top view of a transistor structure according to other embodiments of the present invention.

Claims

1. A transistor structure, comprising: The substrate includes an active region, wherein the active region includes a first edge and a second edge opposite to each other; A gate is located on the substrate of the active region and overlaps the first edge and the second edge; a first doped region and a second doped region are located in the substrate of the active region on both sides of the gate; a gate dielectric layer is located between the gate and the substrate; And a dipole layer, located between the gate and the gate dielectric layer, wherein the dipole layer includes a first opening and a second opening, the first opening overlapping the first edge, the second opening overlapping the second edge, and the first opening and the second opening being located in and penetrating the dipole layer.

2. The transistor structure as claimed in claim 1, wherein the dipole layer extends from the first edge to the second edge and overlaps the first edge and the second edge.

3. The transistor structure as claimed in claim 1, wherein the first opening and the second opening are aligned with each other in the direction from the first edge toward the second edge.

4. The transistor structure as claimed in claim 1, wherein the first opening and the second opening are not aligned with each other in the direction from the first edge toward the second edge.

5. The transistor structure of claim 1, wherein in a direction from the first doped region toward the second doped region, the first opening extends through the dipole layer and the second opening extends through the dipole layer, thereby dividing the dipole layer into a plurality of mutually separated portions.

6. The transistor structure of claim 1, wherein the dipole layer includes a plurality of first openings and a plurality of second openings, wherein the plurality of first openings overlap the first edge and the plurality of second openings overlap the second edge.

7. The transistor structure as claimed in claim 1, wherein the dipole layer comprises a negative dipole layer or a positive dipole layer.

8. The transistor structure as claimed in claim 7, wherein the material of the negative polarity dipole layer comprises lanthanum oxide.

9. The transistor structure as claimed in claim 7, wherein the material of the positive polarity dipole layer comprises aluminum oxide.

10. The transistor structure as claimed in claim 1, wherein the gate comprises a metal gate and the gate dielectric layer comprises a high dielectric constant dielectric layer.

11. The transistor structure as described in claim 1, further comprising: An isolation structure is located in the substrate and defines the active region, wherein a first opening overlaps the isolation structure and a second opening overlaps the isolation structure.

12. A transistor structure, comprising: The substrate includes an active region, wherein the active region includes a first edge and a second edge opposite to each other; A gate is located on the substrate of the active region and overlaps the first edge and the second edge; a first doped region and a second doped region are located in the substrate of the active region on both sides of the gate; a gate dielectric layer is located between the gate and the substrate; A first island dipole layer and a second island dipole layer are located between the gate and the gate dielectric layer and are separated from each other, wherein the first island dipole layer overlaps the first edge and the second island dipole layer overlaps the second edge.

13. The transistor structure of claim 12, wherein the first island dipole layer and the second island dipole layer are aligned with each other in a direction from the first edge toward the second edge.

14. The transistor structure of claim 12, wherein the first island dipole layer and the second island dipole layer are not aligned with each other in the direction from the first edge toward the second edge.

15. The transistor structure of claim 12, wherein, in the direction from the first doped region toward the second doped region, the first island dipole layer extends to opposite edges of the gate, and the second island dipole layer extends to opposite edges of the gate.

16. The transistor structure of claim 12, comprising a plurality of first island dipole layers and a plurality of second island dipole layers, wherein the plurality of first island dipole layers overlap the first edge and the plurality of second island dipole layers overlap the second edge.

17. The transistor structure of claim 12, wherein the first island dipole layer and the second island dipole layer comprise a positive dipole layer.

18. The transistor structure of claim 12, wherein the first island dipole layer and the second island dipole layer comprise a negative dipole layer.

19. The transistor structure of claim 12, wherein the gate comprises a metal gate and the gate dielectric layer comprises a high dielectric constant dielectric layer.

20. The transistor structure as described in claim 12, further comprising: An isolation structure is located in the substrate and defines the active region, wherein a first island dipole layer overlaps the isolation structure, and a second island dipole layer overlaps the isolation structure.

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