Thin film transistor

Abstract

A thin film transistor includes a semiconductor layer and a buffer layer located on one side of the semiconductor layer. The semiconductor layer includes a source region, a drain region and a channel region, wherein the source region and the drain region are doped with boron, and the channel region is located between the source region and the drain region. The buffer layer includes a first region, a second region and a third region located between the first region and the second region. The first region and the second region are doped with boron and overlapped with the source region and the drain region, respectively. The third region is overlapped with the channel region and not doped with boron.

Description

[Technical Field]

[0001] This invention relates to a semiconductor element, and more particularly to a thin-film transistor. [Previous Technology]

[0002] Generally speaking, electronic devices contain many semiconductor components. For example, display devices often contain many thin-film transistors, which are formed by depositing various thin films (such as semiconductors, metals, dielectric layers, etc.) on a substrate. In display devices, thin-film transistors can be disposed in the pixel structure or in the driving circuit.

[0003] Current trends in display devices require high-current micro-LED products, making it imperative to improve the carrier mobility of thin-film transistors. Although reducing the channel size of thin-film transistors can improve the on-state current (Ion) and carrier mobility, it is accompanied by problems such as electrical inhomogeneity across the entire substrate (e.g., threshold voltage (Vth) divergence) and drain-induced barrier lowering (DIBL) effects, leading to easy conduction at large trans-voltages.

[0004] Therefore, how to improve the carrier mobility of thin-film transistors while maintaining the channel size remains one of the goals that related companies are seeking to improve. [Summary of the Invention]

[0005] One embodiment of the present invention provides a thin-film transistor, comprising a semiconductor layer and a buffer layer located on one side of the semiconductor layer. The semiconductor layer includes a source region, a drain region, and a channel region, wherein the source region and the drain region are boron-doped, and the channel region is located between the source region and the drain region. The buffer layer includes a first region, a second region, and a third region. The first region and the second region are boron-doped and overlap the source region and the drain region, respectively. The third region is located between the first region and the second region and overlaps the channel region, wherein the third region is undoped.

[0006] In one embodiment of the present invention, the semiconductor layer described above comprises a metal oxide semiconductor material.

[0007] In one embodiment of the present invention, the boron concentration in the first region of the buffer layer is higher than the boron concentration in the source region, and the boron concentration in the second region of the buffer layer is higher than the boron concentration in the drain region.

[0008] In one embodiment of the present invention, the thin-film transistor further includes a bottom gate, wherein a buffer layer is located between the bottom gate and the semiconductor layer.

[0009] In one embodiment of the present invention, the thin film transistor further includes a top gate and a gate insulating layer, wherein the gate insulating layer is located on the side of the semiconductor layer opposite to the buffer layer, and the gate insulating layer is located between the channel region of the semiconductor layer and the top gate.

[0010] In one embodiment of the present invention, the gate insulating layer completely overlaps the channel region of the semiconductor layer.

[0011] In one embodiment of the present invention, the gate insulating layer described above is not boron-doped.

[0012] In one embodiment of the present invention, the thin film transistor further includes an interlayer insulating layer, which physically contacts the source and drain regions of the semiconductor layer, and the interlayer insulating layer is rich in hydrogen.

[0013] In one embodiment of the present invention, the thin film transistor further includes a source and a drain, the source and drain passing through the interlayer insulating layer and electrically connected to the source region and the drain region respectively.

[0014] In one embodiment of the present invention, the above-mentioned gate insulating layer overlaps the channel region, source region and drain region of the semiconductor layer.

[0015] In one embodiment of the present invention, the overlapping source and drain regions of the gate insulating layer are partially boron-doped.

[0016] In one embodiment of the present invention, the thin film transistor further includes an interlayer insulating layer, which covers the top gate and the gate insulating layer, and the gate insulating layer separates the semiconductor layer from the interlayer insulating layer.

[0017] In one embodiment of the present invention, the thin film transistor further includes a source and a drain, the source and drain passing through the interlayer insulating layer and the gate insulating layer to be electrically connected to the source region and the drain region respectively.

[0018] In order to make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are given in conjunction with the accompanying drawings.

Implementation Method

[0019] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Throughout the specification, the same reference numerals denote the same elements. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected" to another element, it may be directly on or connected to the other element, or intermediate elements may also be present. Conversely, when an element is referred to as being "directly on" or "directly connected" to another element, no intermediate elements are present. As used herein, "connection" can refer to a physical and / or electrical connection. Furthermore, "electrical connection" or "coupling" may refer to the presence of other elements between two elements.

[0020] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, the first "element," "component," "region," "layer," or "part" discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings of this document.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include the plural forms, including "at least one" or indicating "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should also be understood that, when used in this specification, the terms "comprising" and / or "including" specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0022] Furthermore, relative terms such as "below" or "bottom" and "above" or "top" may be used herein to describe the relationship between one element and another element, as shown in the figures. It should be understood that relative terms are intended to include different orientations of the device other than those shown in the figures. For example, if a device in one figure is flipped, an element described as being "below" the other element will be oriented "above" the other element. Thus, the exemplary term "below" can include both "below" and "above" orientations, depending on the specific orientation of the figure. Similarly, if a device in one figure is flipped, an element described as being "below" or "below" the other element will be oriented "above" the other element. Thus, the exemplary term "below" or "below" can include both "above" and "below" orientations.

[0023] Given the specific number of measurements discussed and the associated errors (i.e., limitations of the measurement system), the terms "about," "approximately," or "substantially" as used herein include the value and the average value within an acceptable range of deviations of the specific value as determined by one of ordinary skill in the art. For example, "about" may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the terms "about," "approximately," or "substantially" as used herein may be chosen based on optical, etched, or other properties to select a more acceptable range of deviations or standard deviations, rather than applying a single standard deviation to all properties.

[0024] Figures 1A to 1E are cross-sectional schematic diagrams illustrating the steps of a method for fabricating a thin-film transistor 10 according to an embodiment of the present invention. Hereinafter, the method for fabricating the thin-film transistor 10 will be described in conjunction with Figures 1A to 1E.

[0025] Referring to FIG1A, firstly, a substrate 102 is provided. For example, the material of the substrate 102 may include glass, quartz, organic polymer, or opaque / reflective material (e.g., conductive material, metal, wafer, ceramic or other applicable material) or other applicable material.

[0026] Next, an insulating layer 104 is formed on the substrate 102. The method for forming the insulating layer 104 is, for example, physical vapor deposition, chemical vapor deposition, or other suitable methods. The insulating layer 104 can be a single layer or multiple layers, and the insulating layer can include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitrides (SiONx), or other suitable materials or stacked layers of the above materials.

[0027] Next, a bottom gate 106 is formed on the insulating layer 104. The method for forming the bottom gate 106 may include the following steps. First, a gate metal layer (not shown) is formed on the insulating layer 104. Then, a patterned photoresist (not shown) is formed on the gate metal layer using a photolithography process. Next, the gate metal layer is subjected to a wet or dry etching process using the patterned photoresist as a mask to form the bottom gate 106. Afterward, the patterned photoresist is removed.

[0028] The material of the bottom gate 106 may include metals such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn), lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn), or alloys of any combination of the above metals, or stacks of the above metals and / or alloys, but is not limited thereto. The bottom gate 106 may also use other conductive materials, such as: metal nitrides, metal oxides, metal oxynitrides, stacks of metals and other conductive materials, or other materials with conductive properties.

[0029] Next, a buffer layer 108 is formed on the bottom gate 106 and the insulating layer 104. The method for forming the buffer layer 108 is, for example, physical vapor deposition, chemical vapor deposition, or other suitable methods. The buffer layer 108 can be a single layer or multiple layers of insulating layers, and the insulating layers can include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitrides (SiONx), or other suitable materials or stacks of the above materials.

[0030] Next, a semiconductor layer 110 is formed on the bottom gate 106. For example, the method of forming the semiconductor layer 110 may include the following steps: First, a blanket semiconductor material layer (not shown) is formed on the buffer layer 108; then, a patterned photoresist (not shown) is formed on the semiconductor material layer using a photolithography process; subsequently, the patterned photoresist is used as a mask to perform a wet or dry etching process on the semiconductor material layer to form the semiconductor layer 110; afterward, the patterned photoresist is removed. The buffer layer 108 can store oxygen atoms to repair oxygen vacancies (Vo) in the semiconductor layer 110 in subsequent thermal processes.

[0031] The orthogonal projection of the semiconductor layer 110 onto the substrate 102 can overlap with the orthogonal projection of the bottom gate 106 onto the substrate 102. The semiconductor layer 110 may include a metal oxide semiconductor material. In some embodiments, the semiconductor layer 110 may include at least one of metal elements such as indium, zinc, aluminum, tungsten, tin, and gallium. For example, the material of the semiconductor layer 110 may include indium zinc oxide (InZnO, IZO), indium gallium zinc oxide (InGaZnO, IGZO), indium aluminum zinc oxide (InAlZnO, IAZO), indium tungsten oxide (InWO, IWO), indium tungsten zinc oxide (InWZnO, IWZO), indium zinc tin oxide (InZnSnO, IZTO), indium gallium tin oxide (InGaSnO, IGTO), or indium gallium zinc tin oxide (InGaZnSnO, IGZTO), but the present invention is not limited thereto.

[0032] Next, a gate insulating layer 112 is formed on the semiconductor layer 110 and the buffer layer 108. The method for forming the gate insulating layer 112 is, for example, physical vapor deposition, chemical vapor deposition, or other suitable methods. The gate insulating layer 112 can be a single layer or multiple layers of insulating layers, and the insulating layers can include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitrides (SiONx), or other suitable materials or stacks of the above materials. The material of the gate insulating layer 112 may be different from the material of the buffer layer 108.

[0033] Next, a top gate 114 is formed on the semiconductor layer 110. The method for forming the top gate 114 may include the following steps. First, a gate metal layer (not shown) is formed on the gate insulating layer 112. Then, a patterned photoresist (not shown) is formed on the gate metal layer using a photolithography process. Next, the gate metal layer is subjected to a wet or dry etching process using the patterned photoresist as a mask to form the top gate 114. Afterward, the patterned photoresist is removed.

[0034] The orthogonal projection of the top gate 114 onto the substrate 102 overlaps with the orthogonal projection of the semiconductor layer 110 onto the substrate 102. The material of the top gate 114 may include metals, such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn), lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn), or alloys of any combination of the above metals, or stacks of the above metals and / or alloys, but is not limited thereto. The top gate 114 may also use other conductive materials, such as: metal nitrides, metal oxides, metal oxide oxynitrides, stacks of metals and other conductive materials, or other materials with conductive properties. The material of the top gate 114 may be the same as or different from the material of the bottom gate 106.

[0035] Referring to Figure 1B, next, using the top gate 114 as a mask, a portion of the gate insulating layer 112 is removed to form a gate insulating layer 112'. After the gate insulating layer 112' is formed, the portion of the semiconductor layer 110 that does not overlap with the top gate 114 is exposed. The gate insulating layer 112 can be removed using an etching process or other suitable methods. For example, the etching process described above can be performed using an etchant that has relatively high etch selectivity for the gate insulating layer 112 but does not readily etch the semiconductor layer 110.

[0036] Referring to Figure 1C, the boron doping process BD is then performed. The boron doping process BD can utilize the top gate 114 as a mask to perform doping on the semiconductor layer 110 and the buffer layer 108. After the boron doping process BD, the portion of the semiconductor layer 110 that overlaps with the top gate 114 can form a channel region 110c, and the first region 110a and the second region 110b of the semiconductor layer 110 that do not overlap with the top gate 114 can have a higher boron (B) concentration than the channel region 110c. In some embodiments, the first region 110a and the second region 110b of the semiconductor layer 110 are boron doped, and the channel region 110c is located between the first region 110a and the second region 110b and is not boron doped. Boron doping process (BD) can implant boron into the first region 110a and the second region 110b of semiconductor layer 110, thereby breaking the covalent bonds between metal atoms and oxygen atoms and ejecting oxygen atoms. Furthermore, the boron atoms can form stable bonds with the ejected oxygen atoms, thereby generating more oxygen vacancies (Vo), which reduces the resistance of the first region 110a and the second region 110b and improves the Ion and carrier mobility of the thin film transistor.

[0037] After the boron doping process BD, the portion of the buffer layer 108 with the overlapping top gate 114 can form an undoped region 108c, and the first region 108a and the second region 108b of the buffer layer 108 without the overlapping top gate 114 can have a higher boron concentration than the undoped region 108c. In other words, the first region 108a and the second region 108b of the buffer layer 108 are boron doped, and the undoped region 108c is located between the first region 108a and the second region 108b and is undoped. The boron doping process (BD) implants boron into the first region 108a and the second region 108b of the buffer layer 108, thereby enabling boron atoms to form stable bonds with the extra oxygen atoms (exO). This prevents these exO atoms from continuously repairing defects in the first region 110a and the second region 110b of the semiconductor layer 110 during subsequent processes, thus preventing an increase in the resistance of the first region 110a and the second region 110b, and consequently preventing a decrease in the Ion and carrier mobility of the thin-film transistor. Furthermore, the undoped region 108c can still repair defects in the channel region 110c of the semiconductor layer 110 during subsequent processes, thereby improving the reliability of the thin-film transistor.

[0038] The implantation depth of boron can be proportional to the implantation energy used in the boron-doped BD process. In some embodiments, the implantation energy used in the boron-doped BD process is about 10 keV to 40 keV, for example, about 20 keV or 30 keV. In some embodiments, the implantation dose used in the boron-doped BD process is about 8.00E+11 ions / cm2 to 1.20E+15 ions / cm2, for example, about 1.20E+13 ions / cm2 or 1.20E+14 ions / cm2.

[0039] In some embodiments, the boron concentration of the first region 108a of the buffer layer 108 is higher than the boron concentration of the first region 110a of the semiconductor layer 110, and the boron concentration of the second region 108b of the buffer layer 108 is higher than the boron concentration of the second region 110b of the semiconductor layer 110. In some embodiments, the boron concentration of the first region 108a and the second region 108b of the buffer layer 108 is about 450% to 14500% higher than that of the first region 110a and the second region 110b of the semiconductor layer 110. For example, the boron concentration of the first region 108a of the buffer layer 108 is about 4.5 to 145 times that of the first region 110a of the semiconductor layer 110. Alternatively, the boron concentration of the second region 108b of the buffer layer 108 may be about 4.5 to 145 times that of the second region 110b of the semiconductor layer 110. In some embodiments, the boron concentration of the first region 108a and / or the second region 108b of the buffer layer 108 is about 10 to 100 times that of the boron concentration of the first region 110a and / or the second region 110b of the semiconductor layer 110.

[0040] Referring to Figure 1D, an interlayer insulating layer 118 is then formed on the top gate 114, the gate insulating layer 112', the semiconductor layer 110, and the buffer layer 108. The method for forming the interlayer insulating layer 118 is, for example, physical vapor deposition, chemical vapor deposition, or other suitable methods. In this embodiment, the reactants used to form the interlayer insulating layer 118 may contain hydrogen, making the interlayer insulating layer 118 a hydrogen-rich insulating layer. The interlayer insulating layer 118 can be a single layer or multiple layers of insulating layers, and the material of the insulating layer includes, for example, silicon nitride (SiNx).

[0041] During the formation of the interlayer insulating layer 118 or in the subsequent heat treatment process, hydrogen can migrate or diffuse from the interlayer insulating layer 118 into the semiconductor layer 110, thereby adjusting the hydrogen content of the first region 110a and the second region 110b of the semiconductor layer 110 and improving its conductivity. In this way, the first region 110a and the second region 110b can be transformed into the source region 110d and the drain region 110e with higher hydrogen concentrations, respectively, and the source region 110d and the drain region 110e have higher conductivity than the first region 110a and the second region 110b, thereby enabling them to form ohmic contacts with the subsequently formed source and drain, respectively.

[0042] Referring to Figure 1E, vias V1 and V2 are then formed in the interlayer insulating layer 118, and vias V1 and V2 expose the source region 110d and drain region 110e of the semiconductor layer 110, respectively. For example, a patterned photoresist (not shown) is formed on the interlayer insulating layer 118 using a photolithography process. Subsequently, the patterned photoresist is used as a mask to perform a wet or dry etching process on the interlayer insulating layer 118 to form vias V1 and V2 penetrating the interlayer insulating layer 118. Afterward, the patterned photoresist is removed.

[0043] Next, a source 120 is formed on the interlayer insulating layer 118 and in the via V1, and a drain 122 is formed on the interlayer insulating layer 118 and in the via V2. The source 120 can be electrically connected to the source region 110d of the semiconductor layer 110 through the via V1, and the drain 122 can be electrically connected to the drain region 110e of the semiconductor layer 110 through the via V2, thereby forming a thin-film transistor 10, which can be a dual-gate thin-film transistor.

[0044] For example, the method for forming the source 120 and drain 122 may include the following steps. First, a conductive layer (not shown) is formed on the substrate 102 using chemical vapor deposition or physical vapor deposition. Next, a patterned photoresist (not shown) is formed on the conductive layer using a photolithography process. Subsequently, the conductive layer is subjected to a wet or dry etching process using the patterned photoresist as a mask to form the source 120 and drain 122. Afterward, the patterned photoresist is removed. The source 120 and drain 122 may belong to the same film layer. The materials of the source 120 and drain 122 may include chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, alloys of the aforementioned metals, or stacked layers of the aforementioned metals and / or alloys, or other conductive materials.

[0045] In some embodiments, a passivation layer 124 may also be formed on the source 120, drain 122, and interlayer insulating layer 118. The passivation layer 124 may be formed by plasma chemical vapor deposition or other suitable processes, and the material of the passivation layer 124 may be silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials or a stack of the above materials.

[0046] FIG1E is a schematic cross-sectional view of a thin-film transistor 10 according to an embodiment of the present invention. The thin-film transistor 10 may be disposed on a substrate 102 and includes a semiconductor layer 110 and a buffer layer 108, wherein the buffer layer 108 may be located between the substrate 102 and the semiconductor layer 110. The semiconductor layer 110 may include a source region 110d, a drain region 110e, and a channel region 110c. The channel region 110c is located between the source region 110d and the drain region 110e. The source region 110d and the drain region 110e are boron-doped, while the channel region 110c is not boron-doped, such that the boron concentration of the source region 110d and the drain region 110e may be higher than the boron concentration of the channel region 110c. Boron doping can break the covalent bonds between metal atoms and oxygen atoms in the source region 110d and drain region 110e, thereby ejecting oxygen atoms. Furthermore, the boron atoms can form stable bonds with the ejected oxygen atoms, thereby generating more oxygen vacancies, which in turn reduces the resistance of the source region 110d and drain region 110e and improves the Ion and carrier mobility of the thin film transistor 10.

[0047] Buffer layer 108 is located on one side of semiconductor layer 110, for example, the lower side. Buffer layer 108 may include a first region 108a, a second region 108b, and an undoped region 108c. The undoped region 108c is located between the first region 108a and the second region 108b, and the first region 108a and the second region 108b are boron-doped, while the undoped region 108c is undoped. The boron concentration of the first region 108a and the second region 108b may be higher than the boron concentration of the undoped region 108c, so that the additional oxygen atoms in the first region 108a and the second region 108b can form stable bonds with boron atoms, thereby preventing these additional oxygen atoms from continuously repairing defects in the source region 110d and the drain region 110e of semiconductor layer 110 during subsequent processes, thereby preventing the resistance of the source region 110d and the drain region 110e of semiconductor layer 110 from increasing. In addition, the undoped region 108c can still repair defects in the channel region 110c of the semiconductor layer 110 during subsequent processes, thereby improving the reliability of the thin film transistor 10.

[0048] In some embodiments, the first region 108a completely overlaps with the source region 110d, the second region 108b completely overlaps with the drain region 110e, and the undoped region 108c completely overlaps with the channel region 110c. In some embodiments, the boron concentration of the first region 108a is higher than the boron concentration of the source region 110d, and the boron concentration of the second region 108b is higher than the boron concentration of the drain region 110e.

[0049] The thin-film transistor 10 may further include a bottom gate 106, and a buffer layer 108 may be located between the bottom gate 106 and the semiconductor layer 110. In some embodiments, the thin-film transistor 10 may further include a gate insulating layer 112' and a top gate 114, wherein the gate insulating layer 112' is located on the side of the semiconductor layer 110 opposite to the buffer layer 108; in other words, the semiconductor layer 110 may be located between the buffer layer 108 and the gate insulating layer 112'. The gate insulating layer 112' may be entirely located between the top gate 114 and the semiconductor layer 110. For example, the gate insulating layer 112' completely overlaps the top gate 114; therefore, the gate insulating layer 112' is not boron-doped. The gate insulating layer 112' may completely overlap the channel region 110c of the semiconductor layer 110, but does not overlap the source region 110d and drain region 110e of the semiconductor layer 110.

[0050] The thin-film transistor 10 may further include a hydrogen-rich interlayer insulating layer 118, and the interlayer insulating layer 118 may cover the top gate 114, the gate insulating layer 112', the semiconductor layer 110, and the buffer layer 108. For example, the interlayer insulating layer 118 may substantially contact the upper and side surfaces of the top gate 114, the side surface of the gate insulating layer 112', the upper and side surfaces of the source region 110d and the drain region 110e of the semiconductor layer 110, and the upper surface of the non-overlapping portion of the semiconductor layer 110 of the buffer layer 108.

[0051] The thin-film transistor 10 may further include a source 120 and a drain 122, and the source 120 and drain 122 may penetrate the interlayer insulating layer 118 and be electrically connected to the source region 110d and drain region 110e of the semiconductor layer 110, respectively. In some embodiments, the thin-film transistor 10 may further include an insulating layer 104 located between the bottom gate 106 and the substrate 102 to prevent impurities in the substrate 102 from diffusing into other film layers of the thin-film transistor 10. In some embodiments, the thin-film transistor 10 may further include a passivation layer 124, and the passivation layer 124 may cover the source 120, drain 122 and interlayer insulating layer 118 to provide protection for the film layers of the thin-film transistor 10.

[0052] Figures 2A to 2C are schematic cross-sectional views illustrating the steps of a method for fabricating a thin-film transistor 20 according to another embodiment of the present invention. It must be noted that the embodiments in Figures 2A to 2C follow the steps of Figure 1A, and the embodiments in Figures 2A to 2C use the same component designations and some content as the embodiments in Figures 1A to 1E, where the same or similar designations are used to represent the same or similar components, and descriptions of identical technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, which will not be repeated here.

[0053] Referring to Figure 2A, after forming the insulating layer 104, bottom gate 106, buffer layer 108, semiconductor layer 110, gate insulating layer 112, and top gate 114 on the substrate 102 as shown in Figure 1A, the top gate 114 can be used as a mask to perform a boron doping process BD on the gate insulating layer 112, semiconductor layer 110, and buffer layer 108. After the boron doping process BD, the portion of the buffer layer 108 overlapping the top gate 114 can form an undoped region 108c, and the first region 108a and the second region 108b of the buffer layer 108 that do not overlap the top gate 114 can have a higher boron concentration than the undoped region 108c. Furthermore, after the boron doping process BD, the portion of the semiconductor layer 110 with the overlapping top gate 114 can form a channel region 110c, and the first region 110a and the second region 110b of the semiconductor layer 110 without the overlapping top gate 114 can have a higher boron concentration than the channel region 110c. Additionally, after the boron doping process BD, the portion of the gate insulating layer 112 with the overlapping top gate 114 can form an undoped region 112c, and the first region 112a and the second region 112b of the gate insulating layer 112 without the overlapping top gate 114 can have a higher boron concentration than the undoped region 112c.

[0054] Referring to Figure 2B, the top gate 114 can then be used as a mask to perform a doping process IA on the semiconductor layer 110. After the doping process IA, the first region 110a and the second region 110b of the semiconductor layer 110 that do not overlap with the top gate 114 can be transformed into source region 110d and drain region 110e, respectively, and the source region 110d and drain region 110e have lower resistance than the channel region 110c. In some embodiments, the doping process IA is a hydrogen plasma process, and the doping process IA can implant hydrogen elements into the first region 110a and the second region 110b of the semiconductor layer 110, so that the first region 110a and the second region 110b are transformed into source region 110d and drain region 110e with higher hydrogen concentrations, and the source region 110d and drain region 110e have improved carrier mobility. In some embodiments, an ohmic contact can be formed between the source region 110d of the semiconductor layer 110 and the subsequently formed source 120, and an ohmic contact can be formed between the drain region 110e of the semiconductor layer 110 and the subsequently formed drain 122.

[0055] Referring to Figure 2C, an interlayer insulating layer 218 is then formed on the top gate 114 and the gate insulating layer 112. Next, the interlayer insulating layer 218 and the gate insulating layer 112 are patterned. For example, a blanket dielectric material layer (interlayer insulating layer 218 before patterning) is formed on the substrate 102 using chemical vapor deposition or physical vapor deposition. Next, a patterned photoresist (not shown) is formed on the dielectric material layer using a photolithography process. Next, using the patterned photoresist as a mask, a wet or dry etching process is performed on the interlayer insulating layer 218 and the gate insulating layer 112 before patterning to form vias V1 and V2. Afterward, the patterned photoresist is removed.

[0056] The patterned interlayer insulating layer 218 and gate insulating layer 112 have vias V1 and V2 passing through the interlayer insulating layer 218 and the gate insulating layer 112. For example, via V1 passes through the first region 112a of the interlayer insulating layer 218 and the gate insulating layer 112 and exposes the exposed portion in the source region 110d of the semiconductor layer 110, while via V2 passes through the second region 112b of the interlayer insulating layer 218 and the gate insulating layer 112 and exposes the exposed portion in the drain region 110e of the semiconductor layer 110.

[0057] In this embodiment, the material of the interlayer insulating layer 218 may include silicon nitride, silicon oxide, silicon oxynitride, organic polymers, or other suitable materials, or a stacked layer of the above materials. In some embodiments, the reactants used to form the interlayer insulating layer 218 may contain hydrogen, and during the formation of the interlayer insulating layer 218 or in subsequent patterning or heat treatment processes, hydrogen may migrate or diffuse to the source region 110d and drain region 110e of the semiconductor layer 110, thereby adjusting the hydrogen content in the source region 110d and drain region 110e, and thus improving their conductivity.

[0058] Next, a source electrode 120 is formed on the interlayer insulating layer 218 and in the via V1, and a drain electrode 122 is formed on the interlayer insulating layer 218 and in the via V2, thereby forming a thin-film transistor 20. For example, the source electrode 120 can be electrically connected to the source region 110d through the via V1, and the drain electrode 122 can be electrically connected to the drain region 110e through the via V2, and the source electrode 120 and the drain electrode 122 can form ohmic contacts with the source region 110d and the drain region 110e, respectively. In some embodiments, a passivation layer 124 can also be formed on the source electrode 120, the drain electrode 122, and the interlayer insulating layer 218.

[0059] FIG2C is a schematic cross-sectional view of a thin-film transistor 20 according to an embodiment of the present invention. The thin-film transistor 20 may include a substrate 102, an insulating layer 104, a bottom gate 106, a buffer layer 108, a semiconductor layer 110, a gate insulating layer 112, a top gate 114, an interlayer insulating layer 218, a source 120, a drain 122, and a passivation layer 124.

[0060] The main difference between the thin-film transistor 10 shown in FIG. 1E and the thin-film transistor 20 shown in FIG. 2C is that the gate insulating layer 112 of the thin-film transistor 20 extends to the source region 110d and the drain region 110e of the semiconductor layer 110. For example, the first region 112a of the gate insulating layer 112 overlaps the source region 110d of the semiconductor layer 110, and the second region 112b of the gate insulating layer 112 overlaps the drain region 110e of the semiconductor layer 110. In addition, the gate insulating layer 112 may also cover the side surface of the semiconductor layer 110 and the upper surface of the portion of the buffer layer 108 that does not overlap with the semiconductor layer 110.

[0061] In some embodiments, the first region 112a and the second region 112b of the gate insulating layer 112 that do not overlap with the top gate 114 are boron-doped, and the undoped region 112c of the gate insulating layer 112 overlaps with the top gate 114 and is located between the first region 112a and the second region 112b. The first region 112a and the second region 112b may have a higher boron concentration than the undoped region 112c.

[0062] In some embodiments, the source 120 and drain 122 of the thin-film transistor 20 are electrically connected to the source region 110d and drain region 110e of the semiconductor layer 110, respectively, through the interlayer insulating layer 218 and the gate insulating layer 112. In addition to silicon nitride, the material of the interlayer insulating layer 218 of the thin-film transistor 20 can also be silicon oxide, silicon oxynitride, organic polymers, or other suitable materials, or a stack of the above materials. Furthermore, the gate insulating layer 112 also separates the interlayer insulating layer 218 from the semiconductor layer 110.

[0063] Figures 3A to 3G are cross-sectional schematic diagrams illustrating the steps of a method for fabricating a thin-film transistor 30 according to another embodiment of the present invention. It must be noted that the embodiments in Figures 3A to 3G use the same component reference numerals and some content as the embodiments in Figures 2A to 2C, where the same or similar reference numerals are used to represent the same or similar components, and descriptions of identical technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and they will not be repeated here.

[0064] Referring to FIG3A, an insulating layer 104 can be formed on the substrate 102 using a thin film deposition process such as physical vapor deposition or chemical vapor deposition. Next, a bottom gate 106 can be formed on the insulating layer 104 using a deposition process, a lithography process, and an etching process. Next, a buffer layer 108 can be formed on the bottom gate 106 and the insulating layer 104 using a physical vapor deposition process, a chemical vapor deposition process, or other suitable methods. Next, a patterned photoresist PR can be formed on the buffer layer 108 using a spin coating process, a lithography process, and an ashing process.

[0065] Referring to Figure 3B, the buffer layer 108 is then subjected to a first boron doping process BD1 using a patterned photoresist PR as a mask. After the first boron doping process BD1, the portion of the buffer layer 108 overlapping with the patterned photoresist PR can form an undoped region 108c, and the first region 108a and the second region 108b of the buffer layer 108 without overlapping patterned photoresist PR can have a higher boron concentration than the undoped region 108c. Referring to Figure 3C, the patterned photoresist PR is then removed.

[0066] Referring to Figure 3D, a semiconductor layer 110 can then be formed on the first region 108a, the second region 108b, and the undoped region 108c of the buffer layer 108 using deposition, lithography, and etching processes. Next, a gate insulating layer 112 can be formed on the semiconductor layer 110 and the buffer layer 108 using physical vapor deposition, chemical vapor deposition, or other suitable methods. Next, a top gate 114 can be formed on the gate insulating layer 112 using deposition, lithography, and etching processes.

[0067] Referring to Figure 3E, the top gate 114 can then be used as a mask to perform a second boron doping process BD2 on the gate insulating layer 112, the semiconductor layer 110, and the buffer layer 108. After the second boron doping process BD2, the first region 108a of the non-overlapping top gate 114 of the buffer layer 108 can be transformed into a first region 108d with a higher boron concentration, and the second region 108b of the non-overlapping top gate 114 of the buffer layer 108 can be transformed into a second region 108e with a higher boron concentration. In other words, the boron concentration of the first region 108d is higher than that of the first region 108a, and the boron concentration of the second region 108e is higher than that of the second region 108b. Furthermore, after the second boron doping process BD2, the portion of the semiconductor layer 110 with the overlapping top gate 114 can form a channel region 110c, and the first region 110a and the second region 110b of the semiconductor layer 110 without the overlapping top gate 114 can have a higher boron concentration than the channel region 110c. Additionally, after the second boron doping process BD2, the portion of the gate insulating layer 112 with the overlapping top gate 114 can form an undoped region 112c, and the first region 112a and the second region 112b of the gate insulating layer 112 without the overlapping top gate 114 can have a higher boron concentration than the undoped region 112c.

[0068] Referring to Figure 3F, the top gate 114 can then be used as a mask to perform a doping process IA on the semiconductor layer 110. After the doping process IA, the first region 110a and the second region 110b of the semiconductor layer 110 that do not overlap with the top gate 114 can be transformed into source region 110d and drain region 110e, respectively, and the source region 110d and drain region 110e have lower resistance than the channel region 110c. In some embodiments, the doping process IA is a hydrogen plasma process, and the doping process IA can implant hydrogen elements into the first region 110a and the second region 110b of the semiconductor layer 110, so that the first region 110a and the second region 110b are transformed into source region 110d and drain region 110e with higher hydrogen concentration, respectively. In this way, the source region 110d and drain region 110e can have reduced resistance, so that the thin film transistor 30 has improved Ion and carrier mobility.

[0069] Referring to Figure 3G, an interlayer insulating layer 218 is then formed on the top gate 114 and the gate insulating layer 112. Next, the interlayer insulating layer 218 and the gate insulating layer 112 are patterned to form vias V1 and V2 in the interlayer insulating layer 218 and the gate insulating layer 112, and the vias V1 and V2 expose the source region 110d and the drain region 110e of the semiconductor layer 110, respectively.

[0070] Next, a source electrode 120 is formed on the interlayer insulating layer 218 and in the via V1, and a drain electrode 122 is formed on the interlayer insulating layer 218 and in the via V2, thereby forming a thin-film transistor 30. The source electrode 120 can be electrically connected to the source region 110d through the via V1, and the drain electrode 122 can be electrically connected to the drain region 110e through the via V2, and the source electrode 120 and the drain electrode 122 can form ohmic contacts with the source region 110d and the drain region 110e, respectively. In some embodiments, a passivation layer 124 can also be formed on the source electrode 120, the drain electrode 122, and the interlayer insulating layer 218.

[0071] FIG3G is a schematic cross-sectional view of a thin-film transistor 30 according to an embodiment of the present invention. The thin-film transistor 30 may include a substrate 102, an insulating layer 104, a bottom gate 106, a buffer layer 108, a semiconductor layer 110, a gate insulating layer 112, a top gate 114, an interlayer insulating layer 218, a source 120, a drain 122, and a passivation layer 124.

[0072] Compared with the thin-film transistor 20 shown in Figure 2C, the main difference of the thin-film transistor 30 shown in Figure 3G is that the boron concentration of the first region 108d of the buffer layer 108 of the thin-film transistor 30 is higher than that of the first region 108a of the buffer layer 108 of the thin-film transistor 20, and the boron concentration of the second region 108e of the buffer layer 108 of the thin-film transistor 30 is higher than that of the second region 108b of the buffer layer 108 of the thin-film transistor 20. This is because the boron concentration of the first region 108d and the second region 108a of the buffer layer 108 of the thin-film transistor 30 is higher than that of the first region 108e of the buffer layer 108 of the thin-film transistor 20. Region 108e underwent two boron doping processes, namely the first boron doping process BD1 and the second boron doping process BD2. This avoids the problem of insufficient implantation depth in the boron doping process, ensuring that the first region 108d and the second region 108e of the buffer layer 108 have a sufficiently high boron concentration to prevent oxygen atoms from continuously repairing defects in the source region 110d and drain region 110e of the semiconductor layer 110 during subsequent processes, thereby preventing the resistance of the source region 110d and drain region 110e of the semiconductor layer 110 from increasing.

[0073] In summary, the thin-film transistor of the present invention, by implanting boron atoms into the source and drain regions of the semiconductor layer, can break the covalent bonds between metal atoms and oxygen atoms to eject oxygen atoms. Furthermore, the boron atoms can form stable bonds with the ejected oxygen atoms, thereby generating more oxygen vacancies, thus reducing the resistance of the source and drain regions and improving the Ion and carrier mobility of the thin-film transistor. In addition, the thin-film transistor of the present invention, by implanting boron atoms into the first and second regions of the non-overlapping top gate of the buffer layer, allows the boron atoms to form stable bonds with the extra oxygen atoms (exO) therein, preventing these exO atoms from continuously repairing defects in the source and drain regions of the semiconductor layer during subsequent processes, thereby preventing an increase in the resistance of the source and drain regions and thus preventing a decrease in the Ion and carrier mobility of the thin-film transistor. Furthermore, the undoped region of the overlapping top gate of the buffer layer can still repair defects in the channel region of the semiconductor layer during subsequent processes, thereby improving the reliability of the thin-film transistor.

[0074] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0075] Figures 1A to 1E are schematic cross-sectional views of the steps of a method for fabricating a thin-film transistor according to an embodiment of the present invention. Figures 2A to 2C are schematic cross-sectional views of the steps of a method for fabricating a thin-film transistor according to another embodiment of the present invention. Figures 3A to 3G are schematic cross-sectional views of the steps of a method for fabricating a thin-film transistor according to another embodiment of the present invention.

Claims

1. A thin-film transistor, comprising: A semiconductor layer includes: a source region and a drain region, both boron-doped; a channel region located between the source region and the drain region; and a buffer layer located on one side of the semiconductor layer, comprising: a first region and a second region, both boron-doped and overlapping the source region and the drain region, respectively; and a third region located between the first region and the second region and overlapping the channel region, wherein the third region is undoped.

2. The thin-film transistor as claimed in claim 1, wherein the semiconductor layer comprises a metal oxide semiconductor material.

3. The thin-film transistor of claim 1, wherein the boron concentration in the first region of the buffer layer is higher than the boron concentration in the source region, and the boron concentration in the second region of the buffer layer is higher than the boron concentration in the drain region.

4. The thin-film transistor of claim 1 further includes a bottom gate, wherein the buffer layer is located between the bottom gate and the semiconductor layer.

5. The thin-film transistor of claim 1 further includes a top gate and a gate insulating layer, wherein the gate insulating layer is located on the side of the semiconductor layer opposite to the buffer layer, and the gate insulating layer is located between the channel region of the semiconductor layer and the top gate.

6. The thin-film transistor as claimed in claim 5, wherein the gate insulating layer completely overlaps the channel region of the semiconductor layer.

7. The thin-film transistor as claimed in claim 6, wherein the gate insulating layer is not boron-doped.

8. The thin-film transistor of claim 6 further comprises an interlayer insulating layer that substantially contacts the source region and the drain region of the semiconductor layer, and the interlayer insulating layer is rich in hydrogen.

9. The thin-film transistor of claim 8 further includes a source and a drain, which are electrically connected to the source region and the drain region respectively through the interlayer insulating layer.

10. The thin-film transistor of claim 5, wherein the gate insulating layer overlaps the channel region, the source region, and the drain region of the semiconductor layer.

11. The thin-film transistor of claim 10, wherein the portion of the gate insulating layer overlapping the source region and the drain region is boron-doped.

12. The thin-film transistor of claim 10 further includes an interlayer insulating layer covering the top gate and the gate insulating layer, wherein the gate insulating layer separates the semiconductor layer from the interlayer insulating layer.

13. The thin-film transistor of claim 12 further includes a source and a drain, electrically connected to the source region and the drain region respectively through the interlayer insulating layer and the gate insulating layer.

Images