Forming method of stacking transistor structure

Abstract

A method includes forming a fin over a substrate, the fin comprising lower nanostructures, upper nanostructures, dummy nanostructures, and the dielectric isolation layer disposed between the lower nanostructures and the upper nanostructures; forming a source / drain region adjacent to the fin; forming a recess laterally adjacent to the fin; removing the dummy nanostructures from the fin; forming gate dielectrics around the lower nanostructures and the upper nanostructures; dispensing a directed self-assembly (DSA) material into the recess; exposing the DSA material to a selected ambient, polymer molecules of the DSA material being substantially aligned in the recess; performing a curing process on a lower portion of the DSA material; performing a first etch process to remove an uncured upper portion of the DSA material; doping a dipole dopant into the upper gate dielectrics; and forming a gate electrode around the lower nanostructures and the upper nanostructures.

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