Semiconductor structure and methods of forming the same

Abstract

The disclosure provides a method of forming a semiconductor structure, including forming a gate structure on a substrate, depositing a first dielectric material on the gate structure, performing a first implantation process to implant the substrate with a uniform top surface to form a first doping region in the substrate, performing a second implantation process to implant the substrate with the uniform top surface to form a second doping region in the substrate, depositing a second dielectric material on the first dielectric material, etching a portion of the first dielectric material, the second dielectric material and the substrate to form recesses in the substrate, performing a third implantation process to implant the recesses to form a third doping region in the substrate, and performing an anneal process.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor structure and a method for forming the same. [Previous Technology]

[0002] Due to the reduction in the length of semiconductor structures, implantation processes are used to reduce the hot carrier effect and punch-through effect. However, even tiny depressions on the substrate can affect the distribution and depth of implantation, thereby affecting the performance stability of the semiconductor structure.

[0003] Therefore, a method capable of forming a uniform distribution and depth of implantation is of importance in the art. [Summary of the Invention]

[0004] This disclosure provides a method for forming a semiconductor structure, including forming a gate structure on a substrate, conformally depositing a first dielectric material on the gate structure and the substrate, performing a first implantation process to implant a first dopant into the substrate to form a first doped region in the substrate, wherein the top surface of the substrate is uniform. The method further includes performing a second implantation process to implant a second dopant into the substrate to form a second doped region in the substrate, the second dopant being the opposite of the first dopant, wherein the top surface of the substrate is uniform. The method further includes depositing a second dielectric material on the first dielectric material, etching portions of the first dielectric material, the second dielectric material, and the substrate to form a recess in the substrate, performing a third implantation process to implant a third dopant into the recess in the substrate to form a third doped region in the substrate, wherein the third dopant is the same as the second dopant, and performing an annealing process on the substrate.

[0005] This disclosure provides a semiconductor structure including a gate structure, spacers, a second dielectric layer, a recess, a first doped region, a second doped region, and a third doped region. The gate structure is on a substrate. Each spacer includes a first portion along a sidewall of the gate structure and a second portion on the substrate connecting the endpoints of the first portion. The second dielectric layer is on the spacers and adjacent to the first and second portions. The recess is exposed on the top of the substrate and laterally surrounds the gate structure, the spacers, and the second dielectric layer. The first doped region is in the substrate and has a first doping class, including a width between the top and bottom surfaces of the first doped region ranging from 18.2 nm to 33.8 nm, a distance between the top surface of the first doped region and the top surface of the substrate ranging from 16.1 nm to 23.9 nm, a distance between the bottom surface of the first doped region and the top surface of the substrate ranging from 42.1 nm to 49.9 nm, and a maximum doping concentration at a depth below the top surface of the substrate ranging from 30 nm to 36 nm. The second doped region is located in the substrate below the second portion and has a second doping type opposite to the first doping type. It includes a width between the top and bottom surfaces of the second doped region ranging from 1.6 nm to 2.8 nm, a distance between the top surface of the second doped region and the top surface of the substrate ranging from 1.6 nm to 2.2 nm, a distance between the bottom surface of the second doped region and the top surface of the substrate ranging from 3.8 nm to 4.4 nm, and a maximum doping concentration at a depth below the top surface of the substrate ranging from 2.75 nm to 3.25 nm. A third doped region is located in the substrate below the recess and has a third doping type, wherein the third doped region partially overlaps with the first doped region.

[0006] It should be understood that the foregoing general description and the following detailed description are by way of example and are intended to provide further explanation of the claimed disclosure.

Implementation Method

[0007] Embodiments of the present disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0008] Referring to Figure 1, the method begins with step S10. A substrate 100 is provided. A gate structure 102 is formed on the substrate 100. The gate structure 102 includes a conductive stack 104 and a capping layer 106 on the conductive stack 104. The conductive stack 104 may be a single layer, a double layer, or a multilayer, and the material of the conductive stack 104 may be polycrystalline silicon, copper (Cu), tungsten (W), titanium (Ti), etc. In some embodiments, the conductive stack 104 may include polycrystalline silicon and a metal layer on the polycrystalline silicon. In some embodiments, the gate structure 102 is a high-k dielectric metal gate, and an additional high-k dielectric layer (not shown), such as HfO2, may be formed between the substrate 100 and the conductive stack 104 of the gate structure 102. In some embodiments, the material of the capping layer 106 may include silicon nitride.

[0009] After the gate structure 102 is formed, a first dielectric material 108 is conformally deposited on the substrate 100 and the gate structure 102. The first dielectric material 108 may extend along the top surface and sidewalls of the gate structure 102 and the top surface of the substrate 100. The first dielectric material 108 may be formed by any suitable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc. In some embodiments, the material of the first dielectric material 108 may include silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, low dielectric constant dielectric materials and / or any suitable insulating material to protect the gate structure 102.

[0010] Referring to Figure 2, the method proceeds to step S20. A first implantation process, such as a HALO implantation process, is performed to implant a first dopant species through the first dielectric material 108 onto the substrate 100, and a first doped region 110 is formed in the substrate 100. In some embodiments, a photoresist layer or hard masking layer (not shown) may be formed on the gate structure 102 and prevent the gate structure 102 from being implanted during the first implantation process. The HALO implantation process with angular implantation results in the formed first doped region 110 extending laterally by a distance in the substrate 100 below the gate structure 102. The HALO implantation process may be performed with an angle θ to the sidewalls of the gate structure 102, and the angle θ is from 12˚ to 22˚. In some embodiments, the doping concentration of the first dopant species in the first doped region 110 may be in the range of 1.0E14 cm2 to 8.0E14 cm2.

[0011] It should be noted that the top surface of the substrate 100 remains flat and / or uniform without additional etching processes, and the distribution and depth of the first doped region 110 can be uniform. Furthermore, the first dielectric material 108 along the sidewalls of the gate structure 102 and the top surface of the substrate 100 can be L-shaped rather than irregularly angled, resulting in a uniform distribution of the first doped region 110. In some embodiments, the semiconductor structure has an n-type metal-oxide-semiconductor field-effect transistor (NMOSFET), and the first doping type may include p-type doping, such as boron (B). In some embodiments, the semiconductor structure has a p-type metal-oxide-semiconductor field-effect transistor (PMOSFET), and the first doping type may include n-type doping, such as phosphorus (P).

[0012] Referring to Figure 3, the method proceeds to step S30. A second implantation process, such as a light-doped drain implantation process, is performed to implant a second dopant type into the substrate 100 through the first dielectric material 108, and a second doped region 112 is formed in the substrate 100, the second dopant type being the opposite of the first dopant type. The second doped region 112 in the substrate 100 includes an implantation distribution and dopant type different from the first doped region 110. In some embodiments, a photoresist layer or hard mask layer (not shown) may be formed on the gate structure 102 and prevent the gate structure 102 from being implanted during the second implantation process. The light-doped drain implantation process may be performed perpendicular to the substrate 100. The gate structure 102 may act as a mask such that the second doped region 112 is not located below the gate structure 102. Therefore, the second doped region 112 may be distributed near the top surface of the substrate 100 and around the gate structure 102. In some embodiments, the doping concentration of the second doping type in the second doped region 112 may be in the range of 1.0E15 cm2 to 6.0E15 cm2.

[0013] It should be noted that the top surface of the substrate 100 remains flat and / or uniform without additional etching processes, which can reduce the risk of lateral scattering during lightly doped drain implantation processes, thereby achieving a shallow junction without lateral scattering. In some embodiments, the semiconductor structure has an n-type metal-oxide-semiconductor field-effect transistor (NMOSFET), and the second doping type may include n-type doping, such as phosphorus (P). In some embodiments, the semiconductor structure has a p-type metal-oxide-semiconductor field-effect transistor (PMOSFET), and the second doping type may include p-type doping, such as boron (B).

[0014] A ring implantation process and a lightly doped drain implantation process are employed to prevent the hot carrier effect and punch-through effect. During the operation of the ring implantation process and the lightly doped drain implantation process as described in Figures 2 and 3 of this disclosure, the top surface of the substrate 100 is flat and / or uniform without additional etching processes, resulting in a uniform distribution and depth of doping, further improving the stability of the drain source currents (IDs). Furthermore, performing a lightly doped drain implantation process on such a flat and / or uniform surface of the substrate 100 allows for shallow contact without lateral scattering.

[0015] Referring to Figure 4, the method proceeds to step S40. A second dielectric material 114 is conformally deposited on the first dielectric material 108. The second dielectric material 114 may cover the first dielectric material 108 and the gate structure 102. The second dielectric material 114 can be used to define the distance from the sidewall of the gate structure 102 outward for subsequent source / drain implantation. This distance for subsequent source / drain implantation may vary according to process requirements. The second dielectric material 114 may be formed by any suitable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc. In some embodiments, the second dielectric material 114 may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), high dielectric constant dielectric materials, and / or any suitable dielectric material.

[0016] Referring to Figure 5, the method proceeds to step S50. An etching process is performed to remove portions of the first dielectric material 108 (as shown in Figure 4), the second dielectric material 114 (as shown in Figure 4), and the substrate 100 to form a recess 124 exposed on the top of the substrate 100. Specifically, lateral portions of the first dielectric material 108 and the second dielectric material 114 above the gate structure 102 are removed to expose the top surface of the gate structure 102, and other lateral portions of the first dielectric material 108 and the second dielectric material 114 above the substrate 100 are partially removed to expose portions of the top surface of the substrate 100, thereby forming the recess 124 in the substrate 100 with the exposed top surface. The etching process can be performed by any suitable process, such as dry etching and / or wet etching. In some embodiments, the top surface of the gate structure 102 is coplanar with the top surface of the retained first dielectric material 108. In some embodiments, the recess 124 may have a depth d1 from the top surface S0 of the substrate 100, and the depth d1 is in the range of 6 nm to 10 nm.

[0017] The retained first dielectric material 108 may serve as spacers 116. Each spacer 116 includes a first portion 118 along the sidewall of the gate structure 102 and a second portion 120 along the top surface S0 of the substrate 100 and connecting the endpoints of the first portion 118. In some embodiments, the first portion 118 and the second portion 120 are L-shaped. The retained second dielectric material 114 may serve as a second dielectric layer 122. The second dielectric layer 122 is on the spacers 116 and adjacent to the first portion 118 and the second portion 120 of the spacers 116. The second dielectric layer 122 may also laterally surround the gate structure 102 and the first portion 118 of the spacers 116.

[0018] After the etching process is performed, the recess 124 in the top of the substrate 100 may laterally surround the gate structure 102, the spacer 116, and the second dielectric layer 122. Since the second doped region 112 is located near the top surface S0 of the substrate 100, the formation of the recess 124 may further remove a portion of the second doped region 112, such that the remaining second doped region 112 may be located below the second portion 120 of the spacer 116.

[0019] Referring to Figure 6, the method proceeds to step S60. A third implantation process, such as a source / drain implantation process, is performed to implant a third dopant into the recess 124 in the substrate 100, and a third doped region 126 is formed in the substrate 100. The third dopant is the same as the second dopant. The second dielectric layer 122 and the gate structure 102 can serve as protective layers to prevent the region below the second dielectric layer 122 and the gate structure 102 from being implanted during source / drain implantation. The second dielectric layer 122 can be further defined with a distance D1 to determine the lateral distance between the sidewall of the gate structure 102 and the third doped region 126. The distance D1 can vary according to process requirements. The third doped region 126 can be distributed in the substrate 100 below the recess 124 and laterally surrounds the gate structure 102, the spacer 116, and the second dielectric layer 122. In some embodiments, the doping concentration of the third doping species in the third doping region 126 may be in the range of 2.0E15 cm2 to 9.0E15 cm2.

[0020] It should be noted that the substrate 100 after one etching process (as shown in Figure 5) may include a recess 124 having a slightly uniform bottom surface, which is beneficial for the depth of the source / drain implantation process. In some embodiments, the semiconductor structure has an n-type metal-oxide-semiconductor field-effect transistor (NMOSFET), and the third doping type may include n-type doping, such as phosphorus (P). In some embodiments, the semiconductor structure has a p-type metal-oxide-semiconductor field-effect transistor (PMOSFET), and the third doping type may include p-type doping, such as boron (B).

[0021] Referring to Figure 7, the method proceeds to step S70. An annealing process is performed. After the annealing process, the first doped region 110 may have a top surface S1 and a bottom surface S2, and a width W1 is between the top surface S1 and the bottom surface S2 of the first doped region 110. In some embodiments, for example, the width W1 is in the range of 18.2 nm to 33.8 nm. The first doped region 110 has a distance D3 between the top surface S1 of the first doped region 110 and the top surface S0 of the substrate 100, and the distance D3 is in the range of 16.1 nm to 23.9 nm. The first doped region 110 has a distance D4 between the bottom surface S2 of the first doped region 110 and the top surface S0 of the substrate 100, and the distance D4 is in the range of 42.1 nm to 49.9 nm. Each first doped region 110 has the highest doping concentration at a depth d2 below the top surface S0 of the substrate 100, where depth d2 ranges from 30 nm to 36 nm. The doping concentration of the first doped region 110 gradually decreases from depth d2 to the top surface S1 of the first doped region 110, and also gradually decreases from depth d2 to the bottom surface S2 of the first doped region 110. In some embodiments, for example, the highest doping concentration of the first doped region 110 is at a depth d2 of 33 nm from the top surface S0 of the substrate 100, and the doping distribution of the first doped region 110 may be distributed at a depth ranging from 33 ± 13 nm from the top surface S0 of the substrate 100. In other words, the distance D3 between the top surface S1 of the first doped region 110 and the top surface S0 of the substrate 100 is approximately 20 nm, and the distance D4 between the bottom surface S2 of the first doped region 110 and the top surface S0 of the substrate 100 is approximately 46 nm. The doping concentration of the first doped region 110 gradually decreases from a depth d2 of 33 nm from the top surface S0 of the substrate 100 to the top surface S1 of the first doped region 110 (e.g., at a distance D3 of 20 nm from the top surface S0 of the substrate 100), and the doping concentration of the first doped region 110 gradually decreases from a depth d2 of 33 nm from the top surface S0 of the substrate 100 to the bottom surface S2 of the first doped region 110 (e.g., at a distance D4 of 46 nm from the top surface S0 of the substrate 100). Due to the angular implantation of the ring implantation process, the first doped region 110 extends further by a distance D2 to the region below the gate structure 102. For example, the distance D2 is in the range of 4.3 nm to 18.6 nm from the sidewall of the first portion 118 of the spacer 116.

[0022] After the annealing process, the second doped region 112 may have a top surface S3 and a bottom surface S4, and a width W2 is between the top surface S3 and the bottom surface S4 of the second doped region 112. In some embodiments, for example, the width W2 is in the range of 1.6 nm to 2.8 nm. The second doped region 112 has a distance D5 between the top surface S3 of the second doped region 112 and the top surface S0 of the substrate 100, and the distance D5 is in the range of 1.6 nm to 2.2 nm. The second doped region 112 has a distance D6 between the bottom surface S4 of the second doped region 112 and the top surface S0 of the substrate 100, and the distance D6 is in the range of 3.8 nm to 4.4 nm. Each second doped region 112 has the highest doping concentration at a depth d3 below the top surface S0 of the substrate 100, and the depth d3 is in the range of 2.75 nm to 3.25 nm. The doping concentration of the second doped region 112 gradually decreases from depth d3 to the top surface S3 of the second doped region 112, and also gradually decreases from depth d3 to the bottom surface S4 of the second doped region 112. In some embodiments, for example, the highest doping concentration of the second doped region 112 is at a depth d3 at a distance of 3 nm from the top surface S0 of the substrate 100, and the doping distribution of the second doped region 112 may be distributed at a depth within a range of 3 ± 1.1 nm from the top surface S0 of the substrate 100. In other words, the distance D5 between the top surface S3 of the second doped region 112 and the top surface S0 of the substrate 100 is approximately 1.9 nm, and the distance D6 between the bottom surface S4 of the second doped region 112 and the top surface S0 of the substrate 100 is approximately 4.1 nm. The doping concentration of the second doped region 112 gradually decreases from a depth d3 at a distance of 3 nm from the top surface of the substrate 100 to the top surface S3 of the second doped region 112 (e.g., at a distance D5 at a distance of 1.9 nm from the top surface of the substrate 100), and the doping concentration of the second doped region 112 gradually decreases from a depth d3 at a distance of 3 nm from the top surface of the substrate 100 to the bottom surface S4 of the second doped region 112 (e.g., at a distance D6 at a distance of 4.1 nm from the top surface of the substrate 100).

[0023] After the annealing process, the third doped region 126 may have a top surface S5 and a bottom surface S6, and a width W3 is between the top surface S5 and the bottom surface S6 of the third doped region 126. In some embodiments, for example, the width W3 is in the range of 8 nm to 24 nm. The third doped region 126 has a distance D7 between the top surface S5 of the third doped region 126 and the top surface S0 of the substrate 100, and the distance D7 is in the range of 7.5 nm to 15.5 nm. The third doped region 126 has a distance D8 between the bottom surface S6 of the third doped region 126 and the top surface S0 of the substrate 100, and the distance D8 is in the range of 23.5 nm to 31.5 nm. Each third doped region 126 has the highest doping concentration at a depth d4 below the top surface S0 of the substrate 100, and the depth d4 is in the range of 16 nm to 20 nm. The doping concentration of the third doped region 126 gradually decreases from depth d4 to the top surface S5 of the third doped region 126, and also gradually decreases from depth d4 to the bottom surface S6 of the third doped region 126. In some embodiments, for example, the highest doping concentration of the third doped region 126 is at a depth d4 of 18 nm from the top surface S0 of the substrate 100, and the doping distribution of the third doped region 126 may be distributed at a depth within a range of 18 ± 8 nm from the top surface S0 of the substrate 100. In other words, the distance D7 between the top surface S5 of the third doped region 126 and the top surface S0 of the substrate 100 is approximately 10 nm, and the distance D8 between the bottom surface S6 of the third doped region 126 and the top surface S0 of the substrate 100 is approximately 26 nm. The doping concentration of the third doped region 126 gradually decreases from a depth d4 of 18 nm from the top surface S0 of the substrate 100 to the top surface S5 of the third doped region 126 (e.g., at a distance D7 of 10 nm from the top surface S0 of the substrate 100), and the doping concentration of the third doped region 126 gradually decreases from a depth d4 of 18 nm from the top surface S0 of the substrate 100 to the bottom surface S6 of the third doped region 126 (e.g., at a distance D8 of 26 nm from the top surface S0 of the substrate 100). The first doped region 110 and the third doped region 126 partially overlap.

[0024] The first doped region 110 includes a first doping type, the second doped region 112 includes a second doping type, the second doping type being the opposite of the first doping type, and the third doped region 126 includes a third doping type, the third doping type being the same as the second doping type. In some embodiments, the semiconductor structure has an n-type metal-oxide-semiconductor field-effect transistor (NMOSFET), and the first doped region 110, the second doped region 112, and the third doped region 126 may respectively include p-type doping, n-type doping, and n-type doping. On the other hand, the semiconductor structure has a p-type metal-oxide-semiconductor field-effect transistor (PMOSFET), and the first doped region 110, the second doped region 112, and the third doped region 126 may respectively include n-type doping, p-type doping, and p-type doping.

[0025] Although this disclosure has been described in considerable detail with reference to certain embodiments, other embodiments may also be possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments included herein.

[0026] It will be apparent to those skilled in the art that various modifications and changes can be made to the structure of this disclosure without departing from the scope or spirit of this disclosure. In view of the foregoing, this disclosure is intended to cover modifications and changes to this disclosure that fall within the scope of the appended patent applications. [Simplified Explanation of the Diagram]

[0027] This disclosure can be more fully understood by reading the following embodiments and in conjunction with the detailed description of the accompanying drawings: Figures 1 to 7 are cross-sectional views of manufacturing methods for forming semiconductor devices at various stages according to some embodiments of this disclosure. [Biomaterial Storage]

[0029] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A method for forming a semiconductor structure, comprising: A gate structure is formed on a substrate; A first dielectric material is conformally deposited on the gate structure and the substrate; Perform a first implantation process to implant a first dopant into the substrate to form a first doped region in the substrate, wherein a top surface of the substrate is uniform; perform a second implantation process to implant a second dopant into the substrate to form a second doped region in the substrate, the second dopant being the opposite of the first dopant, wherein the top surface of the substrate is uniform; deposit a second dielectric material on the first dielectric material; etch the first dielectric material, the second dielectric material, and a portion of the substrate to form a plurality of recesses in the substrate; Perform a third implantation process to implant a third dopant into the recesses in the substrate to form a third doped region in the substrate, wherein the third dopant is the same as the second dopant; and perform an annealing process on the substrate.

2. The method as described in claim 1, wherein the first implantation process includes HALO implantation with an angled implantation, and the second implantation process includes light doped drain (LDD).

3. The method as described in claim 2, wherein the angle implantation is performed at an angle to one sidewall of the gate structure, and the angle is between 12˚ and 22˚.

4. The method as described in claim 3, wherein the first doped region extends to a region beneath the gate structure.

5. The method as claimed in claim 1, wherein the doping concentration of the first doping species in the first doped region is in the range of 1.0E14 to 8.0E14 cm2.

6. The method as described in claim 1, wherein the doping concentration of the second doping type in the second doped region is in the range of 1.0E15 to 6.0E15 cm2.

7. The method as claimed in claim 1, wherein the doping concentration of the third doping type in the third doped region is in the range of 2.0E15 to 9.0E15 cm2.

8. The method as described in claim 1, wherein the third implantation process includes source / drain implantation.

9. The method as described in claim 1, wherein etching the first dielectric material, the second dielectric material, and the portion of the substrate to form the recesses in the substrate comprises: Remove a horizontal portion of the first dielectric material and the second dielectric material above a top surface of the gate structure, and partially remove another horizontal portion of the first dielectric material and the second dielectric material on the substrate, thereby exposing the top surface of the gate structure.

10. The method as claimed in claim 1, wherein etching the first dielectric material, the second dielectric material, and the portion of the substrate to form the recesses in the substrate further includes removing a portion of the second doped region.

11. A semiconductor structure, comprising: A gate structure is mounted on a substrate. A plurality of spacers, each spacer comprising: a first portion along a sidewall of the gate structure; and a second portion on the substrate and connected to one end of the first portion; a second dielectric layer on the spacers and adjacent to the first and second portions; a plurality of recesses exposed at a top of the substrate and laterally surrounding the gate structure, the spacers, and the second dielectric layer; a first doped region in the substrate and having a first doping class, comprising: a width between a top surface and a bottom surface of the first doped region, the width being in the range of 18.2 nm to 33.8 nm; a distance between the top surface of the first doped region and a top surface of the substrate, the distance being in the range of 16.1 nm to 23.9 nm; a distance between the bottom surface of the first doped region and the top surface of the substrate, the distance being in the range of 42.1 nm to 49.9 nm; and a maximum doping concentration at a depth below the top surface of the substrate, the depth being in the range of 30 nm to 40 nm. The second doped region is in the range of nm to 36 nm; a second doped region is located in the substrate below the second portion and has a second doped type opposite to the first doped type, comprising: a width between a top surface and a bottom surface of the second doped region, the width being in the range of 1.6 nm to 2.8 nm; a distance between the top surface of the second doped region and the top surface of the substrate, the distance being in the range of 1.6 nm to 2.2 nm; a distance between the bottom surface of the second doped region and the top surface of the substrate, the distance being in the range of 3.8 nm to 4.4 nm; and a maximum doping concentration at a depth below the top surface of the substrate, the depth being in the range of 2.75 nm to 3.25 nm; and a third doped region is located in the substrate below the recesses and has a third doped type, wherein the third doped region partially overlaps with the first doped region.

12. The semiconductor structure of claim 11, wherein a doping concentration of the first doped region gradually decreases from the depth to the top surface of the first doped region; and wherein the doping concentration of the first doped region gradually decreases from the depth to the bottom surface of the first doped region.

13. The semiconductor structure as claimed in claim 11, wherein the recesses are located in the range of 6 nm to 10 nm from the top surface of the substrate.

14. The semiconductor structure as described in claim 11, wherein the third doped region comprises: A width between a top surface and a bottom surface of the third doped region, the width being in the range of 8 nm to 24 nm; a distance between the top surface of the third doped region and the top surface of the substrate, the distance being in the range of 7.5 nm to 15.5 nm; a distance between the bottom surface of the third doped region and the top surface of the substrate, the distance being in the range of 23.5 nm to 31.5 nm; and a maximum doping concentration at a depth below the top surface of the substrate, the depth being in the range of 16 nm to 20 nm.

15. The semiconductor structure as described in claim 11, wherein the first portion and the second portion are L-shaped.

16. The semiconductor structure as claimed in claim 11, wherein the semiconductor structure includes an NMOS transistor, the first doping type includes p-type doping, the second doping type includes n-type doping, and the third doping type includes n-type doping.

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