Foreline for semiconductor processing

Abstract

A semiconductor processing system is provided with a processing chamber defining an interior volume, a plurality of exhaust ports in a bottom of the chamber, and a foreline network fluidically connected to the exhaust ports and the interior volume, configured to receive process gases from the interior volume, and having a first branch extending from a first exhaust port and terminating at a first junction, a second branch extending from a second exhaust port and terminating at the first junction, and a third branch extending from, and downstream of, the first junction and configured to fluidically connect with an exhaust. The third branch is downstream of the first branch, second branch, and the first junction, the first branch, the second branch, and the third branch has aluminum tubing with nickel-plating, and the nickel-plating is on interior surfaces of the first branch, second branch, and third branch.

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