Semiconductor device and method of forming the same

Abstract

The disclosure provides a forming method of a semiconductor device, including providing a substrate with an active area and a terminated area around the active area. The substrate in the active area includes an epitaxy layer and a doped region in a bottom-up direction that is perpendicular to the substrate. A gate trench is formed by etching downward a top surface of the active area, and a bottom surface of the gate trench is lower than a bottom surface of the doped region. A dielectric structure is formed in the gate trench. The dielectric structure includes a bottom layer and a spacer on the bottom layer, and the spacer includes a upwardly protruding profile. The disclosure also provides a semiconductor device.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device and a method for forming the same. [Previous Technology]

[0002] In the manufacturing process of semiconductor devices, oxide needs to be formed at the bottom of the gate trench to reduce gate charge, thereby achieving lower power consumption and higher switching speed. If oxide (e.g., low-pressure tetraethyl orthosilicate, LPTEOS) is directly deposited to fill the gate trench, voids are easily generated in the gate trench. This often requires additional implantation processes to solve the above problems, making the process more complex. [Summary of the Invention]

[0003] This disclosure provides a method for forming a semiconductor device. The method includes providing a substrate, the substrate including an active region and a terminal region, the substrate having an epitaxial layer and a doped region in the active region from bottom to top in a direction perpendicular to the substrate. The method includes etching downward from the top surface of the active region of the substrate to form a gate trench, the bottom surface of the gate trench being lower than the bottom surface of the doped region. The method includes forming a dielectric structure in the gate trench, the dielectric structure including a bottom layer and spacers disposed on the bottom layer, the spacers having an upwardly convex profile.

[0004] This disclosure provides a semiconductor device including a substrate, an epitaxial layer, a first doped region, a second doped region, and a gate structure. The substrate includes an active region and a termination region surrounding the active region. The epitaxial layer is above the substrate and distributed in the active region and the termination region. The first doped region is above the epitaxial layer in the active region. The second doped region is above the epitaxial layer in the termination region. The gate structure is located in the first doped region and a portion of the epitaxial layer, and the gate structure includes a dielectric structure and a conductive structure located above the dielectric structure. The dielectric structure includes a bottom layer and spacers located above the bottom layer, the spacers having a raised profile in a direction perpendicular to the substrate. The bottom layer includes low-pressure tetraethyl orthosilicate (LPTEOS), and the spacers include borophosphosilicate glass (BPSG).

Implementation Method

[0005] Embodiments of the present disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0006] Referring to Figure 1, a substrate 100 is provided. The substrate 100 includes an active area 102 and a termination area 104 surrounding the active area 102. An epitaxial layer 106 is formed over the substrate 100, and the epitaxial layer 106 is distributed in the active area 102 and the termination area 104. In some embodiments, the epitaxial layer 106 may be an n-type doped epitaxial layer. A first doped region 108 is formed on top of the epitaxial layer 106 in the active area 102. The first doped region 108 includes a well region 112 and a source region 110 above the well region 112. The source region 110 may be an n-type doped region. The well region 112 includes a p-type doped region 114 and a heavily p-type doped region 116 located on top of the p-type doped region 114, and the source region 110 covers the p-type doped region 114 and the heavily p-type doped region 116. In some embodiments, the doping concentration of the heavily p-type doped region 116 is greater than that of the p-type doped region 114. In some embodiments, the top surface of the p-type doped region 114 may be coplanar with the top surface of the heavily p-type doped region 116. A second doped region 120 is formed on top of the epitaxial layer 106 of the terminal region 104. The second doped region 120 may serve as a p-type doped guard ring, and the second doped region 120 forms a PN junction with the epitaxial layer 106 to prevent leakage current in the x-direction. In some embodiments, the bottom surface of the second doped region 120 may be coplanar with the bottom surface of the well region 112 in the first doped region 108.

[0007] Referring again to Figure 1, a gate trench 118 is formed in the epitaxial layer 106 of the active region 102. The gate trench 118 extends from the top surface of the first doped region 108 toward the substrate 100 to the epitaxial layer 106. After the gate trench 118 is formed, the top of the gate trench 118 is surrounded in the x-direction by the first doped region 108 and the second doped region 120. In some embodiments, the bottom surface of the gate trench 118 is lower than the bottom surface of the well region 112 of the first doped region 108. In some embodiments, the gate trench 118 can be formed by, for example, reactive ion etching (RIE), wet etching, plasma etching, inductively coupled plasma (ICP) etching, etc.

[0008] Referring to Figure 2, a first oxide layer 122 is conformally deposited on the top surfaces of the epitaxial layer 106, the first doped region 108, and the second doped region 120, as well as in the gate trench 118. The first oxide layer 122 is distributed in the active region 102 and the terminal region 104. The material of the first oxide layer 122 can be, for example, low-pressure tetraethyl orthosilicate (LPTEOS). The thickness of the first oxide layer 122 can be in the range of about 2000 Å to 8000 Å. If the thickness is less than 2000 Å, the thickness of the first oxide layer 122 on the sidewall of the gate trench 118 will be too thin, which may cause phosphorus and boron atoms in the subsequently formed second oxide layer 124 to diffuse to the sidewall of the gate trench 118, thereby affecting the characteristics and reliability of the device. If the thickness exceeds 8000 Å, voids may be formed directly in the gate trench 118, causing subsequent etching to disrupt the underlying 132 architecture of the subsequently formed dielectric structure 136 along these voids. The thickness of the first oxide layer 122 can control the profile of the subsequently formed dielectric structure 136. In some embodiments, the first oxide layer 122 can be conformally formed using deposition methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), low-pressure CVD (LPCVD), and plasma-enhanced chemical vapor deposition (PECVD).

[0009] Referring to Figure 3, a second oxide layer 124 is formed over the first oxide layer 122. The second oxide layer 124 is distributed in the active region 102 and the terminal region 104. The second oxide layer 124 fills the gate trench 118 (as shown in Figure 2) and covers the first oxide layer 122. The material of the second oxide layer 124 can be, for example, borophosphosilicate glass (BPSG). In some embodiments, the second oxide material can be deposited by deposition methods such as CVD, PVD, ALD, electron beam evaporation, etc., and then a planarization process is performed on the second oxide material to form the second oxide layer 124. The planarization process can be chemical mechanical planarization (CMP), anisotropic etching, high temperature thermal reflow, or a combination thereof.

[0010] Referring to Figure 4, a portion of the second oxide layer 124 located above the first oxide layer 122 is removed, such that the second oxide layer 124 retained in the gate trench 118 forms a second oxide 126, and the first oxide layer 122 exposed above the top surfaces of the first doped region 108, the second doped region 120, and the epitaxial layer 106 is made so that the top surfaces of the first oxide layer 122 and the second oxide 126 may be coplanar. In some embodiments, the removal of the second oxide layer 124 may be performed by a wet etching process using an etchant, such as a buffered oxide etch (BOE).

[0011] Referring to Figure 5, a wet etching process is performed to remove a portion of the first oxide layer 122 and a portion of the second oxide layer 126 to form a first oxide 128 and a second oxide 130 in the gate trench 118. A portion of the first oxide layer 122 located above the top surface of the first doped region 108, the second doped region 120, and the epitaxial layer 106, and at the top of the gate trench 118, is removed to form the first oxide 128. A portion of the second oxide 126 at the top of the gate trench 118 is also removed to form the second oxide 130, such that the bottom of the second oxide 130 is surrounded by the first oxide 128. After the wet etching process is completed, the second oxide 130 has an upwardly convex profile in a direction perpendicular to the substrate 100. In some embodiments, the topmost level of the second oxide 130 is higher than the top surface level of the first oxide 128, and the top surface of the first oxide 128 is lower than the bottom surface of the source region 110. In some embodiments, the wet etching process may use, for example, a buffer oxide etchant (BOE).

[0012] Referring to Figure 6, a wet etching process is performed to remove a portion of the first oxide 128 and a portion of the second oxide 130, such that the remaining first oxide 128 and second oxide 130 form a dielectric structure 136 at the bottom of the gate trench 118. The dielectric structure 136 includes a bottom layer 132 and spacers 134 above the bottom layer 132. A portion of the first oxide 128 is removed to form the bottom layer 132, and a portion of the second oxide 130 is removed to form the spacers 134. The top surface of the bottom layer 132 is lower than the bottom surface of the well region 112 of the first doped region 108, and the topmost horizontal plane of the spacers 134 is lower than the bottom surface of the source region 110.

[0013] After wet etching, the spacer 134 may have an upwardly convex profile in a direction perpendicular to the substrate 100 (e.g., the y-direction), and the cross-section of the profile (e.g., the xy-plane) may have a shape including sharp corners, rounded corners, or arcs. The shape of the profile can be controlled by adjusting the thickness of the first oxide layer 122 (as shown in Figure 4). For example, if a thicker first oxide layer 122 (e.g., 3000 Å) is deposited, the spacer 134 may have a sharp-cornered profile. For example, if a thinner first oxide layer 122 (e.g., 2000 Å) is deposited, the spacer 134 may have an arc-shaped (flat) profile.

[0014] Referring to Figure 7, Figure 7 shows an enlarged view of the dielectric structure 136 of region 148 in Figure 6 within the gate trench 118. The gate trench 118 extends downward from the top surface of the active region 102 with a depth D1, and the topmost horizontal surface of the spacer 134 has a dimension D2 with the bottom surface of the gate trench 118. In some embodiments, the dimension D2 can be in the range of about 5000 Å to 10000 Å. If the dimension D2 is too low, it will affect the withstand voltage capability of the device, and the dimension D2 cannot exceed the depth D1. The ratio of dimension D2 to depth D1 can be in the range of 40% to 80%. Furthermore, the bottommost horizontal surface of the top surface of the bottom layer 132 between the sidewalls of the gate trench 118 and the spacer 134 has a dimension D3 with the bottom surface of the gate trench 118. In some embodiments, the ratio of dimension D3 to dimension D2 can be in the range of 60% to 80%. If dimension D3 is too low, it will affect the voltage withstand capability of the component, and dimension D3 cannot exceed dimension D2. Furthermore, the bottom surface of spacer 134 and the bottom surface of gate trench 118 have dimension D4. In some embodiments, the ratio of dimension D4 to dimension D3 can be in the range of 100% to 200%, and dimension D4 cannot be less than dimension D3. In some embodiments, the ratio of dimension D4 to dimension D2 can be in the range of 20% to 80%. On the other hand, gate trench 118 has a width W1 in the direction parallel to substrate 100 (e.g., the x-direction), and the bottom surface of spacer 134 has a width W2 in the direction parallel to substrate 100 (e.g., the x-direction). In some embodiments, the ratio between width W2 and width W1 can be in the range of 50% to 80%. If width W2 is too narrow, it will affect the ability of subsequent gate material to fill the trench, and width W2 cannot exceed width W1.

[0015] Referring to Figure 8, Figure 8 illustrates another embodiment of the dielectric structure 136 of Figure 7. After a portion of the first oxide 128 (as shown in Figure 5) is removed by wet etching, the resulting underlayer 132 has its top surface higher than the bottom surface of the spacer 134 between the sidewalls of the gate trench 118 and the spacer 134. In other words, the underlayer 132 may be the bottom surrounding the spacer 134.

[0016] Referring again to Figure 8, the gate trench 118 extends downward from the top surface of the active region 102 with a depth D5, and the topmost horizontal surface of the spacer 134 has a dimension D6 with the bottom surface of the gate trench 118. In some embodiments, the dimension D6 can be in the range of about 5000 Å to 10000 Å. The ratio of dimension D6 to depth D5 can be in the range of 40% to 80%. The bottommost horizontal surface of the bottom layer 132 of the dielectric structure 136 in the top surface between the sidewall of the gate trench 118 and the spacer 134 has a dimension D7 with the bottom surface of the gate trench 118, and the bottom surface of the spacer 134 has a dimension D8 with the bottom surface of the gate trench 118. In some embodiments, the ratio of dimension D7 to dimension D8 can be in the range of 100% to 200%, and dimension D7 cannot be less than dimension D8. On the other hand, the gate trench 118 has a width W3 in the direction parallel to the substrate 100 (e.g., the x-direction), and the bottom surface of the spacer 134 has a width W4 in the direction parallel to the substrate 100 (e.g., the x-direction). In some embodiments, the ratio between the width W4 and the width W3 can be in the range of 50% to 80%. If the width W4 is too narrow, it will affect the ability of the subsequent gate material to fill the trench, and the width W4 cannot exceed the width W3.

[0017] In some embodiments, the dielectric structure 136 can be formed by depositing only a first oxide material (e.g., LPTEOS) over-filling the gate trench 118 and then removing part of the first oxide material. However, depositing the first oxide material over-filling the gate trench 118 easily forms voids in the gate trench 118, which is undesirable. Therefore, an additional implantation process (e.g., Ar implant) is required to form a specially shaped oxide at the bottom of the gate trench 118. The semiconductor device formation method provided in this disclosure only requires depositing LPTEOS and BPSG in the gate trench 118 and then performing a wet etching process, without performing an additional implantation process to obtain a specially shaped oxide at the bottom of the gate trench 118. Furthermore, the contour of the oxide can be adjusted using LPTEOS.

[0018] Referring to Figure 9, a gate structure 140 is formed in a gate trench 118 (as shown in Figure 6). The gate structure 140 includes a conductive structure 138 and a dielectric structure 136. The conductive structure 138 can be formed by depositing a conductive material to fill the gate trench 118 and then removing a portion of the conductive material located above the top surface of the first doped region 108, the second doped region 120, and the epitaxial layer 106. In some embodiments, the material of the conductive structure 138 can be polysilicon, which can serve as a gate electrode to perform gate switching operations by applying different bias voltages. Because the gate structure 140 includes a dielectric structure 136, the volume of the conductive structure 138, which serves as the gate electrode, is reduced. In some embodiments, the volume ratio of the dielectric structure 136 to the gate structure 140 can be between approximately 20% and 70%, so that the dielectric structure 136 can effectively protect the thin oxide (not shown) located on the sidewall of the gate trench 118 and prevent the component from being damaged. However, if the volume ratio of the dielectric structure 136 to the gate structure 140 is too large, it will compress the size of the upper conductive structure 138, making it impossible for the component to be smoothly controlled by the gate structure 140.

[0019] Next, an insulating layer 142 is formed covering the top surface of the first doped region 108, the second doped region 120, the epitaxial layer 106, and the gate structure 140. The insulating layer 142 is distributed in the active region 102 and the terminal region 104. Next, a plug 144 is formed in the insulating layer 142 of the active region 102. The plug 144 passes through the insulating layer 142 and is connected to the first doped region 108. The plug 144 may be a conductive material such as tungsten (W). After the plug 144 is formed, a source metal layer 146 is formed above the insulating layer 142 of the active region 102. The source metal layer 146 covers the top surface of the insulating layer 142 and the plug 144 in the active region 102, such that the source metal layer 146 is connected to the first doped region 108 through the plug 144.

[0020] Although this disclosure has been described in considerable detail with reference to certain embodiments, other embodiments may also be possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments included herein.

[0021] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of this disclosure without departing from the scope or spirit of the invention. In view of the foregoing, this disclosure is intended to cover modifications and variations of this disclosure that fall within the scope of the appended claims. [Simplified Explanation of the Diagram]

[0022] The present invention can be more fully understood by reading the following detailed description of embodiments in conjunction with the accompanying drawings: Figures 1 to 6 are cross-sectional views of methods for forming a semiconductor device at various stages according to some embodiments of the present disclosure. Figures 7 and 8 are enlarged views of the region in Figure 6 according to some embodiments of the present disclosure. Figure 9 is a cross-sectional view of methods for forming a semiconductor device at various stages according to some embodiments of the present disclosure. [Biomaterial Storage]

[0024] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A method of forming a semiconductor device, comprising: A substrate is provided, the substrate including an active area and a termination area surrounding the active area, the substrate having an epitaxial layer and a doped region in the active area from bottom to top in a direction perpendicular to the substrate; etching downward from a top surface in the active area of ​​the substrate to form a gate trench, a bottom surface of the gate trench being lower than a bottom surface of the doped region; and forming a dielectric structure in the gate trench, the dielectric structure including a bottom layer and a spacer disposed on the bottom layer, the spacer having an upwardly protruding profile.

2. The method as described in claim 1, wherein the method further comprises: A gate structure is formed in the gate trench, wherein the volume ratio of the dielectric structure to the gate structure is in the range of 20% to 70%.

3. The method as described in claim 1, wherein the material of the substrate comprises low-pressure tetraethyl orthosilicate (LPTEOS) and the material of the spacer comprises borophosphosilicate glass (BPSG).

4. The method as described in claim 1, wherein forming the dielectric structure in the gate trench comprises: A first oxide layer is deposited in the gate trench; A second oxide layer is deposited on top of the first oxide layer; And remove a portion of the first oxide layer and a portion of the second oxide layer, wherein the first oxide layer is formed by conformal deposition.

5. The method as described in claim 1, wherein the top surface of the bottom layer is lower than the bottom surface of the doped region.

6. The method as described in claim 1, wherein the profile has a shape including sharp corners, rounded corners, or arcs.

7. The method as described in claim 1, wherein the distance between the topmost horizontal plane of the spacer and the bottom surface of the gate trench is in the range of 5000 Å to 10000 Å.

8. The method as claimed in claim 1, wherein the topmost horizontal plane of the spacer has a dimension with the bottom surface of the gate trench, the gate trench extends downward from the top surface in the active region of the substrate to a depth, and a ratio of the dimension to the depth is in the range of 40% to 80%.

9. The method as claimed in claim 1, wherein the bottommost horizontal plane of the top surface of the bottom layer between the sidewall of the gate trench and the spacer has a first dimension with the bottom surface of the gate trench, and the topmost horizontal plane of the spacer has a second dimension with the bottom surface of the gate trench, wherein a ratio of the first dimension to the second dimension is in the range of 60% to 80%.

10. The method of claim 1, wherein the gate trench has a first width in a direction parallel to the substrate, the bottom surface of the spacer has a second width in the same direction parallel to the substrate, and the ratio of the second width to the first width is in the range of 50% to 80%.

11. The method as claimed in claim 1, wherein the bottommost horizontal plane of the top surface of the bottom layer between the sidewall of the gate trench and the spacer has a first dimension with the bottom surface of the gate trench, and the bottom surface of the spacer has a third dimension with the bottom surface of the gate trench, the third dimension being in a ratio of the first dimension to the third dimension being in the range of 100% to 200%.

12. The method as described in claim 1, wherein the underlying layer further surrounds the bottom of the spacer.

13. The method as claimed in claim 12, wherein the bottommost horizontal plane of the top surface of the bottom layer between the sidewall of the gate trench and the spacer has a fourth dimension with the bottom surface of the gate trench, and the bottom surface of the spacer has a fifth dimension with the bottom surface of the gate trench, wherein the ratio of the fourth dimension to the fifth dimension is in the range of 100% to 200%.

14. A semiconductor device, comprising: A substrate includes an active region and a terminal region surrounding the active region; An epitaxial layer is disposed above the substrate and distributed in the active region and the terminal region; a first doped region is disposed above the epitaxial layer in the active region; and a second doped region is disposed above the epitaxial layer in the terminal region. The system also includes a gate structure located in the first doped region and a portion of the epitaxial layer, the gate structure comprising: a dielectric structure; and a conductive structure located above the dielectric structure, wherein the dielectric structure comprises: a bottom layer; and a spacer located above the bottom layer, having a raised profile in a direction perpendicular to the substrate, wherein the bottom layer comprises low-pressure tetraethyl orthosilicate (LPTEOS), and the spacer comprises borophosphosilicate glass (BPSG).

15. The semiconductor device as claimed in claim 14, wherein the underlying layer has a thickness in the range of 2000 Å to 8000 Å in that direction.

16. The semiconductor device as claimed in claim 14, wherein the topmost horizontal surface of the spacer has a second dimension with the bottom surface of the gate structure, the bottom surface of the spacer has a third dimension with the bottom surface of the gate structure, and the ratio of the third dimension to the second dimension is in the range of 20% to 80%.

Images