Fully isolated super via in wafer stacking structure

TW202638950APending Publication Date: 2026-09-16APPLIED MATERIALS INC
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Patent Information

Application Number
TW114138094
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Priority Date
2025-03-05
Filing Date
2025-10-02
Publication Date
2026-09-16

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Patent Text Reader

Abstract

A method of forming a fully isolated super via in wafer stacking structure includes performing a metal passivation process to passivate exposed sidewalls of bonding pads within a super via formed through a multi-wafer stacking structure with a passivation layer, the multi-wafer stacking structure comprising the bonding pads, bond layer interfaces, dielectric layers encapsulating the bonding pads and the bond layer interfaces, and silicon layers covering the dielectric layers, performing a selective deposition process to form an insulator layer on sidewalls of the silicon layers, the dielectric layers, and the bond layer interfaces within the super via, performing a clean process to remove the passivation layer, and performing a metallization process to fill the super via with contact metal material.
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