Passive device and manufacturing method of the same

Abstract

The present disclosure provides a passive device, comprising: a substrate; a plurality of vias located inside the substrate; wherein each of the plurality of vias comprises at least one metal layer and at least one dielectric layer, the at least one metal layer and the at least one dielectric layer forming at least one metal-dielectric-metal (MIM) structure; wherein the at least one metal layer and the at least one dielectric layer are respectively exposed at at least one end of each of the plurality of vias.

Description

[Technical Field]

[0001] This invention relates to a passive device and its manufacturing method. [Previous Technology]

[0002] Integrated passive components (IPD) and technology, by forming passive components such as capacitors in a substrate, have advantages such as large-area production, small capacitor size, low cost, and good electrical performance, and are therefore widely used in advanced packaging processes. However, when glass is used as the substrate, glass substrates with through glass vias (TGV) are prone to breakage during processing, making processing on glass substrates quite difficult. Therefore, there is a need to improve the manufacturing method of glass substrate integrated passive components. [Summary of the Invention]

[0003] At least one embodiment of the present invention provides a method for manufacturing a passive device, comprising: forming a patterned metal layer on a carrier plate; forming a thin film dielectric layer on the patterned metal layer; forming a thin film metal layer on the thin film dielectric layer; forming a substrate preparation layer on the thin film metal layer; heating the carrier plate to make the substrate preparation layer become a substrate; removing the carrier plate; and planarizing the substrate to expose the patterned metal layer, the thin film dielectric layer, and the thin film metal layer.

[0004] At least one embodiment of the present invention provides a passive device, comprising: a substrate; a plurality of vias located inside the substrate; wherein each of the plurality of vias includes at least one metal layer and at least one dielectric layer, the at least one metal layer and the at least one dielectric layer forming at least one metal-dielectric-metal (MIM) structure; wherein the at least one metal layer and the at least one dielectric layer are exposed at at least one end of each of the plurality of vias.

[0005] Based on the above, by first forming a metal-dielectric-metal (MIM) structure and then forming a glass substrate surrounding the MIM structure by sintering, a glass substrate with a large number of passive components can be manufactured, which has the advantages of easy processing and freely definable size.

Implementation Method

[0006] FIG1 is a schematic diagram of a passive device according to an embodiment of the present invention. Please refer to FIG1. ​​The passive device 100 includes: a substrate 118 and a plurality of vias V.

[0007] In this embodiment, the substrate 118 is made of glass, but this is not a limitation. The thickness of the substrate 118 is less than 200 μm, and the thickness of the substrate 118 can be changed according to actual needs, and this disclosure is not limited thereto.

[0008] Multiple vias V are located inside the substrate 118. As shown in FIG1, multiple vias V are distributed on the substrate 118, and each via V has the same structure. In this embodiment, the diameter D of each via V is 5μm to 100μm, but can be changed as needed, and this disclosure is not limited thereto. In this embodiment, the spacing P between adjacent vias V is 10μm to 500μm, but can be changed as needed, and this disclosure is not limited thereto.

[0009] As shown in Figure 1, each of the vias V includes a columnar structure 112, at least one thin-film metal layer 116 and at least one thin-film dielectric layer 114.

[0010] The columnar structure 112 is made of metal and extends to both ends of the via V. In some embodiments, the columnar structure 112 is made of copper or other conductive metals, and this disclosure is not limited thereto. In some embodiments, the shape of the columnar structure includes a cylinder or a square column, or a columnar structure with a cross-section of other shapes, and this disclosure is not limited thereto.

[0011] A thin-film dielectric layer 114 is formed on the columnar structure 112, i.e., the side surface of the columnar structure of the metal layer 112. In this embodiment, the thin-film dielectric layer 114 has one layer, but in other embodiments, the thin-film dielectric layer 114 may have multiple layers, such as two, three or more layers, and this disclosure is not limited thereto. In some embodiments, the material of the thin-film dielectric layer 114 may be a high dielectric constant (High-K) material such as HfO, Al2O3, ZrO, or Ta2O5, and this disclosure is not limited thereto. In some embodiments, the thickness of the thin-film dielectric layer 114 may be 1 to 5000 mm, and this disclosure is not limited thereto.

[0012] A thin-film metal layer 116 is formed on a thin-film dielectric layer 114. In this embodiment, the thin-film metal layer 116 has one layer, but in other embodiments, the thin-film metal layer 116 may have multiple layers, such as two, three, or more layers, and this disclosure is not limited thereto. When the number of thin-film dielectric layer 114 and thin-film metal layer 116 is more than one, the thin-film dielectric layer 114 and thin-film metal layer 116 are formed alternately. In some embodiments, the material of the thin-film metal layer 116 may be copper or other conductive metals, and this disclosure is not limited thereto. In some embodiments, the thickness of the thin-film metal layer 116 may be 0.1 μm to 2 μm, and this disclosure is not limited thereto.

[0013] As shown in FIG. 1, the thin-film metal layer 116 and the thin-film dielectric layer 114 form part of a metal-insulator-metal (MIM) structure. Specifically, in this embodiment, the metal layer 112, the thin-film dielectric layer 114, and the thin-film metal layer form a MIM structure, which can be used as a passive component, such as a capacitor. In this embodiment, the via V includes at least one MIM structure, such as a MIM structure formed by the metal layer 112, the thin-film dielectric layer 114, and the thin-film metal layer. In some embodiments, when multiple thin-film metal layers 116 and multiple thin-film dielectric layers 114 are alternately arranged, multiple MIM structures can be formed.

[0014] In some embodiments, the thin-film metal layer 116 and the thin-film dielectric layer 114 are exposed at at least one end of the via V to increase the convenience of connecting to the wiring structure located on the surface of the passive device 100. As shown in FIG1, portions of the thin-film metal layer 116 and the thin-film dielectric layer 114 are exposed at the upper and lower ends of the via V.

[0015] Figures 2A to 2I are schematic diagrams of a method for manufacturing a passive device according to an embodiment of the present invention.

[0016] Please refer to Figure 2A. A carrier plate 102 is provided. An adhesive layer 104, a first seed layer 106, and a second seed layer 108 are sequentially formed on the carrier plate 102.

[0017] In some embodiments, the carrier plate 102 can be made of high-temperature resistant materials such as silicon, metal, and gallium arsenide, and its size can be square or round, such as 320x400mm2, 510x515mm2, 600x600mm2, or 800x800mm2. This disclosure is not limited to this.

[0018] Adhesive layer 104 is disposed on carrier plate 102. In some embodiments, adhesive layer 104 may be a light-to-heat conversion (LTHC) layer. The LTHC layer may be a solvent-based coating applied using a spin coating method. The LTHC layer can convert ultraviolet light into heat, which can cause the material of the LTHC layer to lose its adhesiveness. Alternatively, adhesive layer 104 may contain a thermally degradable adhesive material. For example, adhesive layer 104 may contain an acrylic pressure-sensitive adhesive that decomposes at high temperatures. The peel temperature of the thermally degradable adhesive material may be in the range of 1500°C to 2000°C.

[0019] A first seed layer 106 is disposed on the adhesive layer 104, and a second seed layer 108 is disposed on the first seed layer 106 to facilitate subsequent electroplating processes on the carrier plate 102. In some embodiments, the material of the first seed layer 106 may be titanium or molybdenum, and the material of the second seed layer 108 may be copper. In some embodiments, the first seed layer 106 and the second seed layer 108 may be selectively added, for example, excluding the first seed layer 106 and the second seed layer 108, or including only one of the first seed layer 106 and the second seed layer 108, or including both the first seed layer 106 and the second seed layer 108; this disclosure is not limited thereto.

[0020] Please refer to FIG. 2B. A patterned photoresist layer 110 is formed on a second seed layer 108 on a carrier plate 102. Specifically, a photoresist layer 110 is formed on the second seed layer 108, and the photoresist layer 110 is subjected to an exposure process to pattern the photoresist layer 110. After the exposure process, a development process is performed to remove unwanted portions of the photoresist layer 110 to form the patterned photoresist layer 110. In some embodiments, the photoresist thickness of the photoresist layer 110 can be 50 μm, 100 μm, or 200 μm, but other thicknesses are also possible as needed, and this disclosure is not limited thereto. In some embodiments, the photoresist layer 110 can be formed on the second seed layer 108 by vacuum lamination, spin coating, or other methods, and this disclosure is not limited thereto. In some embodiments, the material of the photoresist layer 110 can be g-line, h-line, or i-line photoresist. In some embodiments, the material of the photoresist layer 110 can be dry film photoresist or wet film photoresist, and this disclosure is not limited thereto. In some embodiments, the patterned photoresist layer 110 has a plurality of openings with a diameter between 5 μm and 100 μm. The spacing between adjacent openings can be between 10 μm and 500 μm. In some embodiments, the pattern of the plurality of openings is not limited to cylinders or square pillars, and may include wire structures.

[0021] Please refer to FIG. 2C. A patterned metal layer 112 is formed in a patterned photoresist layer 110 on a carrier substrate 102. Specifically, the patterned metal layer 112 is formed on a second seed layer 108 and in a plurality of openings within the patterned photoresist layer 110. In some embodiments, the patterned metal layer 112 includes a plurality of columnar structures and / or conductive structures. In some embodiments, the material of the patterned metal layer 112 is copper. In some embodiments, the patterned metal layer 112 is formed by electroplating, but this disclosure is not limited thereto.

[0022] Please refer to FIG2D. The patterned photoresist layer 110 is removed. In some embodiments, the patterned photoresist layer 110 can be removed by an ashing process, a stripping process or other suitable process.

[0023] Please refer to FIG. 2E. A thin film dielectric layer 114 is formed on the patterned metal layer 112. The thin film dielectric layer 114 covers the second seed layer 108. In some embodiments, the material of the thin film dielectric layer 114 can be a high-k dielectric material such as HfO, Al2O3, ZrO, or Ta2O5. In some embodiments, the thin film dielectric layer 114 can be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable processes, and the thickness can be 1 to 5000 nm.

[0024] Please refer to Figure 2F. A thin film metal layer 116 is formed on the thin film dielectric layer 114. In some embodiments, the material of the thin film metal layer 116 may be copper. In some embodiments, the thin film metal layer 116 may be formed by sputtering or chemical plating, and the thickness may be 0.1 μm - 2 μm.

[0025] In some embodiments, the steps of FIG2E and FIG2F may be repeated to form a multilayer thin film dielectric layer 114 and a thin film metal layer 116.

[0026] Please refer to FIG. 2G. A substrate preparation layer 118' is formed on the thin film metal layer 116. In some embodiments, the material of the substrate preparation layer 118' can be glass glue, glass film, glass powder or other glass materials. In some embodiments, the material of the substrate preparation layer 118' is formed on the thin film metal layer 116 by coating or pressing. Wherein, after coating or pressing, the thickness of the substrate preparation layer 118' needs to be greater than the thickness of the patterned photoresist layer 110 in FIG. 2B, so as to completely cover the thin film metal layer 116.

[0027] The carrier plate 102 is heated to transform the substrate preparation layer 118' into the substrate 118. Specifically, by heating the carrier plate 102, the glass adhesive, glass film, glass powder, or other glass material of the substrate preparation layer 118' is sintered. During the sintering process, the temperature must be greater than 7000°C. When the temperature is greater than 9000°C, the substrate preparation layer 118' will sinter into a glass ceramic. The sintering time of the substrate preparation layer 118' is at least 2 hours. After sintering, it is cooled, and the substrate preparation layer 118' becomes the substrate 118 made of glass.

[0028] Please refer to Figure 2H. Remove the carrier plate 102. Specifically, the adhesive layer 104 is de-adhesive by means of light or heat, so that the carrier plate 102 is separated from the first seed layer 106.

[0029] Please refer to FIG. 2I. The substrate 118 is planarized to expose the patterned metal layer 112. Both sides of the substrate 118 are planarized to remove portions of the substrate 118, as well as the first seed layer 106 and the second seed layer 108, so that the patterned metal layer 112 is exposed on both sides of the substrate 118. Furthermore, the thin-film dielectric layer 114 and the thin-film metal layer 116 are exposed on at least one side of the substrate 118, respectively. In some embodiments, the method for planarizing the substrate 118 includes, but is not limited to, chemical mechanical polishing (CMP), etching, or polishing. FIG. 2I yields the passive device 100 shown in FIG. 1.

[0030] The passive device 100 shown in FIG1, fabricated according to the steps of FIG2A to FIG2I, can form a glass substrate integrated passive element with a large number of vias. Each via includes at least one metal-dielectric-metal (MIM) structure, such as metal layer 112, thin film dielectric layer 114, and thin film metal layer 116.

[0031] FIG3 is a schematic diagram of another passive device according to an embodiment of the present invention. Please refer to FIG3. Passive device 100B is similar to passive device 100 of FIG1. ​​The difference is that, as shown in FIG3, each of the vias V includes a columnar structure 113, at least two thin film metal layers 116A, 116B, and at least one thin film dielectric layer 114.

[0032] In this embodiment, the columnar structure 113 is made of a dielectric material and extends to both ends of the via V. In some embodiments, the material of the columnar structure 113 may be a high-dielectric-constant (High-K) material such as HfO, Al2O3, ZrO, or Ta2O5, and this disclosure is not limited thereto. In some embodiments, the shape of the columnar structure includes a cylinder or a square column, or a columnar structure with other cross-sectional shapes, and this disclosure is not limited thereto.

[0033] Thin film metal layer 116A, thin film dielectric layer 114, and thin film metal layer 116B are sequentially formed on the side surface of columnar structure 113. The materials and formation methods of thin film metal layers 116A and 116B are the same as those of thin film metal layer 116, and will not be described again here. By combining thin film metal layer 116A, thin film dielectric layer 114, and thin film metal layer 116B, a MIM structure can be formed to serve as a passive component, such as a capacitor.

[0034] FIG4 is a schematic diagram of another passive device according to an embodiment of the present invention. Please refer to FIG4. The passive device 100C shown in FIG4 is similar to the passive device 100B shown in FIG3. The difference is that the columnar structure 113 includes a metal wire 115, which is located within the columnar structure 113 and connected to the first thin film metal layer 116. In some embodiments, the metal wire 115 is made of copper, and therefore the metal wire 115 is sometimes referred to as a copper bridge. The metal wire 115 can be located at any position in the columnar structure 113.

[0035] FIG5 is a schematic diagram of another passive device according to an embodiment of the present invention. Please refer to FIG5. As shown in FIG5, in addition to the substrate 224, the metal columnar structure 218 in the via V, the thin film dielectric layers 220A, 220B, and the thin film metal layers 222A, 222B, the two ends of the via V are further connected to wires (seed layer 206, metal layer 210, seed layer 226, and metal layer 230) to control the passive element, such as a capacitor, formed in the via V by the metal columnar structure 218, the thin film dielectric layer 220A, 220B, and the thin film metal layers 222A, 222B.

[0036] The following describes the manufacturing method of the passive device 200.

[0037] Figures 6A to 6S are schematic diagrams of another method for manufacturing a passive device according to an embodiment of the present invention.

[0038] Please refer to Figure 6A. A carrier plate 202 is provided. An adhesive layer 204 and a seed layer 206 are sequentially formed on the carrier plate 202.

[0039] In some embodiments, the carrier plate 202 can be made of high-temperature resistant materials such as silicon, metal, gallium arsenide, etc., and the size can be square or round, such as 320x400mm2, 510x515mm2, 600x600mm2, 800x800mm2, etc. This disclosure is not limited to this.

[0040] Adhesive layer 204 is disposed on carrier plate 202. In some embodiments, adhesive layer 204 may be a light-to-heat conversion (LTHC) layer. The LTHC layer may be a solvent-based coating applied using a spin coating method. The LTHC layer can convert ultraviolet light into heat, which can cause the material of the LTHC layer to lose its adhesiveness. Alternatively, adhesive layer 204 may contain a thermally degradable adhesive material. For example, adhesive layer 204 may contain an acrylic pressure-sensitive adhesive that decomposes at high temperatures. The peel temperature of the thermally degradable adhesive material may be in the range of 1500°C to 2000°C.

[0041] The seed layer 206 is disposed on the adhesive layer 204 to facilitate subsequent electroplating processes on the carrier plate 202. In some embodiments, the material of the seed layer 206 may be titanium, molybdenum, or copper. In some embodiments, the seed layer 206 may be a single-layer or multi-layer structure. In some embodiments, the seed layer 206 may be selectively added, for example, the seed layer 206 may not be included, and this disclosure is not limited thereto.

[0042] Please refer to FIG. 6B. A patterned photoresist layer 208 is formed on the seed layer 206. Specifically, a photoresist layer is formed on the seed layer 206, and an exposure process is performed on the photoresist layer to pattern the photoresist layer 208. After the exposure process, a development process is performed to remove unwanted portions of the photoresist layer 208 to form the patterned photoresist layer 208. In some embodiments, the photoresist layer 208 may be formed on the seed layer 206 by vacuum lamination, spin coating, etc., and this disclosure is not limited thereto. In some embodiments, the material of the photoresist layer 208 may be g-line, h-line, or i-line photoresist. In some embodiments, the material of the photoresist layer 208 may be dry film photoresist or wet film photoresist, and this disclosure is not limited thereto.

[0043] Please refer to FIG6C. A metal layer 210 is formed in the photoresist layer 208 and on the seed layer 206. In this embodiment, the material of the metal layer 210 is copper. In some embodiments, the metal layer 210 is formed by electroplating, but this disclosure is not limited thereto.

[0044] Please refer to Figure 6D. Remove the photoresist layer 208 and etch the seed layer 206 using the metal layer 210 as an etching mask. In some embodiments, the photoresist layer 208 can be removed by an ashing process, a stripping process, or other suitable processes. In some embodiments, the seed layer 206 can be etched by a dry etching process, a wet etching process, or other suitable processes.

[0045] Please refer to FIG. 6E. An insulating layer 212 is formed on the adhesive layer 204, which may be silicon nitride, silicon carbide nitride, silicon oxide, or silicon oxynitride, etc., and the insulating layer 212 surrounds the seed layer 206 and the metal layer 210. In some embodiments, the insulating layer 212 is formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable processes.

[0046] Please refer to FIG. 6F. A seed layer 214 is formed on the metal layer 210 and the insulating layer 212. In some embodiments, the material of the seed layer 214 may be titanium, molybdenum, or copper. In some embodiments, the seed layer 214 may be selectively added, for example, the seed layer 214 may not be included, and this disclosure is not limited thereto.

[0047] Please refer to FIG. 6H. A photoresist layer 216 is formed on the seed layer 214, and the photoresist layer 216 is subjected to an exposure process to pattern the photoresist layer 216. After the exposure process, a development process is performed to remove unwanted portions of the photoresist layer 216 to form a patterned photoresist layer 216. In some embodiments, the photoresist thickness of the photoresist layer 216 can be 50 μm, 100 μm, or 200 μm, but other thicknesses are also possible as needed, and this disclosure is not limited thereto. In some embodiments, the photoresist layer 216 can be formed on the seed layer 214 by vacuum lamination, spin coating, or other methods, and this disclosure is not limited thereto. In some embodiments, the material of the photoresist layer 216 can be g-line, h-line, or i-line photoresist. In some embodiments, the material of the photoresist layer 216 can be dry film photoresist or wet film photoresist, and this disclosure is not limited thereto. In some embodiments, the patterned photoresist layer 216 has multiple openings with a diameter between 5 μm and 100 μm. The spacing between adjacent openings can be between 10 μm and 500 μm. In some embodiments, the pattern of the multiple openings is not limited to cylinders or square prisms, and may include wire structures.

[0048] Please refer to FIG. 6H. A patterned metal layer 218 is formed in the patterned photoresist layer 216. Specifically, the patterned metal layer 218 is formed on the seed layer 214 and in a plurality of openings within the patterned photoresist layer 216. In some embodiments, the patterned metal layer 218 includes a plurality of columnar structures and / or conductive structures. In some embodiments, the material of the patterned metal layer 218 is copper. In some embodiments, the patterned metal layer 218 is formed by electroplating, but this disclosure is not limited thereto.

[0049] Please refer to FIG6I. Remove the photoresist layer 216 and etch the seed layer 214 using the patterned metal layer 218 as an etching mask. In some embodiments, the photoresist layer 216 can be removed by an ashing process, a stripping process, or other suitable processes. In some embodiments, the seed layer 214 can be etched by a dry etching process, a wet etching process, or other suitable processes.

[0050] Please refer to Figure 6J. A thin film dielectric layer 220A is formed on the patterned metal layer 218. The thin film dielectric layer 220A surrounds the side surface of the seed layer 214 and covers the upper surface of the metal layer 210 and the upper surface of the insulating layer 212. In some embodiments, the material of the thin film dielectric layer 220A can be a high-k dielectric material such as HfO, Al2O3, ZrO, or Ta2O5. In some embodiments, the thin film dielectric layer 220A can be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable processes, and its thickness can be 1~5000 nm.

[0051] Please refer to Figure 6K. A thin film metal layer 222A is formed on the thin film dielectric layer 220A. In some embodiments, the material of the thin film metal layer 222A may be copper. In some embodiments, the thin film metal layer 222A may be formed by sputtering or chemical plating, and the thickness may be 0.1 μm-2 μm.

[0052] Please refer to Figure 6L. Repeat the steps of Figures 6J and 6K to sequentially form a thin film dielectric layer 220B and a thin film metal layer 222B on the thin film metal layer 222A.

[0053] In some embodiments, the steps of FIG6L may be repeated to form a multilayer thin film dielectric layer and a thin film metal layer.

[0054] Please refer to FIG. 6M. A substrate preparation layer 224' is formed on the thin film metal layer 222B. In some embodiments, the material of the substrate preparation layer 224' can be glass glue, glass film, glass powder or other glass materials. In some embodiments, the material of the substrate preparation layer 224' is formed on the thin film metal layer 222B by coating or pressing. Wherein, after coating or pressing, the thickness of the substrate preparation layer 224' needs to be greater than the thickness of the patterned photoresist layer 216 in FIG. 6H, so as to completely cover the thin film metal layer 222B.

[0055] The carrier plate 202 is heated to transform the substrate preparation layer 224' into the substrate 224. Specifically, by heating the carrier plate 202, the glass adhesive, glass film, glass powder, or other glass material of the substrate preparation layer 224' is sintered. During the sintering process, the temperature must be greater than 7000°C. When the temperature is greater than 9000°C, the substrate preparation layer 224' will sinter into a glass ceramic. The sintering time of the substrate preparation layer 224' is at least 2 hours. After sintering, it is cooled, and the substrate preparation layer 224' becomes the substrate 224, which is made of glass.

[0056] Please refer to Figure 6N. The substrate 224 is planarized to expose the patterned metal layer 218. In addition to exposing the patterned metal layer 218, portions of the thin film dielectric layer 220A, thin film metal layer 222A, thin film dielectric layer 220B, and thin film metal layer 222B are also exposed.

[0057] In some embodiments, the method of planarizing the substrate 224 includes chemical mechanical polishing (CMP), etching or polishing, but is not limited thereto.

[0058] Please refer to FIG. 60. A seed layer 226 is formed on the substrate 224 to cover the patterned metal layer 218, thin film dielectric layer 220A, thin film metal layer 222A, thin film dielectric layer 220B, and thin film metal layer 222B. In some embodiments, the material of the seed layer 226 may be titanium, molybdenum, or copper. In some embodiments, the seed layer 226 may be selectively added, for example, the seed layer 226 may not be included, and this disclosure is not limited thereto.

[0059] Please continue to refer to FIG. 60. Next, a patterned photoresist layer 228 is formed on the seed layer 226. Specifically, a photoresist layer 228 is formed on the seed layer 226, and an exposure process is performed on the photoresist layer 228 to pattern it. After the exposure process, a development process is performed to remove unwanted portions of the photoresist layer 228 to form the patterned photoresist layer 228. In some embodiments, the photoresist layer 228 may be formed on the seed layer 226 by vacuum lamination, spin coating, etc., and this disclosure is not limited thereto. In some embodiments, the material of the photoresist layer 228 may be g-line, h-line, or i-line photoresist. In some embodiments, the material of the photoresist layer 228 may be dry film photoresist or wet film photoresist, and this disclosure is not limited thereto.

[0060] Please refer to Figure 6P. A metal layer 230 is formed in the photoresist layer 228 and on the seed layer 226. In this embodiment, the material of the metal layer 230 is copper. In some embodiments, the metal layer 230 is formed by electroplating, but this disclosure is not limited thereto.

[0061] Please refer to Figure 6Q. Remove the photoresist layer 228 and etch the seed layer 226 using the metal layer 230 as an etching mask. In some embodiments, the photoresist layer 228 can be removed by an ashing process, a stripping process, or other suitable processes. In some embodiments, the seed layer 206 can be etched by a dry etching process, a wet etching process, or other suitable processes.

[0062] Please continue to refer to FIG. 6Q. An insulating layer 232 is formed on substrate 224, the insulating layer 232 surrounding seed layer 226 and metal layer 230. In some embodiments, the insulating layer 232 is formed by chemical vapor deposition (CVD), atomic layer deposition (ALD) or other suitable processes.

[0063] Please continue to refer to Figure 6Q. Planarization of metal layer 230 and insulating layer 232. Methods for planarizing metal layer 230 and insulating layer 232 include, but are not limited to, chemical mechanical polishing (CMP), etching or polishing.

[0064] Please refer to Figure 6R. Remove the carrier plate 202. Specifically, the adhesive layer 204 is de-adhesive by means of light or heat, so that the carrier plate 202 is separated from the seed layer 206.

[0065] Please continue to refer to Figure 6S. Planarization of seed layer 206 and insulating layer 212. Methods for planarizing seed layer 206 and insulating layer 212 include, but are not limited to, chemical mechanical polishing (CMP), etching or polishing.

[0066] The passive device 200 shown in FIG5, fabricated according to the steps of FIG6A to FIG6S, can form a glass substrate integrated passive element having a surface conductive structure (e.g., metal layer 210, seed layer 214, seed layer 226, metal layer 230). The substrate 224 has a large number of vias, and each via includes at least one metal-dielectric-metal (MIM) structure, such as metal layer 218, thin film dielectric layer 220A, and thin film metal layer 222A.

[0067] In summary, by first forming a metal-dielectric-metal (MIM) structure and then forming a glass substrate surrounding the MIM structure by sintering, the present invention can produce a glass substrate with a large number of passive components, which has the advantages of easy processing and freely definable size. [Simplified Explanation of the Diagram]

[0068] FIG1 is a schematic diagram of a passive device according to an embodiment of the present invention. FIG2A to FIG2I are schematic diagrams of a method for manufacturing a passive device according to an embodiment of the present invention. FIG3 is a schematic diagram of another passive device according to an embodiment of the present invention. FIG4 is a schematic diagram of another passive device according to an embodiment of the present invention. FIG5 is a schematic diagram of another passive device according to an embodiment of the present invention. FIG6A to FIG6S are schematic diagrams of a method for manufacturing another passive device according to an embodiment of the present invention.

Claims

1. A method for manufacturing a passive device, comprising: A patterned metal layer is formed on the carrier plate; A thin dielectric layer is formed on the patterned metal layer; A thin-film metal layer is formed on the thin-film dielectric layer; A substrate preparation layer is formed on the thin-film metal layer; the carrier plate is heated to turn the substrate preparation layer into a substrate; Remove the carrier plate; and planarize the dielectric layer to expose the patterned metal layer, the thin-film dielectric layer, and the thin-film metal layer.

2. The manufacturing method as described in claim 1, wherein, The step of forming the patterned metal layer on the carrier plate further includes: forming a seed layer on the carrier plate, and forming the patterned metal layer on the seed layer.

3. The manufacturing method as described in claim 1, wherein, The step of forming the patterned metal layer on the carrier further includes: forming a patterned photoresist layer on the carrier, and forming the patterned metal layer in the patterned photoresist layer.

4. The manufacturing method as described in claim 1, wherein, The patterned metal layer includes multiple columnar structures and / or conductive structures.

5. The manufacturing method as claimed in claim 1, wherein the shape of the plurality of columnar structures includes a cylinder, a square column, or an elliptical column.

6. A passive device, comprising: substrate; Multiple vias are located inside the substrate; Each of the plurality of vias includes at least one metal layer and at least one dielectric layer, the at least one metal layer and the at least one dielectric layer forming at least one metal-dielectric-metal (MIM) structure; wherein the at least one metal layer and the at least one dielectric layer are exposed at at least one end of each of the plurality of vias; wherein each of the plurality of vias includes a columnar structure, the columnar structure being the innermost layer of the at least one metal layer and the at least one dielectric layer; wherein the columnar structure is made of a dielectric material; and a first metal layer of the at least one metal layer is formed on the side surface of the columnar structure.

7. The passive device as claimed in claim 6, wherein the columnar structure includes a metal wire located within the columnar structure and connected to the first metal layer.

8. The passive device as claimed in claim 6, wherein the diameter of each of the plurality of vias is 5 μm to 100 μm.

9. The passive device as described in claim 6, wherein the spacing between adjacent vias of the plurality of vias is 10 μm to 500 μm.

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