Electronic package and manufacturing method thereof

Abstract

An electronic package is provided with a strengthening layer on an non-active surface of an electronic component embedded in an encapsulating layer, so that the strengthening layer is bonded to an insulating protective layer on a surface of the encapsulating layer, thereby improving the bonding between the electronic component and the insulating protective layer. Therefore, it can effectively avoid the delamination problem to ensure a normal electrical conduction between a conductive element on the insulating protective layer and TSV of an interposer embedded in the encapsulating layer.

Description

[Technical Field]

[0001] This invention relates to a semiconductor packaging technology, and more particularly to an electronic package that can improve reliability and its manufacturing method. [Previous Technology]

[0002] In order to ensure the continued miniaturization and multifunctionality of electronic products and communication equipment, semiconductor packaging needs to develop towards miniaturization to facilitate multi-pin connections, high-speed operation, and high functionality. For example, in advanced process packaging, commonly used packaging types include fan-out wiring combined with embedded component processes.

[0003] Figure 1A is a cross-sectional schematic diagram of a conventional semiconductor package 1a. As shown in Figure 1A, the conventional semiconductor package 1a includes: a cover layer 15, a bridging chip 11 embedded in the cover layer 15, an intermediate chip 12 embedded in the cover layer 15, a plurality of conductive pillars 13 embedded in the cover layer 15, a plurality of functional chips 16 disposed on one surface 15b of the cover layer 15, and a plurality of solder balls 19 disposed on the other surface 15a of the cover layer 15. Any two functional chips 16 are electrically bridged to each other by an electrode pad 110 on the working surface 11a of the bridging chip 11, and any two functional chips 16 are electrically bridged to each other by a conductive via 120 of the intermediate chip 12.

[0004] However, in the conventional method of manufacturing semiconductor package 1a, before implanting the solder balls 19, a leveling process of the surface 15a of the cladding layer 15 is required. At this time, the difference between the materials to be removed is too large. For example, semiconductor materials (bridging wafer 11 and intermediate wafer 12), insulating materials (cladding layer 15) and copper materials (conductive pillars 13 and conductive vias 120) are not easy to grind, resulting in uneven grinding surfaces (for example, the surface of the intermediate wafer 12, the end face of the conductive via 120, the surface 15a of the cladding layer 15, the end face of the conductive pillar 13 and the surface of the bridging wafer 11 are not flush). This results in an uneven grinding surface, which is not conducive to the subsequent alignment and bonding of the solder balls 19, and thus causes poor reliability and yield of the semiconductor package 1a.

[0005] Furthermore, the back side 11b of the bridging chip 11 has no circuit structure, thus forming a dummy area. Its silicon material is different from the material of the insulating protective layer 14 used to position the solder ball 19, resulting in poor bonding between the bridging chip 11 and the insulating protective layer 14. This makes it easy for the two to delaminate, so the solder ball 19 is prone to misalignment or falling off, resulting in poor reliability and yield of the semiconductor package 1a.

[0006] Therefore, in order to solve the problem of the solder ball 19 being misaligned or falling off, the industry has added a circuit structure 112 to the back side 11b of the bridging chip 11, as shown in FIG1B, so as to take advantage of the easy bonding characteristics of metal materials to bond the solder ball 19 to the circuit structure 112.

[0007] However, the circuit structure 112 is made of copper, which causes the back side 11b of the bridging chip 11 to lose its passivation effect, resulting in copper migration. Therefore, electrical short circuits are likely to occur between the electrode pads 110 on the working surface 11a of the bridging chip 11, causing the electrical function of the bridging chip 11 to malfunction, resulting in poor reliability and yield of the semiconductor package 1.

[0008] Furthermore, as shown in Figure 1B, the semiconductor package 1b still has the problem that the uneven grinding surface is not conducive to the alignment and bonding of the solder balls 19.

[0009] Therefore, how to overcome the various problems of the aforementioned conventional technologies has become a pressing issue that the industry urgently needs to address. [Summary of the Invention]

[0010] In view of the various deficiencies of the prior art, the present invention provides an electronic package comprising: a cover layer having opposing first and second surfaces; an electronic component embedded in the cover layer as a bridging element, having opposing active and non-active surfaces, the active surface facing the second surface of the cover layer and having a plurality of electrode pads; an intermediate element embedded in the cover layer as a bridging element and having a plurality of conductive vias; and a protective layer embedded in the first surface of the cover layer and bonded to the non-active surface of the electronic component, and not placed on the intermediate element.

[0011] The present invention also provides a method for manufacturing an electronic package, comprising: providing an electronic module, comprising: a cover layer having opposing first and second surfaces, an electronic component embedded in the cover layer as a bridging element, and an intermediate element embedded in the cover layer as a bridging element, wherein the electronic component has opposing active and non-active surfaces, and the active surface faces the second surface of the cover layer and has a plurality of electrode pads, and the intermediate element has a plurality of conductive vias, and a protective layer embedded in the first surface of the cover layer is disposed on the non-active surface of the electronic component and the intermediate element; and performing a leveling process on the first surface of the cover layer to remove the protective layer on the intermediate element while retaining the protective layer on the electronic component.

[0012] In the aforementioned electronic package and its manufacturing method, an insulating protective layer with a plurality of openings is formed on the first surface of the protective layer and the covering layer, so as to form a plurality of conductive blind holes in the plurality of openings for connecting a plurality of conductive components.

[0013] In the aforementioned electronic package and its manufacturing method, an insulating protective layer with a plurality of openings is provided on the first surface of the intermediate element and the covering layer, so that the plurality of openings correspond to the plurality of conductive through holes, and a conductive blind hole electrically connected to the conductive through hole is formed in each of the openings for connecting conductive elements.

[0014] In the aforementioned electronic package and its manufacturing method, a wiring structure is provided on the first surface of the protective layer and the covering layer.

[0015] In the aforementioned electronic package and its manufacturing method, the intermediate element and the first surface of the covering layer are provided with a wiring structure that electrically connects the plurality of conductive through holes.

[0016] In the aforementioned electronic package and its manufacturing method, the width of the conductive through hole is greater than 11 micrometers.

[0017] In the aforementioned electronic package and its manufacturing method, the width of the conductive through hole is less than 11 micrometers.

[0018] In the aforementioned electronic package and its manufacturing method, a circuit structure electrically connecting the electrode pad is provided on the second surface of the covering layer and the functional surface of the electronic component. For example, a plurality of functional elements are provided on the circuit structure so that the electronic component and / or the intermediate element are electrically bridged to the plurality of functional elements through the circuit structure.

[0019] In the aforementioned electronic package and its manufacturing method, a passivation structure is formed on the intermediate element to cover the ends of the plurality of conductive through holes, and the end faces of the plurality of conductive through holes are exposed in the passivation structure.

[0020] As can be seen from the above, the electronic package and its manufacturing method of the present invention mainly utilize the provision of a protective layer embedded in the first surface of the coating layer on both the non-functional surface of the electronic component and the intermediate component. This reduces the difference in material to be removed during the leveling process of the first surface of the coating layer. Therefore, compared with the prior art, the present invention can avoid the problem of uneven grinding surface and form a flat grinding surface, which is beneficial to the subsequent alignment and bonding of the conductive component, thereby improving the reliability and yield of the electronic package.

[0021] Furthermore, the non-functional surface of the electronic component has no circuit structure, so it does not cause the conventional copper migration problem. Therefore, compared with the conventional technology, the present invention can effectively avoid the problem of electrical short circuit, so as to ensure the normal electrical function of the electronic component, thereby improving the reliability and yield of the electronic package.

[0022] Furthermore, although the non-functional surface of the electronic component has no circuit structure, the protective layer can improve the bonding between the electronic component and the insulating protective layer. Therefore, compared with the prior art, the present invention can effectively avoid the problem of delamination, so as to ensure normal electrical conduction between the conductive component and the conductive via, thereby improving the reliability and yield of the electronic package. [Simplified Explanation of the Diagram]

[0089] Figure 1A is a cross-sectional schematic diagram of a conventional semiconductor package.

[0090] Figure 1B is a cross-sectional schematic diagram of another conventional semiconductor package.

[0091] Figures 2A to 2C are cross-sectional schematic diagrams of the manufacturing method of the first embodiment of the electronic package of the present invention.

[0092] Figures 3A to 3F are cross-sectional schematic diagrams of the manufacturing method of the second embodiment of the electronic package of the present invention.

Implementation Method

[0023] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0024] It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings of this specification are only used to complement the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention. At the same time, the terms such as "above," "first," "second," and "a" used in this specification are only for the convenience of description and are not intended to limit the scope of the present invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the present invention.

[0025] Figures 2A to 2C are cross-sectional schematic diagrams of the manufacturing method of the first embodiment of the electronic package 2 of the present invention.

[0026] As shown in FIG2A, an electronic module 2a is provided, which includes: a covering layer 25, at least one electronic component 21, at least one intermediate component 22, at least one conductive post 23, a circuit structure 20, and at least one functional component 26.

[0027] The coating layer 25 has a first surface 25a and a second surface 25b opposite to each other.

[0028] In this embodiment, the coating layer 25 is an insulating material, such as polyimide (PI), dry film, or an encapsulating compound such as epoxy resin. For example, the coating layer 25 can be formed by liquid compounding, injection, lamination, or compression molding.

[0029] The electronic component 21 is embedded in the covering layer 25. The electronic component 21 is an active component, a passive component, or a combination of both. The active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor.

[0030] In this embodiment, the electronic component 21 is a semiconductor wafer with opposing active surfaces 21a and non-active surfaces 21b. The active surface 21a faces the second surface 25b and has a plurality of electrode pads 210 to bond and electrically connect a plurality of conductors 212, and the conductors 212 are covered with a protective film 211, such as a passivation material. For example, the conductors 212 may be spherical, such as conductive lines or solder balls, or columnar, such as copper pillars or solder bumps, or stud conductive parts made by wire bonding machines, but are not limited to these.

[0031] Furthermore, a protective layer 28a is disposed on the non-functional surface 21b of the electronic component 21, which is embedded in the first surface 25a of the cladding layer 25. For example, the protective layer 28a is in the form of a die-attach film (DAF) and is exposed on the first surface 25a of the cladding layer 25.

[0032] The intermediate element 22 is a semiconductor material such as silicon substrate, which has at least one conductive through-hole 220, such as a conductive silicon through-hole (TSV).

[0033] In this embodiment, the conductive via 220 has a large diameter, with a width D (as shown in Figure 2B) greater than 11 micrometers (µm). The conductive via 220 has a contact 223 on one side of the end face of the intermediate element 22 to connect and electrically link a plurality of conductors 222, and the conductors 222 are covered with a protective film 221, such as a passivation material. For example, the conductors 222 may be spherical, such as conductive lines or solder balls, or columnar, such as copper pillars or solder bumps, or stud conductive parts made by wire bonding machines, but are not limited to these.

[0034] Furthermore, a protective layer 28b is disposed on the other side of the intermediary element 22, embedded in the first surface 25a of the cover layer 25. For example, the protective layer 28b is in the form of a die attach film (DAF), which covers the other end face of the conductive via 220 and is exposed on the first surface 25a of the cover layer 25.

[0035] It should be understood that the conductive perforation 220 has many forms, such as being covered with insulating material, and there are no particular restrictions.

[0036] The conductive post 23 is embedded in the covering layer 25, and the material forming the conductive post 23 is a metal such as copper or solder.

[0037] In this embodiment, one end face of the conductive post 23 is exposed on the first surface 25a of the covering layer 25.

[0038] The circuit structure 20 is disposed on the second surface 25b of the covering layer 25 and electrically connects the conductive post 23 and the conductor 212, 222.

[0039] In this embodiment, the circuit structure 20 includes a plurality of dielectric layers 200 and a circuit layer 201 disposed on the dielectric layers 200, such as a redistribution layer (RDL) specification. The outermost dielectric layer 200 can serve as a solder resist layer, and the outermost circuit layer 201 is exposed on the solder resist layer to serve as an electrical contact pad. Alternatively, the circuit structure 20 may also include only a single dielectric layer 200 and a single circuit layer 201.

[0040] Furthermore, the material forming the circuit layer 201 is copper, and the material forming the dielectric layer 200 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or a solder resist such as green paint or ink.

[0041] The functional element 26 is disposed on the outermost layer of the circuit structure 20 and electrically connected to the circuit layer 201, such that the cladding layer 25, conductive pillar 23, electronic component 21 and intermediate element 22 are disposed on one side of the circuit structure 20, and the functional element 26 is disposed on the other side. The functional element 26 is an active element, a passive element or a combination of both, and the active element is, for example, a semiconductor chip, while the passive element is, for example, a resistor, a capacitor and an inductor.

[0042] In this embodiment, the functional element 26 is a semiconductor wafer, which is electrically connected to the circuit layer 201 via a plurality of conductive bumps 260 in a flip-chip manner, and then the conductive bumps 260 are covered with a primer 261; or, the functional element 26 can also be electrically connected to the circuit layer 201 by a plurality of bonding wires (not shown); or, the functional element 26 can directly contact the circuit layer 201. If the functional element 26 is a passive element, it can be electrically connected to the circuit layer 201 via conductive bumps 260. It should be understood that there are no particular limitations on the method by which the functional element 26 is electrically connected to the circuit layer 201.

[0043] Furthermore, the circuit structure 20 is provided with a plurality of the functional elements 26, and the electronic element 21 and / or the intermediate element 22 can be used as a bridge die so that the electronic element 21 and / or the intermediate element 22 are electrically connected to the circuit layer 201 of the circuit structure 20 via the conductors 212, 222, so as to electrically bridge the plurality of functional elements 26.

[0044] Furthermore, an encapsulation layer 27 can be formed on the outermost layer of the circuit structure 20 to cover the functional element 26 and the base adhesive 261. If the encapsulation layer 27 covers the conductive bumps 260, then the base adhesive 261 does not need to be formed. For example, the encapsulation layer 27 is an insulating material, such as polyimide (PI), dry film, epoxy resin, epoxy resin encapsulant, or molding compound, which can be formed by lamination or molding. It should be understood that the material of the covering layer 25 and the encapsulation layer 27 can be the same or different.

[0045] In addition, the encapsulation layer 27 may cover the top surface of the functional element 26. Alternatively, as required, the outer surface of the encapsulation layer 27 may be flush with the top surface of the functional element 26, so that the top surface of the functional element 26 is exposed by the encapsulation layer 27.

[0046] As shown in FIG2B, a leveling process is performed on the first surface 25a of the covering layer 25 to remove the protective layer 28b on the intermediate element 22, while retaining the protective layer 28 on the electronic component 21, so that the conductive via 220 is exposed to the intermediate element 22, and the intermediate element 22 and its conductive via 220 are exposed to the first surface 25a of the covering layer 25. The thickness of the protective layer 28a is different from the thickness of the protective layer 28b (that is, the thickness of the electronic component 21 is different from the thickness of the intermediate element 22), wherein the thickness of the protective layer 28a on the electronic component 21 is greater than the thickness of the protective layer 28b on the intermediate element 22.

[0047] In this embodiment, a leveling process is performed to remove a portion of the material of the protective layer 28b on the intermediary element 22, a portion of the material of the first surface 25a of the covering layer 25, a portion of the material of the conductive pillar 23, and a portion of the material of the protective layer 28a on the electronic component 21, so that the outer surface of the intermediary element 22, the end face of the conductive via 220, the first surface 25a of the covering layer 25, the end face of the conductive pillar 23, and the outer surface of the protective layer 28 on the electronic component 21 are flush. For example, the leveling process is performed by grinding to thin the protective layer 28 on the electronic component 21.

[0048] It should be understood that there are many removal methods that can be used in this leveling process, and it is not limited to grinding.

[0049] As shown in FIG2C, a plurality of conductive elements 29 electrically connected to the conductive pillars 23 and the conductive through-holes 220 are formed on the first surface 25a of the covering layer 25.

[0050] In this embodiment, the conductive element 29 is a solder ball or a metal bump such as a copper bump. For example, the conductive element 29 is a C4 type solder ball, so that the electronic package 2 is attached to an electronic device such as a circuit board (not shown) by means of the conductive elements 29.

[0051] Furthermore, an insulating protective layer 24 with a plurality of openings 240 can be formed on the first surface 25a of the covering layer 25, and the openings 240 expose the protective layer 28, the conductive pillars 23 and the conductive through holes 220. Then, a plurality of conductive blind holes (vias) 241 are formed in the openings 240 to connect the plurality of conductive elements 29.

[0052] Therefore, the manufacturing method of this embodiment mainly utilizes the fact that a protective layer 28a is provided on the non-functional surface 21b of the electronic component 21, embedded in the first surface 25a of the covering layer 25, and a protective layer 28b is also provided on the intermediate element 22, embedded in the first surface 25a of the covering layer 25. This ensures that the difference in materials to be removed during the leveling process of the first surface 25a of the covering layer 25 is smaller, for example, the difference between insulating materials (covering layer 25 and protective layers 28a, 28b) and copper materials (…). The conductive post 23 is easy to grind, so compared with the prior art, the manufacturing method of this embodiment can effectively avoid the problem of uneven grinding surface, so as to form a flat grinding surface (for example, the outer surface of the intermediate element 22, the end face of the conductive through hole 220, the first surface 25a of the covering layer 25, the end face of the conductive post 23 and the outer surface of the protective layer 28 on the electronic component 21 are flush), which is beneficial to the subsequent alignment and bonding of the conductive element 29, thereby improving the reliability and yield of the electronic package.

[0053] Furthermore, a protective layer 28 is provided on the non-functional surface 21b of the electronic component 21, so the conventional copper migration problem will not occur. Therefore, compared with the conventional technology, the manufacturing method of this embodiment can effectively avoid the problem of electrical short circuit, so as to ensure the normal electrical function of the electronic component 21, thereby improving the reliability and yield of the electronic package 2.

[0054] Furthermore, the protective layer 28 can effectively improve the bonding between the electronic component 21 and the insulating protective layer 24. Therefore, compared with the prior art, the manufacturing method of this embodiment can effectively avoid the problem of delamination, so as to ensure normal electrical conduction between the conductive component 29 and the conductive through-hole 220 (or the conductive post 23), thereby improving the reliability and yield of the electronic package 2.

[0055] Figures 3A to 3F are cross-sectional schematic diagrams of the manufacturing method of the second embodiment of the electronic package 3 of the present invention. The difference between this embodiment and the first embodiment lies in the specifications of the intermediate element 32, so the similarities will not be repeated below.

[0056] As shown in Figure 3A, an electronic module 3a is provided, which is generally as shown in Figure 2A. The main difference is that the conductive through-hole 320 of the intermediate element 32 is of a small diameter and its width R is less than 11 micrometers (um).

[0057] As shown in FIG3B, a leveling process as shown in FIG2B is performed to remove the protective layer 28b on the intermediary element 32 so that the conductive through-hole 320 is exposed on the intermediary element 32 and the intermediary element 32 is exposed on the first surface 25a of the covering layer 25, wherein the surface of the intermediary element 32, the first surface 25a of the covering layer 25, the end face of the conductive post 23 and the outer surface of the protective layer 28 of the electronic component 21 are flush.

[0058] As shown in FIG3C, a recess S is formed on the intermediate element 32, so that the end of the conductive through hole 320 protrudes from the bottom surface of the recess S.

[0059] In this embodiment, the recess S is formed by etching silicon material, but the method of forming the recess S is not limited to the above.

[0060] As shown in FIG3D, a passivation structure 32a is formed in the recess S to cover the end of the conductive through hole 320, and the end face of the conductive through hole 320 is exposed in the passivation structure 32a.

[0061] In this embodiment, the passivation structure 32a includes at least one or more passivation layers 321, 322. For example, the passivation layers 321, 322 are oxide layers or nitride layers, such as silicon nitride (SiN) and / or silicon oxide (SiO2), but are not limited to the above.

[0062] Furthermore, the process of the passivation structure 32a can first form at least one passivation layer 321, 322 on the first surface 25a of the covering layer 25, the end face of the conductive pillar 23, the protective layer 28 and the wall and bottom surfaces of the recess S, and then remove the passivation layers 321, 322 on the first surface 25a of the covering layer 25, the end face of the conductive pillar 23, the protective layer 28 and the wall surfaces of the recess S, leaving only the passivation layers 321, 322 on the bottom surface of the recess S. For example, by using a leveling process, a portion of the material of the first surface 25a of the coating layer 25 and its passivation layers 321, 322, a portion of the material of the conductive pillar 23 and its passivation layers 321, 322, and a portion of the material of the protective layer 28 and its passivation layers 321, 322 are removed by grinding, so that the surface of the passivation structure 32a, the first surface 25a of the coating layer 25, the end face of the conductive pillar 23 and the outer surface of the protective layer 28 on the electronic component 21 are flush, so that the passivation structure 32a and the end face of its conductive through-hole 320 are exposed on the first surface 25a of the coating layer 25.

[0063] It should be understood that there are many ways to manufacture the passivation structure 32a, and it is not limited to the above.

[0064] As shown in FIG3E, a wiring structure 34 is formed on the first surface 25a of the covering layer 25, so that the wiring structure 34 is electrically connected to the conductive post 23 and the conductive through-hole 320 of the intermediate element 32.

[0065] In this embodiment, the wiring structure 34 includes at least one insulating layer 340 and a wiring layer 341 disposed on the insulating layer 340 and electrically connecting the conductive post 23 and the conductive via 320. For example, in a redistribution layer (RDL) specification, the outermost insulating layer 340 can serve as a solder resist layer, and the outermost wiring layer 341 is exposed on the solder resist layer to serve as an electrical contact pad 342. Alternatively, the wiring structure 34 may also include only a single insulating layer 340 and a single wiring layer 341.

[0066] Furthermore, the material forming the wiring layer 341 is copper, and the material forming the insulating layer 340 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or a solder resist such as green paint or ink.

[0067] As shown in FIG3F, a plurality of conductive elements 29 electrically connected to the wiring layer 341 are formed on each of the electrical contact pads 342, so that the electronic package 3 is connected to an electronic device (not shown) such as a circuit board through the conductive elements 29.

[0068] In this embodiment, the conductive element 29 is a C4 type solder ball, and a bump under metal layer (UBM) 290 for bonding the conductive element 29 can be formed on the electrical contact pad 342.

[0069] Therefore, the manufacturing method of this embodiment mainly utilizes the fact that a protective layer 28a is embedded in the first surface 25a of the covering layer 25 on the non-functional surface 21b of the electronic component 21, and a protective layer 28b is also embedded in the first surface 25a of the covering layer 25 on the intermediate element 32, so that the difference in materials to be removed during the leveling process of the first surface 25a of the covering layer 25 is small, such as the difference between insulating material (covering layer 25 and protective layers 28a, 28b) and copper material (conductive pillar 23). Because it is easy to grind, the manufacturing method of this embodiment can effectively avoid the problem of uneven grinding surface compared with the prior art, so as to form a flat grinding surface (for example, the outer surface of the intermediary element 32, the end face of the conductive through hole 320, the first surface 25a of the covering layer 25, the end face of the conductive post 23 and the outer surface of the protective layer 28 on the electronic component 21 are flush, as shown in FIG3B). This is beneficial to the subsequent alignment and bonding of the wiring structure 34 and the conductive element 29, thereby improving the reliability and yield of the electronic package.

[0070] Furthermore, the non-functional surface 21b of the electronic component 21 is provided with a protective layer 28, so the conventional copper migration problem will not occur. Therefore, compared with the conventional technology, the manufacturing method of this embodiment can effectively avoid the problem of electrical short circuit, so as to ensure the normal electrical function of the electronic component 21, thereby improving the reliability and yield of the electronic package 3.

[0071] Furthermore, the protective layer 28 can improve the bonding between the electronic component 21 and the insulating layer 340 of the wiring structure 34. Therefore, compared with the prior art, the manufacturing method of this embodiment can effectively avoid the problem of delamination, so as to ensure normal electrical conduction between the wiring layer 341 of the wiring structure 34 and the conductive via 220 (or the conductive post 23), thereby improving the reliability and yield of the electronic package 3.

[0072] The present invention further provides an electronic package 2,3, which includes: a cover layer 25, at least one electronic component 21 embedded in the cover layer 25, at least one intermediate component 22,32 embedded in the cover layer 25, and a protective layer 28 embedded in the cover layer 25.

[0073] The coating layer 25 has a first surface 25a and a second surface 25b opposite to each other.

[0074] The electronic component 21 is a bridging element, having an active surface 21a and a non-active surface 21b, and the active surface 21a faces the second surface 25b of the covering layer 25 and has a plurality of electrode pads 210.

[0075] The intermediate elements 22 and 32 are used as bridging elements and have at least one through conductive via 220 or 320.

[0076] The protective layer 28 is embedded in the first surface 25a of the covering layer 25 and bonded to the non-functional surface 21b of the electronic component 21, but is not provided on the intermediate components 22, 32.

[0077] In one embodiment, an insulating protective layer 24 with a plurality of openings 240 is provided on the first surface 25a of the protective layer 28 and the covering layer 25, so as to form a plurality of conductive blind holes 241 in the plurality of openings 240 for connecting a plurality of conductive elements 29.

[0078] In one embodiment, an insulating protective layer 24 with a plurality of openings 240 is provided on the first surface 25a of the intermediate element 22 and the covering layer 25, so that the plurality of openings 240 correspond to the conductive through hole 220, and a conductive blind hole 241 electrically connected to the conductive through hole 220 is formed in the opening 240 for connecting the conductive element 29.

[0079] In one embodiment, a wiring structure 34 is provided on the first surface 25a of the protective layer 28 and the covering layer 25.

[0080] In one embodiment, the intermediate element 32 and the first surface 25a of the covering layer 25 are provided with a wiring structure 34 that is electrically connected to the conductive through hole 320.

[0081] In one embodiment, the width D of the conductive via 220 is greater than 11 micrometers.

[0082] In one embodiment, the width R of the conductive via 320 is less than 11 micrometers.

[0083] In one embodiment, a circuit structure 20 electrically connecting the electrode pad 210 is provided on the second surface 25b of the covering layer 25 and the working surface 21a of the electronic component 21. For example, a plurality of functional elements 26 are provided on the circuit structure 20 so that the electronic component 21 and / or the intermediate elements 22, 32 are electrically bridged to the plurality of functional elements 26 through the circuit structure 20.

[0084] In one embodiment, a passivation structure 32a is formed on the intermediate element 32 to cover the end of the conductive through hole 320, and the end face of the conductive through hole 320 is exposed in the passivation structure 32a.

[0085] In summary, the electronic package and its manufacturing method of the present invention are based on the provision of a protective layer (with different thicknesses) embedded on the first surface of the cover layer on both the non-functional surface of the electronic component and the intermediate component. This reduces the difference in material to be removed during the leveling process of the first surface of the cover layer. Therefore, the present invention can effectively avoid the problem of uneven grinding surface and form a flat grinding surface, which is beneficial to the subsequent alignment and bonding of the conductive component, thereby improving the reliability and yield of the electronic package.

[0086] Furthermore, the non-functional surface of the electronic component is provided with a protective layer, so the conventional copper migration problem will not occur. Therefore, the present invention can effectively avoid the problem of electrical short circuit, so as to ensure the normal electrical function of the electronic component, thereby improving the reliability and yield of the electronic package.

[0087] Furthermore, the protective layer can improve the bonding between the electronic component and the insulating protective layer. Therefore, the present invention can effectively avoid the problem of delamination, so as to ensure normal electrical conduction between the conductive component and the conductive via, thereby improving the reliability and yield of the electronic package.

[0088] The above embodiments are illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as set forth in the following patent claims.

Claims

1. An electronic package, comprising: The coating layer has a first surface and a second surface that are opposite to each other; An electronic component is embedded in the cladding layer as a bridging element and has opposing active and non-active surfaces, with the active surface facing the second surface of the cladding layer; an intermediate element is embedded in the cladding layer as a bridging element and has a plurality of conductive vias; and a protective layer is embedded in the first surface of the cladding layer and bonded to the non-active surface of the electronic component, but not placed on the intermediate element. An insulating protective layer with a plurality of openings is formed on the first surface of the protective layer and the cladding layer, and a plurality of conductive blind vias are formed in the plurality of openings for connecting a plurality of conductive elements.

2. The electronic package as described in claim 1, wherein, The insulating protective layer is also formed on the intermediate element, the plurality of openings correspond to the plurality of conductive vias, and the plurality of conductive blind vias are electrically connected to the plurality of conductive vias.

3. The electronic package as described in claim 1, wherein, The width of the conductive via is greater than 11 micrometers.

4. An electronic package, comprising: The coating layer has a first surface and a second surface that are opposite to each other; An electronic component is embedded in the cladding layer as a bridging element and has opposing active and non-active surfaces, with the active surface facing the second surface of the cladding layer; an intermediate element is embedded in the cladding layer as a bridging element and has a plurality of conductive vias, wherein a passivation structure is formed on the intermediate element to cover the ends of the plurality of conductive vias, and the end faces of the plurality of conductive vias are exposed on the passivation structure; and a protective layer is embedded in the first surface of the cladding layer and bonded to the non-active surface of the electronic component, and is not placed on the intermediate element.

5. The electronic package as described in claim 4, wherein, A wiring structure is provided on the first surface of the protective layer and the covering layer.

6. The electronic package as described in claim 4, wherein, The intermediate element and the first surface of the cladding layer are provided with a wiring structure that electrically connects the plurality of conductive vias.

7. The electronic package as described in claim 4, wherein, The width of the conductive via is less than 11 micrometers.

8. The electronic package as described in claim 4, wherein, The second surface of the coating layer and the working surface of the electronic component are provided with a circuit structure that electrically connects the electronic component.

9. The electronic package as described in claim 8, wherein, The circuit structure is provided with multiple functional elements so that the electronic components and / or the intermediate components can be electrically bridged to the multiple functional elements through the circuit structure.

10. A method for manufacturing an electronic package, comprising: An electronic module is provided, comprising: a cover layer having opposing first and second surfaces, an electronic component embedded in the cover layer as a bridging element, and an intermediary element embedded in the cover layer as a bridging element, wherein the electronic component has opposing active and non-active surfaces, the active surface facing the second surface of the cover layer, and the intermediary element has a plurality of conductive vias, and the non-active surfaces of the electronic component and the intermediary element are disposed with protective layers embedded in the first surface of the cover layer; and a leveling process is performed on the first surface of the cover layer to remove the protective layer on the intermediary element while retaining the protective layer on the electronic component.

11. The method for manufacturing an electronic package as described in claim 10, wherein, An insulating protective layer with a plurality of openings is provided on the first surface of the protective layer and the covering layer on the electronic component, so as to form a plurality of conductive blind holes in the plurality of openings for connecting a plurality of conductive components.

12. The method for manufacturing an electronic package as described in claim 10, wherein, An insulating protective layer with a plurality of openings is formed on the first surface of the intermediary element and the covering layer, and the plurality of openings correspond to the plurality of conductive through holes, and conductive blind holes electrically connected to the conductive through holes are formed in each of the openings for connecting conductive elements.

13. The method for manufacturing an electronic package as described in claim 10, wherein, A wiring structure is provided on the first surface of the protective layer and the covering layer of the electronic component.

14. The method for manufacturing an electronic package as described in claim 10, wherein, The intermediate element and the first surface of the cladding layer are provided with a wiring structure that electrically connects the plurality of conductive vias.

15. The method for manufacturing an electronic package as described in claim 10, wherein, The width of the conductive via is greater than 11 micrometers.

16. The method for manufacturing an electronic package as described in claim 10, wherein, The width of the conductive via is less than 11 micrometers.

17. The method for manufacturing an electronic package as described in claim 10, wherein, The second surface of the coating layer and the working surface of the electronic component are provided with a circuit structure that electrically connects the electronic component.

18. The method for manufacturing an electronic package as described in claim 17, wherein, The circuit structure is provided with multiple functional elements so that the electronic components and / or the intermediate components can be electrically bridged to the multiple functional elements through the circuit structure.

19. The method for manufacturing an electronic package as described in claim 10, wherein, The intermediate element has a passivation structure that covers the ends of the plurality of conductive vias, and the end faces of the plurality of conductive vias are exposed in the passivation structure.

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