Semiconductor package module and method of manufacturing the same

Abstract

A semiconductor package module includes two redistribution layers, two electronic components, an adhesive material, an encapsulation layer and a conductive pillars. The electronic components are located between two redistribution layers, and the adhesive material is disposed between the electronic components. The electronic components and the adhesive material are stacked on each other in the normal direction of one of the redistribution layers, and the active surfaces of the electronic components face the redistribution layers separately. The encapsulation layer is disposed between two redistribution layers and covers the electronic components. The conductive pillar is connected to the redistribution layers and extends from one redistribution layer to the other redistribution layer through the encapsulation layer. The first part and the second part of the conductive pillar are connected to two redistribution layers separately. The interface between the first part and the second part is flush with the plane of the adhesive material.

Description

Technical Field

[0001] This invention relates to a semiconductor packaging module and its manufacturing method. Prior Technology

[0002] Today's mobile and wearable devices, such as laptops, smartphones, and smartwatches, are all trending towards miniaturization. However, the size of these electronic devices is limited by the size of the semiconductor packaging modules inside. To meet the miniaturization trend of mobile and wearable devices, the design of existing semiconductor packaging modules also needs to be improved. Summary of the Invention

[0003] At least one embodiment of the present invention provides a semiconductor packaging module that helps to reduce the size of mobile devices and wearable devices.

[0004] At least one embodiment of the present invention also provides a method for manufacturing the above-mentioned semiconductor packaging module.

[0005] The semiconductor packaging module disclosed in at least one embodiment of the present invention includes a first redistribution layer, a first electronic component, a bonding material, a second electronic component, a second redistribution layer, a sealing layer, and a conductive pillar. The first electronic component is disposed on the first redistribution layer and has a first surface remote from the first redistribution layer. The bonding material is disposed on the first surface of the first electronic component. The second electronic component is disposed on the bonding material, and the first electronic component is located between the first redistribution layer and the second electronic component. The first electronic component, the bonding material, and the second electronic component are stacked on top of each other along a normal of the first redistribution layer. The second redistribution layer is disposed on the second electronic component, and the first electronic component and the second electronic component are located between the first redistribution layer and the second redistribution layer. The active surfaces of the first electronic component and the second electronic component face the first redistribution layer and the second redistribution layer, respectively. The sealing layer is disposed between the first redistribution layer and the second redistribution layer and covers the first electronic component and the second electronic component. The conductive pillar connects the first redistribution layer and the second redistribution layer and extends from the first redistribution layer through the sealing layer to the second redistribution layer. A first portion of the conductive post is connected to a first wiring layer, and a second portion of the conductive post is connected to a second wiring layer, with the interface between the first and second portions flush with a plane of the bonding material.

[0006] In at least one embodiment of the present invention, the bonding material is a die-bonding film.

[0007] In at least one embodiment of the present invention, the bonding material includes a first bonding layer disposed on a first electronic component and a second bonding layer disposed on the first electronic component. The second bonding layer is located between the first bonding layer and the second electronic component, and the first bonding layer and the second bonding layer are connected by a metal bond.

[0008] In at least one embodiment of the present invention, a first electronic component includes a plurality of first conductive vias located inside the first electronic component. The first electronic component is electrically connected to a bonding material via these first conductive vias, and the first conductive vias extend from the active surface of the first electronic component through the body of the first electronic component to a first bonding layer. A second electronic component includes a plurality of second conductive vias located inside the second electronic component. The second electronic component is electrically connected to a bonding material via these second conductive vias, and the second conductive vias extend from the active surface of the second electronic component through the body of the second electronic component to a second bonding layer.

[0009] In at least one embodiment of the present invention, the first electronic component and the second electronic component further include a plurality of pads. These pads are located on the active surface of the first electronic component and the active surface of the second electronic component, respectively. The first electronic component and the second electronic component are connected to the first redistribution layer and the second redistribution layer, respectively, through the pads.

[0010] In at least one embodiment of the present invention, the semiconductor packaging module further includes a plurality of conductive structures respectively disposed on the aforementioned pads. The pads are electrically connected to the first wiring layer and the second wiring layer through the conductive structures.

[0011] In at least one embodiment of the present invention, a first portion of the conductive post has a first cross-section, while a second portion of the conductive post has a second cross-section. The areas of the first cross-section and the second cross-section are not the same.

[0012] In at least one embodiment of the present invention, the second electronic element has a second surface that is away from the second redistribution layer, and the area of ​​the second surface is smaller than the area of ​​the first surface of the first electronic element.

[0013] In at least one embodiment of the invention, the bonding material completely covers a first surface of the first electronic component, while a region of the plane of the second electronic component is not covered by the bonding material. The sealing layer directly contacts this region of the bonding material.

[0014] In at least one embodiment of the present invention, the bonding material completely covers the second surface of the second electronic component, while the bonding material does not cover a region of the first surface of the first electronic component.

[0015] The semiconductor packaging module manufacturing method disclosed in at least one embodiment of the present invention includes providing a carrier plate; forming at least one first conductive pillar on the carrier plate; disposing at least one first electronic component on the carrier plate, wherein a first surface of the first electronic component is connected to the carrier plate; and forming a first sealing layer on the carrier plate after forming the first conductive pillar and disposing the first electronic component. A first sealing layer covers a first conductive post and a first electronic component, and exposes a first end face of the first conductive post. After forming the first sealing layer, a first redistribution layer is disposed on the first end face of the first conductive post, and the first redistribution layer is electrically connected to the first electronic component. The first conductive post has an interface away from the first redistribution layer. After disposing of the first redistribution layer, a carrier plate is removed to expose a first surface of the first electronic component and the interface of the first conductive post. After removing the carrier plate, a second conductive post is formed on the interface of the first conductive post. A bonding material is disposed on a second surface of a second electronic component. After forming the second conductive post, a second electronic component is disposed on the first surface of the first electronic component, such that the first electronic component, the bonding material, and the second electronic component are stacked on top of each other along a normal of the first redistribution layer, and the bonding material is located between the first electronic component and the second electronic component. After disposing of the second electronic component, a second sealing layer is formed on the first sealing layer. The second sealing layer covers the second conductive post and the second electronic component, and exposes a second end face of the second conductive post; and after forming the second sealing layer, a second redistribution layer is disposed on the second end face of the second conductive post, and the second redistribution layer is electrically connected to the second electronic component. The active surface of the first electronic component and the active surface of the second electronic component face the first redistribution layer and the second redistribution layer, respectively.

[0016] In at least one embodiment of the present invention, the method for manufacturing a semiconductor packaging module further includes, before setting a second electronic component on a first electronic component, setting a bonding layer on a first surface of the first electronic component, wherein the bonding layer and the bonding material include metal; bonding the bonding layer on the first electronic component and the bonding material on the second electronic component; and after bonding the bonding layer and the bonding material, connecting the bonding layer and the bonding material by eutectic bonding to form a metal bond between the bonding layer and the bonding material.

[0017] In at least one embodiment of the present invention, the area of ​​the interface of the first conductive post is different from the area of ​​the second end face of the second conductive post.

[0018] Based on the above, since the first electronic component and the second electronic component are stacked back-to-back (i.e., the active surfaces of the first electronic component and the second electronic component face away from each other) between the first and second wiring layers, and the first and second wiring layers are electrically connected through multiple conductive pillars, the planar dimensions (i.e., the dimensions of the xy plane, such as the area) of the semiconductor packaging module can be reduced, which helps to meet the current trend of miniaturization in mobile devices and wearable devices. Simple Explanation of the Diagram

[0019] The nature of the invention can be understood from the following detailed description and accompanying drawings. It should be noted that many features are not drawn to industry-standard scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0020] Figure 1 is a cross-sectional schematic diagram of a semiconductor packaging module according to at least one embodiment of the present invention.

[0021] Figure 2 is a cross-sectional schematic diagram of a semiconductor packaging module according to at least one embodiment of the present invention.

[0022] Figure 3 is a cross-sectional schematic diagram of a semiconductor packaging module according to at least one embodiment of the present invention.

[0023] Figures 4A to 4G are cross-sectional schematic diagrams of the manufacturing method of the semiconductor packaging module in Figure 1.

[0024] Figures 5A to 5C are cross-sectional schematic diagrams of a method for manufacturing a semiconductor packaging module according to at least one embodiment of the present invention.

[0025] Figure 6 is a cross-sectional schematic diagram of the manufacturing method of the semiconductor packaging module in Figure 3. Implementation

[0026] In the following text, to clearly present the technical features of this application, the dimensions (e.g., length, width, thickness, area, or depth) of the elements (e.g., layers, films, substrates, and regions) in the drawings will be enlarged proportionally, and the number of some elements may be reduced. Therefore, the description and explanation of the embodiments below are not limited to the number of elements in the drawings or the size and shape of the elements, but should cover the size, shape, and deviations from both caused by actual manufacturing processes and / or tolerances. For example, a flat surface shown in the drawings may have rough and / or non-linear characteristics, and an acute angle shown in the drawings may be rounded. Therefore, the elements presented in the drawings of this application are mainly for illustration and are not intended to accurately depict the actual shape of the elements, nor are they intended to limit the scope of the claims in this application.

[0027] Secondly, the terms "approximately," "approximately," or "substantially" used in this application not only cover explicitly stated numerical values ​​and ranges, but also the permissible deviation range understandable to someone with ordinary skill in the art to which this invention pertains. This deviation range can be determined by errors that occur during measurement, such as those arising from limitations of the measurement system or process conditions. Furthermore, "approximately" can indicate a deviation within one or more standard deviations of the aforementioned numerical values, such as ±30%, ±20%, ±10%, or ±5%. The terms "approximately," "approximately," or "substantially" used in this application can be chosen based on optical properties, etching properties, mechanical properties, or other properties to select an acceptable deviation range or standard deviation, and do not apply a single standard deviation to all optical, etching, mechanical, and other properties.

[0028] Figure 1 is a cross-sectional schematic diagram of a semiconductor packaging module 100 according to at least one embodiment of the present invention. Referring to Figure 1, the semiconductor packaging module 100 includes a first redistribution layer 111, a second redistribution layer 112, a first electronic component 121, a second electronic component 122, a bonding material 130, a sealing layer 140, and conductive pillars 160.

[0029] A first electronic component 121 is disposed on a first redistribution layer 111 and has a first surface 121s away from the first redistribution layer 111. A bonding material 130 is disposed on the first surface 121s of the first electronic component 121, and a second electronic component 122 is disposed on the bonding material 130. The first electronic component 121 is located between the first redistribution layer 111 and the second electronic component 122, and the first electronic component 121, the bonding material 130, and the second electronic component 122 are stacked on each other on the normal N1 of the first redistribution layer 111, wherein the normal N1 is perpendicular as shown in FIG. 1, and each conductive post 160 can extend along the normal N1.

[0030] As shown in Figure 1, a second redistribution layer 112 is disposed on a second electronic component 122, and a first electronic component 121 and a second electronic component 122 are located between the first redistribution layer 111 and the second redistribution layer 112. The second electronic component 122 has a second surface 122s that is away from the second redistribution layer 112. Specifically, the active surface 121A of the first electronic component 121 (i.e., the surface opposite to the first surface 121s) and the active surface 122A of the second electronic component 122 (i.e., the surface opposite to the second surface 122s) face the first redistribution layer 111 and the second redistribution layer 112, respectively. In other words, the first surface 121s of the first electronic component 121 is disposed facing the second surface 122s of the second electronic component 122.

[0031] The first electronic component 121 and the second electronic component 122 further include a plurality of pads 121p and 122p, respectively. The pads 121p and 122p are located on the active surface 121A of the first electronic component 121 and the active surface 122A of the second electronic component 122, respectively. The first electronic component 121 and the second electronic component 122 are connected to the first redistribution layer 111 and the second redistribution layer 112, respectively, through the pads 121p and 122p.

[0032] The semiconductor packaging module 100 also includes a plurality of conductive structures 150, which are respectively disposed on pads 121p and 122p. Pads 121p and 122p are electrically connected to the first redistribution layer 111 and the second redistribution layer 112 through the conductive structures 150. Specifically, taking FIG1 as an example, a first electronic component 121 may be mounted on the first redistribution layer 111 and electrically connected to the first redistribution layer 111 via the conductive structures 150. On the other hand, a second electronic component 122 may also be mounted on the second redistribution layer 112 and electrically connected to the second redistribution layer 112 via the plurality of conductive structures 150.

[0033] In this embodiment, the conductive structure 150 may be, but is not limited to, a conductive bump or solder ball. Furthermore, in some embodiments, no conductive structure 150 may also be provided between the first electronic element 121 as well as the first rerouting layer 111 (or between the second electronic element 122 and the second rerouting layer 112 ). Also, the first electronic component 121 or the second electronic component 122 may be installed on the first rerouting layer 111 or the second rerouting layer 112 by means of a bump-free (bump-free) manner. As shown in Figure 5C , the electrical conduction between the electronic components as well as the rerouting layers (e.g., between the second electronic component 122 as well as the second rerouting layer 112 ) can be improved by this bump-free setup.

[0034] Furthermore, the thickness saved by the bump-free design may be added to the thickness of the first electronic component 121 or the second electronic component 122 without the thickness of the semiconductor package module 100 being changed. That is, a thicker first electronic component 121 or a second electronic component 122 may be employed. In doing so, the risk of damage to the first electronic component 121 or the second electronic component 122 during die bonding is reduced, thereby improving the process yield.

[0035] On the other hand, when the thickness of the semiconductor package module 100 is reduced due to no bump provided (i.e., the conductive structure 150 ), the thickness (i.e., height) of the conductive column 160 may also decrease accordingly. In general, since the conductive column 160 can be formed by lithography and plating, the thicker the conductive column 160 is more difficult to make and the fabrication risk is higher. Therefore, when the thickness of the conductive column 160 is reduced, it is advantageous to reduce the risk and difficulty of making the conductive column 160 , but it also helps to improve the component setup density in the semiconductor packaging module 100 .

[0036] The first electronic component 121 as well as the second electronic component 122 may be a packaged chip or an unpackaged bare chip (die). In addition, the first electronic component 121 as well as the second electronic component 122 may be a logic chip, such as a Microcontroller Unit (MCU), but the types of the first electronic component 121 and the second electronic component 122 in the present invention are not limited to the above.

[0037] In the embodiment shown in FIG1, the semiconductor packaging module 100 includes a first electronic component 121 and a second electronic component 122. However, in a single semiconductor packaging module of other embodiments, the number of the first electronic component 121 and the second electronic component 122 may be at least one, for example, two of each, that is, the total number of the first electronic component 121 and the second electronic component 122 is four. Therefore, FIG1 does not limit the number of the first electronic component 121 and the second electronic component 122.

[0038] It is worth mentioning that, in the embodiment of FIG1, the bonding material 130 connecting the first electronic component 121 and the second electronic component 122 can be a die attach film (DAF).

[0039] A sealing layer 140 is disposed between the first redistribution layer 111 and the second redistribution layer 112, and covers the first electronic component 121 and the second electronic component 122. Specifically, the sealing layer 140 partially covers the active surface 121A of the first electronic component 121 and partially covers the active surface 122A of the second electronic component 122. That is, the sealing layer 140 does not completely cover the active surface 121A to avoid hindering the electrical connection between the first electronic component 121 and the first redistribution layer 111, nor does it completely cover the active surface 122A to avoid hindering the electrical connection between the second electronic component 122 and the second redistribution layer 112. The sealing layer 140 may include, for example, a solid molding compound or a similar molding compound.

[0040] On the other hand, the sealing layer 140 also covers the conductive post 160. Specifically, the conductive post 160 connects the first rewiring layer 111 and the second rewiring layer 112, and extends from the first rewiring layer 111 through the sealing layer 140 to the second rewiring layer 112. The conductive post 160 has a first portion 161 and a second portion 162, wherein the first portion 161 of the conductive post 160 is connected to the first rewiring layer 111, and the second portion 162 of the conductive post 160 is connected to the second rewiring layer 112. As shown by line segment AA in FIG1, the interface 160i between the first portion 161 and the second portion 162 is flush with the plane 130f of the bonding material 130.

[0041] In detail, the first portion 161 of the conductive post 160 has a first cross-section 161c, while the second portion 162 of the conductive post 160 has a second cross-section 162c. It is worth noting that, in some embodiments, the area of ​​the first cross-section 161c and the area of ​​the second cross-section 162c may be different, and the area of ​​the first cross-section 161c may be larger or smaller than the area of ​​the second cross-section 162c. Furthermore, in other embodiments, the dimensions (e.g., width or volume) of the first portion 161 and the second portion 162 of the same conductive post 160 may also be different.

[0042] However, the present invention is not limited to the above. In some embodiments, the area of ​​the first cross-section 161c and the area of ​​the second cross-section 162c may be the same. Furthermore, the materials forming the first portion 161 and the second portion 162 may be the same or different, for example, including single-layer or multi-layer structures, such as copper, aluminum, nickel, titanium, tin, silver, other suitable materials, alloys of at least two of the above, or combinations thereof. It is worth noting that regardless of whether the materials of the first portion 161 and the second portion 162 are the same or different, an interface (boundary) 160i will be present between the first portion 161 and the second portion 162.

[0043] In the embodiment illustrated in FIG1, the area of ​​the second surface 122s of the second electronic element 122 is smaller than the area of ​​the first surface 121s of the first electronic element 121, but the present invention is not limited thereto. In other embodiments of the present invention, the area of ​​the second surface 122s of the second electronic element 122 may also be equal to (i.e., the first electronic element 121 and the second electronic element 122 coincide on the normal N1) or greater than the area of ​​the first surface 121s of the first electronic element 121.

[0044] Furthermore, to avoid warping caused by an excessive difference in the coefficients of thermal expansion between the bonding material 130 and the sealing layer 140, the contact area between the bonding material 130 and the sealing layer 140 must be reduced. Therefore, in this embodiment, the bonding material 130 completely covers the second surface 122s of the second electronic component 122, but does not cover a region of the first surface 121s of the first electronic component 121.

[0045] On the other hand, the dimensions (e.g., volume or thickness) of the first electronic component 121 and the second electronic component 122 may be different. For example, in this embodiment, the thickness t1 of the first electronic component 121 may be greater than the thickness t2 of the second electronic component 122. For instance, the thickness t1 of the first electronic component 121 may fall within the range of 60µm to 100µm, while the thickness t2 of the second electronic component 122 may fall within the range of 50µm to 80µm, but the invention is not limited thereto. In other embodiments, the thickness t1 of the first electronic component 121 may also be less than or equal to the thickness t2 of the second electronic component 122.

[0046] The semiconductor packaging module 100 may further include a plurality of solder balls S1 connected to the first redistribution layer 111. Using these solder balls S1, the semiconductor packaging module 100 can be mounted on a circuit board to electrically connect the semiconductor packaging module 100 to the circuit board. The circuit board may be a packaging substrate with integrated circuit (IC), a printed circuit board (PCB), or other suitable external device.

[0047] Please refer to Figure 2 for another embodiment of the semiconductor packaging module 200 of the present invention. The semiconductor packaging module 200 is generally similar to the semiconductor packaging module 100, the difference being that the bonding material 230 of the semiconductor packaging module 200 further includes a first bonding layer 231 and a second bonding layer 232. The first bonding layer 231 is disposed on the first electronic component 121, while the second bonding layer 232 is disposed on the second electronic component 122 and located between the first bonding layer 231 and the second electronic component 122.

[0048] It is worth mentioning that the first bonding layer 231 and the second bonding layer 232 are connected by metallic bonding, such as eutectic bonding. Specifically, the first bonding layer 231 and the second bonding layer 232 can be metallic materials with low-temperature eutectic properties, such as gold-indium alloys, copper-tin alloys, gold-tin alloys, or similar materials. In this way, after heating to a temperature range of 156°C to 280°C, a eutectic reaction can occur between the contacting first bonding layer 231 and the second bonding layer 232, connecting them and electrically connecting the first bonding layer 231 to the second bonding layer 232.

[0049] As shown in Figure 2, the first electronic component 121 of the semiconductor packaging module 200 further includes a plurality of first conductive vias 121V, and the second electronic component 122 further includes a plurality of second conductive vias 122V. The first conductive vias 121V are located inside the first electronic component 121, through which the first electronic component 121 is electrically connected to the bonding material 230. Specifically, the first conductive vias 121V extend from the active surface 121A of the first electronic component 121 through the body 121M of the first electronic component 121 to the first bonding layer 231.

[0050] On the other hand, the second conductive via 122V is located inside the second electronic component 122, through which the second electronic component 122 is electrically connected to the bonding material 230. Specifically, the second conductive via 122V extends from the active surface 122A of the second electronic component 122 through the body 122M of the second electronic component 122 to the second bonding layer 232. The first conductive via 121V and the second conductive via 122V can be formed, for example, by through-silicon via (TSV).

[0051] By providing the first conductive via 121V and the second conductive via 122V, the semiconductor package module 200 can have greater flexibility in wiring design (e.g., ground / power line arrangement). In other words, it is not limited to using the conductive post 160 to electrically connect the second electronic component 122 to the first rewiring layer 111.

[0052] In this embodiment, the second electronic component 122 can also be electrically connected to the first redistribution layer 111 through the bonding material 230 and the first electronic component 121. Therefore, the number of conductive pillars 160 in the semiconductor package module 200 can be reduced, thereby reducing the volume of the semiconductor package module 200, especially reducing the size of the semiconductor package module 200 in the XY plane, where the XY plane is, for example, the horizontal plane in FIG2, and the Z-axis direction is, for example, the vertical direction in FIG2.

[0053] Referring to line segment BB in Figure 2, the interface 160i between the first portion 161 and the second portion 162 of the conductive post 160 is flush with the plane 230f of the bonding material 230. The bonding material 230 (the first bonding layer 231) completely covers the first surface 121s of the first electronic component 121, while the second electronic component 122 does not cover a region R1 of the plane 230f of the bonding material 230. Notably, the sealing layer 140 in the semiconductor packaging module 200 directly contacts the region R1 of the bonding material 230.

[0054] Please refer to Figure 3 for another embodiment of the semiconductor packaging module 300 of the present invention. The semiconductor packaging module 300 is generally similar to the semiconductor packaging module 100, except that the semiconductor packaging module 300 further includes at least one electronic package unit 310, which may be, for example, a Multi-Chip Package (MCP) or similar element. Specifically, the electronic package unit 310 includes a circuit board 313, at least one chip 323, and a sealing layer 340. The circuit board 313 of the electronic package unit 310 is disposed between the chip 323 and the second rewiring layer 112, and is electrically connected to the second rewiring layer 112 via a plurality of solder balls S2, wherein the electronic package unit 310 and the second electronic component 122 are located on opposite sides of the second rewiring layer 112.

[0055] The chip 323 can be electrically connected to the circuit board 313 by means of, for example, flip-chip or wire bonding. In this embodiment, the chip 323 can be, for example, an active chip or a passive chip, or the chip 323 can include both active and passive chips, but is not limited thereto.

[0056] A sealing layer 340 is disposed on the surface 313s of the circuit substrate 313 and covers the chip 323. A filler 370 is disposed between the second redistribution layer 112 and the circuit substrate 313 of the electronic package unit 310, and the filler 370 may cover the solder balls S2 to stabilize the bonding strength between the circuit substrate 313 and the second redistribution layer 112. The filler 370 may be, for example, capillary underfill (CUF), non-conductive film (NCF), or other suitable filler materials, but the present invention is not limited thereto.

[0057] Figures 4A to 4G are cross-sectional schematic diagrams of the manufacturing method of the semiconductor packaging module 100 in Figure 1. Referring to Figure 4A, firstly, a carrier plate 410 is provided. This carrier plate 410 can be a rigid substrate such as a glass plate, metal plate, or ceramic plate. In some embodiments, a release layer 412 may also be provided on one side of the carrier plate 410. Next, at least one first conductive post 461 is formed on the side of the carrier plate 410 (where the release layer 412 is provided). The first conductive post 461 may include copper, aluminum, nickel, titanium, tin, silver, other suitable materials or combinations thereof, and may be a conductive post formed, for example, by photolithography, electroplating, or photoresist stripping. However, the present invention is not limited to this, and the first conductive post 461 may be formed by other suitable materials and forming methods depending on the actual design requirements.

[0058] On the other hand, in the steps of FIG4A, at least one first electronic component 121 can be disposed on the carrier plate 410 (the side provided with release layer 412), and the first surface 121s of the first electronic component 121 is bonded to the carrier plate 410 through the release layer 412. In particular, the conductive structure 150 can be disposed on the active surface 121A of the first electronic component 121 before or after the first electronic component 121 is disposed on the carrier plate 410.

[0059] Referring to Figure 4B, after the first conductive post 461 is formed and the first electronic component 121 is disposed, a first sealing layer 441 is formed on the carrier plate 410 (the side with the release layer 412). The first sealing layer 441 covers the first conductive post 461 and the first electronic component 121, and exposes the first end face 461e of the first conductive post 461. In detail, a molding material (not shown) is disposed on the carrier plate 410 and cured. This molding material covers the first electronic component 121 and the first conductive post 461. Next, the upper surface of the cured molding material is ground to form the first sealing layer 441 exposing the first end face 461e. This grinding step also exposes the surface 150s of the conductive structure 150 and makes the first end face 461e of the first conductive post 461 flush with the surface 150s of the conductive structure 150.

[0060] Referring to Figures 4B and 4C, after the first sealing layer 441 is formed, a first redistribution layer 111 is disposed on the first end face 461e of the first conductive post 461, and this first redistribution layer 111 is electrically connected to the first electronic component 121 through the conductive structure 150. The formation of the first redistribution layer 111 may include the following steps: before removing the carrier plate 410, the first redistribution layer 111 is disposed on the first end face 461e of the first conductive post 461, wherein the first redistribution layer 111 covers the first sealing layer 441, the first conductive post 461, and the first electronic component 121. Then, the carrier plate 420 is attached to the first redistribution layer 111 through a release layer (not shown), so that the first redistribution layer 111 is located between the carrier plate 420 and the first electronic component 121.

[0061] Next, after flipping over the carrier plate 410, the first redistribution layer 111, and the carrier plate 420, the carrier plate 410 is removed to expose the first surface 121s of the first electronic component 121, the interface 461i of the first conductive post 461, and the plane 441f of the first sealing layer 441, as shown in FIG4C, wherein the plane 441f, the first surface 121s of the first electronic component 121, and the interface 461i of the first conductive post 461 are coplanar with each other.

[0062] Referring to Figure 4D, after removing the carrier plate 410 (shown in Figure 4B), a second conductive post 462 can be formed on the interface 461i of the first conductive post 461 by photolithography or electroplating. On the other hand, a bonding material 130 is provided on the second surface 122s of the second electronic component 122. After forming the second conductive post 462, the second electronic component 122 is provided on the first surface 121s of the first electronic component 121, such that the first electronic component 121, the bonding material 130, and the second electronic component 122 are stacked on each other on the normal N1 of the first redistribution layer 111, and the bonding material 130 is located between the first electronic component 121 and the second electronic component 122.

[0063] It is worth mentioning that, in another embodiment of the present invention, such as the manufacturing method of the semiconductor packaging module 200 of FIG. 2, the method further includes: before the second electronic component 122 is disposed on the first electronic component 121, a bonding layer (i.e., the first bonding layer 231 in FIG. 2) is disposed on the first surface 121s of the first electronic component 121, and this bonding layer comprises metal. In this embodiment, the bonding material disposed on the second surface 122s of the second electronic component 122 (i.e., the second bonding layer 232 in FIG. 2) also comprises metal. Then, the bonding layer on the first electronic component 121 and the bonding material on the second electronic component 122 are bonded together.

[0064] As mentioned above, after bonding the bonding layer (i.e., the first bonding layer 231 in FIG2) and the bonding material (i.e., the second bonding layer 232 in FIG2), the bonding layer and the bonding material can be connected by eutectic bonding to form a metallic bond between the bonding layer and the bonding material.

[0065] Referring to the embodiment in Figure 4E, the conductive structure 150 can be disposed on the active surface 122A of the second electronic component 122 before or after the second electronic component 122 is disposed. After the second electronic component 122 is disposed, a second sealing layer 442 is formed on the first sealing layer 441. The second sealing layer 442 covers the second conductive post 462 and the second electronic component 122, and exposes the second end face 462e of the second conductive post 462.

[0066] In detail, the molding material forming the second sealing layer 442 may be the same as or different from the molding material forming the first sealing layer 441. The method for forming the second sealing layer 442 may include placing the molding material on the first sealing layer 441 and curing the molding material. This molding material covers the second electronic component 122 and the second conductive post 462. Next, the upper surface of the cured molding material is ground to form the second sealing layer 442, exposing the second end face 462e. This grinding step also exposes the surface 150s of the conductive structure 150 to the second sealing layer 442, and makes the second end face 462e of the second conductive post 462 flush with the surface 150s of the conductive structure 150. Furthermore, in FIG. 4E, an interface (not shown) is formed between the first sealing layer 441 and the second sealing layer 442, and this interface can be observed using instruments. For example, the interface can be observed using an electron microscope.

[0067] Furthermore, although in this embodiment the area of ​​the interface 461i of the first conductive post 461 is the same as the area of ​​the second end face 462e of the second conductive post 462, the present invention is not limited thereto. In other embodiments, the area of ​​the interface 461i of the first conductive post 461 and the area of ​​the second end face 462e of the second conductive post 462 may not be the same. In addition, the thickness t3 of the first sealing layer 441 may be greater than the thickness t4 of the second sealing layer 442.

[0068] Referring to Figure 4F, after the second sealing layer 442 (shown in Figure 4E) is formed, a second redistribution layer 112 is disposed on the second end face 462e of the second conductive post 462. The second redistribution layer 112 is electrically connected to the second electronic component 122 through the conductive structure 150 located on the second electronic component 122. The active surface 121A of the first electronic component 121 and the active surface 122A of the second electronic component 122 face the first redistribution layer 111 and the second redistribution layer 112, respectively.

[0069] Referring to Figure 4G, after the second redistribution layer 112 is set, the carrier board 420 (shown in Figure 4F) is removed, exposing the surface 111s of the first redistribution layer 111. Then, a plurality of solder balls S1 are set on the surface 111s of the first redistribution layer 111. In addition, this step includes dicing the second redistribution layer 112, the first sealing layer 441, the second sealing layer 442, and the first redistribution layer 111 using a dicing tool 45 to perform a monomerization process, thereby forming a plurality of semiconductor packaging modules 100 as shown in Figure 1. The dicing tool 45 can be a rotating blade or a laser beam, but the invention is not limited to these. At this point, the semiconductor packaging module 100 is essentially manufactured.

[0070] The manufacturing method of semiconductor packaging module 300 is similar to that of semiconductor packaging module 100 in Figures 4A to 4G, that is, the method of manufacturing semiconductor packaging module 300 includes the steps of the aforementioned embodiments. Therefore, the following mainly describes the differences in manufacturing method between semiconductor packaging module 300 and semiconductor packaging module 100.

[0071] Please refer to Figure 6. The manufacturing method of the semiconductor packaging module 300 further includes: after setting solder balls S1 on the first wiring layer 111, multiple electronic packaging units 310 in Figure 3 can be set on the second wiring layer 112 by reflow soldering.

[0072] In this embodiment, the electronic package monomer 310 is first disposed on the second redistribution layer 112, and then a filler 370 is formed between the electronic package monomer 310 and the second redistribution layer 112. The filler 370 can cover part of the side surface of the electronic package monomer 310 to improve the bonding between the electronic package monomer 310 and the second redistribution layer 112. After the filler 370 is disposed, the second redistribution layer 112, the second sealing layer 442, the first sealing layer 441, and the first redistribution layer 111 are sequentially cut using a cutting tool 45 to perform a monomerization process, thereby forming multiple semiconductor package modules 300 as shown in FIG3. At this point, the semiconductor package module 300 has been basically manufactured.

[0073] It is worth mentioning that in another embodiment illustrated in Figures 5A to 5C, the second electronic component 122 is mounted on the second redistribution layer 112 without bumps. Referring to Figure 5A, this embodiment is manufactured by first forming at least one second conductive post 462 on the carrier plate 410 (the side with the release layer 412), and then placing at least one second electronic component 122 on the carrier plate 410, wherein the active surface 122A of the second electronic component 122 is bonded to the carrier plate 410 through the release layer 412. Next, a second sealing layer 442 is formed on the carrier plate 410 (the side with the release layer 412), and this second sealing layer 442 exposes the second surface 122s of the second electronic component 122.

[0074] Next, a first electronic element 121 is disposed on the second surface 122s of the second electronic element 122, wherein the first surface 121s of the first electronic element 121 faces the second electronic element 122. Furthermore, a first conductive post 461 can be formed on the second conductive post 462. Notably, in this step, a bonding material 130 can also be formed on the first surface 121s of the first electronic element 121, and the first surface 121s of the first electronic element 121 can be connected to the second surface 122s of the second electronic element 122 through this bonding material 130.

[0075] Referring to FIG5B, after the first electronic component 121 is disposed on the second sealing layer 442 and the first conductive post 461 is formed, the first sealing layer 441 is formed on the second sealing layer 442. Next, by grinding, the surface 150s of the conductive structure 150 is exposed to the first sealing layer 441, and the first end face 461e of the first conductive post 461 is flush with the surface 150s of the conductive structure 150. After forming the first sealing layer 441, a first redistribution layer 111 is disposed on the first end face 461e of the first conductive post 461. After disposing of the first redistribution layer 111, referring to FIG5C, the first redistribution layer 111, the first sealing layer 441, the second sealing layer 442, and the carrier plate 410 are flipped, and the carrier plate 410 (and the release layer 412) are removed to expose the active surface 122A of the second electronic component 122. Next, the second redistribution layer 112 is formed on the active surface 122A of the second electronic component 122.

[0076] The manufacturing methods shown in Figures 5A to 5C form two sealing layers, namely a first sealing layer 441 and a second sealing layer 442. That is, the semiconductor package module manufactured using the methods shown in Figures 5A to 5C includes two sealing layers (a first sealing layer 441 and a second sealing layer 442). However, in other embodiments, the semiconductor package module may include only one sealing layer.

[0077] Please refer to Figures 5A and 5B. The first sealing layer 441 and the second sealing layer 442 shown in Figures 5A and 5B can be replaced by two photoresist layers, such as dry film. Specifically, in other embodiments not shown, during the formation of the second conductive pillar 462, a first photoresist layer after exposure and development can be formed on the release layer 412, which has multiple openings and is in direct contact with the release layer 412.

[0078] Next, using the first photoresist layer as a mask, these second conductive pillars 462 are formed on the release layer 412, wherein all the second conductive pillars 462 are formed within the aforementioned openings and slightly protrude from or do not protrude from the upper surface of the first photoresist layer. Then, these second conductive pillars 462 and the upper surface of the first photoresist layer are polished so that the top surface of each second conductive pillar 462 is coplanar with the polished upper surface of the first photoresist layer.

[0079] Next, the first photoresist layer on the release layer 412 is retained, and a second photoresist layer, after exposure and development, is formed on the first photoresist layer, wherein the second photoresist layer has a plurality of openings exposing the top surfaces of the second conductive pillars 462. Then, the first conductive pillars 461 are formed on the first photoresist layer, wherein the first conductive pillars 461 are respectively formed within the openings of the second photoresist layer. Next, the first conductive pillars 461 and the upper surface of the second photoresist layer are polished so that the top surface of each first conductive pillar 461 is coplanar with the polished upper surface of the second photoresist layer. Next, the first and second photoresist layers are removed, leaving the first conductive pillars 461 and second conductive pillars 462 disposed on the release layer 412. Then, a first electronic component 121 and a second electronic component 122 are disposed on the release layer 412.

[0080] Next, a sealing layer is formed on the release layer 412, which covers the first conductive pillars 461, the second conductive pillars 462, the first electronic component 121, and the second electronic component 122, and covers the release layer 412. Then, the steps shown in Figures 5B and 5C are performed sequentially. For example, by grinding, the first end face 461e of the first conductive pillar 461 is made flush with the surface 150s of the conductive structure 150. Then, a first redistribution layer 111 is formed on the first end face 461e of the first conductive pillar 461. Next, the carrier plate 410 and the release layer 412 are removed to expose the active surface 122A of the second electronic component 122. Then, a second redistribution layer 112 is formed on the active surface 122A to form a semiconductor package module with a single sealing layer.

[0081] In summary, since the first and second electronic components are stacked back-to-back (i.e., their active surfaces face away from each other) between the first and second wiring layers, and are electrically connected through multiple conductive pillars, the planar dimensions (i.e., the dimensions of the xy-plane, such as area) of the semiconductor packaging module can be reduced, the amount of process materials used can be decreased, which helps to meet the current trend of miniaturization in mobile and wearable devices and promotes the efficient use of resources.

[0082] In addition, when the bonding layer between the first electronic component and the second electronic component is conductive, and the first electronic component can be electrically connected to the second electronic component through this bonding layer, it is beneficial to shorten the electrical signal transmission path between the first electronic component and the second electronic component, thereby improving the quality of the semiconductor packaging module in terms of electrical signals.

[0083] On the other hand, the sealing layer used to cover the first electronic component, the second electronic component and the conductive pillar includes upper and lower layers. Since the coefficient of thermal expansion or Young's modulus of the upper and lower layers of the sealing layer can be the same or different (i.e., including the first sealing layer and the second sealing layer), the stress generated by the sealing layer of the semiconductor packaging module when heated can be reduced, thereby preventing the semiconductor packaging module from warping.

[0084] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art to which this invention pertains may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0085] 100, 200, 300: Semiconductor packaging modules 111: First Rewiring Layer 111s, 150s, 313s: Surface 112: Second Rewiring Layer 121: First electronic component 121A, 122A: Active surfaces 121M, 122M: Main Body 121p, 122p: Connecting pads 121s: First surface 121V: First conductive via 122: Second electronic component 122s: Second surface 122V: Second conductive via 130, 230: Bonding material 130f, 230f, 441f: Plane 140, 340: Sealing layer 150: Conductive structure 160: Conductive post 160i, 461i: Interface 161: Part One 161c: First section 162: Part Two 162c: Second section 231: First bonding layer 232: Second bonding layer 310: Electronic Packaging Unit 313: Circuit board 323: Chip 370: Filler 45: Cutting tools 410, 420: Carrier plates 412: Release layer 441: First sealing layer 442: Second sealing layer 461: First conductive post 461e: First end face 462: Second conductive post 462e: Second end face AA, BB: line segments N1: Normal line R1: Region S1, S2: Solder balls t1, t2, t3, t4: Thickness

Claims

1. A semiconductor packaging module, comprising: a first redistribution layer; a first electronic component disposed on the first redistribution layer and having a first surface remote from the first redistribution layer; a bonding material disposed on the first surface of the first electronic component; a second electronic component disposed on the bonding material, wherein the first electronic component is located between the first redistribution layer and the second electronic component, and the first electronic component, the bonding material, and the second electronic component are stacked on each other along a normal of the first redistribution layer; a second redistribution layer disposed on the second electronic component, wherein the first electronic component and the second electronic component are located between the first redistribution layer and the second redistribution layer, wherein the active surface of the first electronic component and the active surface of the second electronic component face the first redistribution layer and the second redistribution layer, respectively; A sealing layer is disposed between the first and second rewiring layers and covers the first and second electronic components; and a conductive post connects the first and second rewiring layers and extends from the first rewiring layer through the sealing layer to the second rewiring layer, wherein a first portion of the conductive post is connected to the first rewiring layer and a second portion of the conductive post is connected to the second rewiring layer, and an interface between the first and second portions is flush with a plane of the bonding material.

2. The semiconductor packaging module as described in claim 1, wherein the bonding material is a die bond film.

3. The semiconductor packaging module as described in claim 1, wherein the bonding material comprises: A first bonding layer is disposed on the first electronic component; A second bonding layer is disposed on the second electronic component and located between the first bonding layer and the second electronic component, wherein the first bonding layer and the second bonding layer are connected by a metal bond.

4. The semiconductor package module as described in claim 3, wherein the first electronic component comprises: The first electronic component includes: a plurality of first conductive vias located inside the first electronic component, wherein the first electronic component is electrically connected to the bonding material via the first conductive vias, and the first conductive vias extend from the active surface of the first electronic component through the body of the first electronic component to the first bonding layer; wherein the second electronic component includes: a plurality of second conductive vias located inside the second electronic component, wherein the second electronic component is electrically connected to the bonding material via the second conductive vias, and the second conductive vias extend from the active surface of the second electronic component through the body of the second electronic component to the second bonding layer.

5. The semiconductor packaging module as described in claim 1, wherein the first electronic component and the second electronic component further comprise: Multiple pads are located on the active surface of the first electronic component and the active surface of the second electronic component, respectively, wherein the first electronic component and the second electronic component are connected to the first rewiring layer and the second rewiring layer through the pads.

6. The semiconductor packaging module as described in claim 5, further comprising: Multiple conductive structures are disposed on the pads, wherein the pads are electrically connected to at least one of the first wiring layer and the second wiring layer through the conductive structures.

7. The semiconductor packaging module as claimed in claim 1, wherein the first portion of the conductive post has a first cross-section, and the second portion of the conductive post has a second cross-section, wherein the area of ​​the first cross-section and the area of ​​the second cross-section are not the same.

8. The semiconductor package module as claimed in claim 1, wherein the second electronic element has a second surface remote from the second redistribution layer, and the area of ​​the second surface is smaller than the area of ​​the first surface of the first electronic element.

9. The semiconductor packaging module as claimed in claim 8, wherein the bonding material completely covers the first surface of the first electronic component, while the second electronic component does not cover a region of the plane of the bonding material, wherein the sealing layer directly contacts the region of the bonding material.

10. The semiconductor package module as claimed in claim 8, wherein the bonding material completely covers the second surface of the second electronic component, while the bonding material does not cover a region of the first surface of the first electronic component.

11. A method for manufacturing a semiconductor packaging module, comprising: A carrier plate is provided; at least one first conductive post is formed on the carrier plate; at least one first electronic component is disposed on the carrier plate, wherein a first surface of the first electronic component is connected to the carrier plate; after forming the first conductive post and disposing of the first electronic component, a first sealing layer is formed on the carrier plate, wherein the first sealing layer covers the first conductive post and the first electronic component, and exposes a first end face of the first conductive post; after forming the first sealing layer, a first redistribution layer is disposed on the first end face of the first conductive post, and the first redistribution layer is electrically connected to the first electronic component, wherein the first conductive post has an interface remote from the first redistribution layer; after disposing of the first redistribution layer, the carrier plate is removed to expose the first surface of the first electronic component and the interface of the first conductive post; after removing the carrier plate, a second conductive post is formed on the interface of the first conductive post; a bonding material is disposed on a second surface of a second electronic component. After the second conductive pillar is formed, the second electronic component is disposed on the first surface of the first electronic component, such that the first electronic component, the bonding material, and the second electronic component are stacked on each other along a normal of the first redistribution layer, and the bonding material is located between the first electronic component and the second electronic component; after the second electronic component is disposed, a second sealing layer is formed on the first sealing layer, wherein the second sealing layer covers the second conductive pillar and the second electronic component, and exposes a second end face of the second conductive pillar; and after the second sealing layer is formed, a second redistribution layer is disposed on the second end face of the second conductive pillar, and the second redistribution layer is electrically connected to the second electronic component, wherein the active surface of the first electronic component and the active surface of the second electronic component face the first redistribution layer and the second redistribution layer, respectively.

12. The method as described in claim 11, further comprising: Before the second electronic component is disposed on the first electronic component, a bonding layer is disposed on the first surface of the first electronic component, and the bonding layer and the bonding material include metal; the bonding layer on the first electronic component and the bonding material on the second electronic component are bonded together; And after bonding the bonding layer and the bonding material, the bonding layer and the bonding material are connected by eutectic bonding to form a metallic bond between the bonding layer and the bonding material.

13. The method as described in claim 11, wherein the area of ​​the interface of the first conductive post is not the same as the area of ​​the second end face of the second conductive post.

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