Low dropout (LDO) NFET voltage regulator using thin oxide devices

Abstract

A voltage regulator including a first PFET including a gate configured to receive a first control signal; a second PFET including a gate configured to receive a first bias voltage; a first NFET, wherein the first PFET, the second PFET, and the first NFET are coupled in series between a first upper voltage rail and an output; an operational amplifier including a first input configured to receive a reference voltage; a voltage boost circuit including an input coupled to an output of the operational amplifier and an output coupled to a gate of the first NFET; a second NFET including a gate configured to receive a second bias voltage; and a third NFET coupled in series with the second NFET between a node between the second PFET and the first NFET and a lower voltage rail, wherein the third NFET includes a gate configured to receive a second control signal.

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