Expandable instruction set

Abstract

An apparatus comprises front end circuitry configured to fetch and decode instructions; and processing circuitry to perform data processing operations in response to instructions decoded by the front end circuitry. In an expandable instruction set mode, the front end circuitry decodes the instructions according to an instruction encoding scheme in which each instruction is required to meet an architectural encoding constraint requiring that, for a given instruction processed in the expandable instruction set mode: the given instruction comprises a set of functional bits representing functionality of the given instruction, and a set of one or more expansion bits; and the set of one or more expansion bits is constrained to specify a predetermined value.

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