Method for shrinking memory signal via region in accordance with memory-side ball layout to adjust control-side ball arrangement for installing control circuit at printed circuit board, and associated apparatus

Abstract

A method for shrinking a memory signal via region in accordance with memory-side ball layout to adjust control-side ball arrangement for installing a control circuit at a printed circuit board (PCB) and associated apparatus are provided. The method may include: providing a set of pads on a board-side region of a package of the control circuit, the set of pads corresponding to a set of first pads within a first installation region of the PCB, to act as control-side memory signal pads for conducting a set of predetermined memory signals; and providing multiple other pads on the board-side region, the multiple other pads corresponding to a set of remaining pads within the first installation region, to act as other-purpose pads for conducting other signals, where multiple vias are arranged as being next to the set of first pads to shrink the memory signal via region, for enhancing control-side ball-arrangement flexibility.

Description

[Technical Field]

[0001] This invention relates to circuit design, and more particularly to a method and related apparatus such as the control circuit and the PCB for mounting a control circuit on a printed circuit board (PCB) by adjusting the control-side ball arrangement to reduce the memory signal via region in accordance with a predetermined memory-side ball layout. [Previous Technology]

[0002] According to related technologies, memory packages conforming to Low-Power Double Data Rate (LPDDR) standards, such as LPDDR4, can be coupled to a PCB using multiple solder balls (or "balls") in an older configuration. An existing circuit layout control scheme has been proposed to address some issues in the related technologies. However, some additional problems may arise. When new versions of the LPDDR standard become available, memory packages conforming to the LPDDR standard, such as LPDDR5 / LPDDR5X, can be coupled to a PCB using (15 * 21) balls in a configuration, with ball pitches, such as the pitch along the X-axis and the pitch along the Y-axis, being predetermined lengths. Since the number of balls and the associated area of ​​LPDDR5 dies / chips have increased significantly, using this existing circuit layout control scheme would greatly increase the package size of a System-on-Chip (SoC). Therefore, a novel approach and related architecture are needed to address these issues with fewer side effects. [Summary of the Invention]

[0003] Therefore, one of the objectives of the present invention is to provide a method and related equipment, such as the control circuit and the PCB, for mounting a control circuit on a PCB by adjusting the control side pin arrangement to reduce the memory signal via area in accordance with a predetermined memory side pin layout, so as to solve the problems in the related art.

[0004] At least one embodiment of the present invention provides a method for adjusting the control side pin arrangement by reducing the memory signal via area to accommodate a predetermined memory side pin layout for mounting a control circuit on a PCB. The PCB has a first mounting area and a second mounting area for mounting the control circuit and a memory, respectively. The first mounting area and the second mounting area are located on opposite sides of the PCB, each side comprising a first side and a second side facing each other. The method may include: providing a set of pads on a board-side area of ​​a package of the control circuit, the set of pads corresponding to a set of first pads in the first mounting area to act as control-side memory signal pads for conducting a predetermined set of memory signals; and providing a plurality of other pads on the board-side area of ​​the package of the control circuit, the plurality of other pads corresponding to a set of remaining pads in the first mounting area to act as pads for other purposes for conducting other signals, wherein the second mounting area... A set of second pads is distributed inside and outside the memory signal via area. Multiple vias on the PCB used to conduct the predetermined memory signal pass through both sides of the PCB to allow the predetermined memory signal to be transmitted between the control circuit and the memory through the set of first pads, the multiple vias and the set of second pads. The multiple vias are arranged adjacent to the set of first pads to reduce the memory signal via area, so as to make room for the multiple other pads and improve the flexibility of the control side pin arrangement.

[0005] At least one embodiment of the present invention provides a control circuit whose package is implemented according to the above method, wherein the package of the control circuit may include: a set of pads, located in a first sub-region of the board side region, for serving as the control-side memory signal pads, wherein the first sub-region of the board side region is used as a first pin arrangement range of the control-side memory signal pads on the board side region; and a plurality of other pads, located in a second sub-region of the board side region, for serving as the other purpose pads, wherein the second sub-region and the first sub-region do not overlap.

[0006] At least one embodiment of the present invention provides a PCB in which a plurality of solder pads are implemented according to the above method, wherein the plurality of solder pads of the PCB may include: a group of first solder pads located in a first sub-region of the first mounting region, the first sub-region of the first mounting region corresponding to a first pin arrangement range of the control-side memory signal solder pads on the board side region; and the group of remaining solder pads located in a second sub-region of the first mounting region, wherein the second sub-region of the first mounting region and the first sub-region of the first mounting region do not overlap.

[0007] One of the many advantages of the present invention is that, through proper design, the method, control circuit, and PCB of the present invention can minimize the package size / area of ​​the control circuit without significantly increasing related costs such as material costs (e.g., SoC / PCB costs). For example, the control circuit can be a SoC, the memory can be random-access memory (RAM), and the PCB can be used to mount the control circuit, such as the SoC, and the memory / RAM, such as LPDDR 5 or above. Furthermore, the method, control circuit, and PCB of the present invention can solve problems in the related art with fewer side effects.

Implementation Method

[0008] Figure 1 is a schematic diagram of an electronic device 10 according to an embodiment of the present invention, wherein the electronic device 10 is implemented based on the method of the present invention of reducing the memory signal via area to adjust the control side pin arrangement in order to mount a control circuit 110 on a PCB 100 in accordance with a predetermined memory side pin layout. For better understanding, the control side and memory side packages can be referred to as packages #1 and #2. As shown in Figure 1, the electronic device 10 may include a control circuit 110, a memory 120 (e.g., RAM), and a PCB 100 for mounting the control circuit 110 and the memory 120. The control circuit 110 can control the operation of the electronic device 10, and the memory 120 can store information for the electronic device 10 (or the control circuit 110). In addition, the PCB 100 may include a plurality of via-pad groups (referred to as "VIA-PAD groups"), each VIA-PAD group including a via and at least one pad. For example, these VIA-PAD groups may include VIA-PAD groups 101 and 102 for coupling pads 111 and 112 of the control circuit 110 (or its package #1) and pads 121 and 122 of the memory 120 (or its package #2) to each other. PCB 100 may further include cross-area pads such as pad 103, which can be coupled to VIA-PAD group 102 via traces on PCB 100 to form larger VIA-PAD groups, such as cross-area VIA-PAD groups.

[0009] Figure 2, in its lower half, illustrates a cross-area circuit layout control scheme according to an embodiment of the present invention, wherein an in-area circuit layout control scheme is illustrated in the upper half of Figure 2 for better understanding. For memory packages conforming to the LPDDR4 standard, this in-area circuit layout control scheme can be applied to the relevant architecture of the LPDDR4 standard. As shown in the upper half of Figure 2, the pads / balls on a SoC (or its package #1) used to couple to an LPDDR4 memory and the corresponding VIA-PAD group on a PCB can be implemented corresponding to the pads / balls on the LPDDR4 memory (or its package #2) (as if mirrored), allowing the SoC and the LPDDR4 memory to be mounted on the top and bottom layers of the PCB respectively, thereby reducing the layout area through large-scale overlap. Since the number of balls and the associated area of ​​LPDDR5 memory are significantly increased, adopting this in-area circuit layout control scheme will greatly increase the package size of the SoC. Table 1 A1 … H1 J1 … N1 P1 R1 T1 … W1 Y1 AA1 A2 … H2 J2 … N2 P2 R2 T2 … W2 Y2 AA2 … … … … … … … … … … … … … A15 … H15 J15 … N15 P15 R15 T15 … W15 Y15 AA15

[0010] Table 1 shows a plurality of pads / balls in the pin layout of the predetermined memory side (or memory package). Taking the LPDDR5 layout as an example, there can be (21 * 15) = 315 balls {{A1, B1, …, H1, J1, …, N1, P1, R1, T1, …, W1, Y1, AA1}, {A2, B2, …, H2, J2, …, N2, P2, R2, T2, …, W2, Y2, AA2}, …, {A15, B15, …, H15, J15, …, N15, P15, R15, T15, …, W15, Y15, AA15}}, which can be arranged on a plane parallel to the XY plane containing the X and Y axes, but the present invention is not limited thereto. Although the use of package #2 conforming to the LPDDR5 standard results in a significant increase in the area of ​​package #2, this cross-area circuit layout control scheme can reduce the memory signal via area to a size smaller than that of package #2, achieving an extremely compact design. Specifically, vias (along with most of the pads coupled to these vias) within the relevant VIA-PAD group are concentrated in the memory signal via area, for example, a predetermined via concentration area 201. Cross-area pads corresponding to the pads on the periphery of package #2 are provided in at least one peripheral area 202, such as peripheral areas 202A and 202B, to form a cross-area VIA-PAD group. For better understanding, the predetermined via concentration area 201 in Figure 2 can be illustrated as a board-side area 211 corresponding to package #1 of the control circuit 110, and smaller in the X-axis direction than a board-side area 221 of package #2 of memory 120. This is for illustrative purposes only and not for limiting the invention. The predetermined through-hole concentration region 201 can be depicted as partially overlapping with the plate side region 211 and being smaller than the plate side region 221 in both the X-axis and Y-axis directions.

[0011] Once the pin layout of the package 220 of memory 120 (labeled "Package #2" for simplicity) has been determined, this cross-area circuit layout control scheme can minimize the size / area of ​​the package 210 of control circuit 110 (labeled "Package #1" for simplicity) without significantly increasing related costs such as material costs (e.g., SoC / PCB costs). For example, control circuit 110 can be a SoC, memory 120 can be RAM, and PCB 100, such as PCB 200, can be used to mount control circuit 110, such as this SoC, and memory 120, such as LPDDR fifth generation or higher RAM.

[0012] Figures 3 to 6, according to an embodiment of the present invention, respectively illustrate a top layer, a second layer, a third layer, and a bottom layer involved in a circuit architecture control scheme of the method, such as four layers TOP, L2, L3, and BOTTOM in a multilayer circuit, wherein the three remaining layers in the multilayer circuit (i.e., isolation layers located between the top layer, the second layer, the third layer, and the bottom layer) can be used to isolate the aforementioned four layers TOP, L2, L3, and BOTTOM. PCB 100 (e.g., PCB 200) may include a multilayer circuit architecture, which may include the aforementioned multilayer circuit, particularly the aforementioned four layers TOP, L2, L3, and BOTTOM. According to some embodiments, the multilayer circuit architecture may include more layers of circuitry.

[0013] PCB 100, such as PCB 200, may have a first mounting region and a second mounting region (on opposite sides of the PCB, the opposite sides comprising a first side and a second side), such as mounting regions 300 and 600, for mounting control circuit 110 and memory 120 respectively. The board-side region 211 of package #1 of control circuit 110 corresponds to the first mounting region, such as mounting region 300, and in particular, has the same size and shape as mounting region 300, and faces mounting region 300 when control circuit 110 is mounted in mounting region 300. The board-side region 221 of package #2 of memory 120 corresponds to the second mounting region, such as mounting region 600, and in particular, has the same size and shape as mounting region 600, and faces mounting region 600 when memory 120 is mounted in mounting region 600. The related operations of this method may include: (1) providing a set of pads {PAD0} on the board-side region 211 of the package #1 of the control circuit 110, the set of pads {PAD0} corresponding to a set of first pads {PAD1} in the first mounting region, such as mounting region 300, to act as control-side memory signal pads {PADM} for conducting a set of predetermined memory signals; and (2) providing a plurality of other pads {PAD0Other} on the board-side region 211 of the package #1 of the control circuit 110, the plurality of other pads {PAD0Other} corresponding to a set of remaining pads {PAD1Other} in the first mounting region, such as mounting region 300, to act as pads for other purposes for conducting other signals; wherein a set of second pads {PAD2} in the second mounting region, such as mounting region 600, may be distributed inside and outside the memory signal via region.

[0014] As shown in Figures 3 to 6, the vias {VIA} on PCB 100, such as PCB 200, used to conduct the predetermined memory signals may include vias {VIA(0)}, {VIA(1)}, {VIA(2)}, {VIA(3)}, and {VIA(4)} for different signal / voltage levels. The VIA-PAD group in the top layer, such as layer TOP, may include various VIA-PAD1 groups, such as VIA(0)-PAD1 group, VIA(1)-PAD1 group, and VIA(2)-PAD1 group corresponding to vias VIA(0), VIA(1), VIA(2), VIA(3), and VIA(4), respectively. PAD1 group, VIA(2)-PAD1 group, VIA(3)-PAD1 group and VIA(4)-PAD1 group, and the VIA-PAD group in the bottom layer, such as the VIA-PAD group in the BOTTOM layer, can include various VIA-PAD2 groups, such as VIA(0)-PAD2 group, VIA(1)-PAD2 group, VIA(2)-PAD2 group, VIA(3)-PAD2 group and VIA(4)-PAD2 group, respectively, which correspond to the through holes VIA(0), VIA(1), VIA(2), VIA(3) and VIA(4). In addition, the vias {VIA} such as the aforementioned vias {VIA(0)}, {VIA(1)}, {VIA(2)}, {VIA(3)} and {VIA(4)} can penetrate both sides of the PCB 100 (e.g., PCB 200) to allow the predetermined memory signal to be transmitted between the control circuit 110 and the memory 120 via the first pad {PAD1}, the vias {VIA} and the second pad {PAD2}. The vias {VIA} can be arranged adjacent to the first pad {PAD1} to reduce the memory signal via area, so as to make room for the other pads {PAD0Other} to improve the flexibility of the control side pin arrangement.

[0015] Figure 7 illustrates the grid lines 700, memory signal pad areas 701, and memory signal via areas 702 involved in the circuit architecture control scheme. The grid lines 700 can represent the grid lines formed by the centers of the respective first pads {PAD1} in the group. The memory signal pad areas 701 can represent the areas occupied by the first pads {PAD1} in the group. The memory signal via areas 702 can represent the areas occupied by the plurality of vias {VIA} and can be used as an example of the aforementioned memory signal via areas. The first pads {PAD1} in the first mounting area, such as mounting area 300, have a first spacing equal to a first predetermined length along a first predetermined direction (e.g., the direction of one of the X-axis and Y-axis). The second spacing of the first pads {PAD1} in the first mounting area, such as mounting area 300, along a second predetermined direction (e.g., the direction of the other of the X-axis and Y-axis) is equal to a second predetermined length. The size of the first pin arrangement range of the control-side memory signal pads {PADM} in the board-side area 211, such as board-side area 800, is equal to a first predetermined multiple of the first spacing multiplied by a second predetermined multiple of the second spacing. Specifically, the first predetermined direction and the second predetermined direction may represent the X-axis direction and the Y-axis direction, respectively, and the first spacing and the second spacing may represent an X-pitch, such as spacing X_Pitch, and a Y-pitch, such as spacing Y_Pitch, respectively. Assuming the first predetermined multiple and the second predetermined multiple can be written as MULTIPLE1 and MULTIPLE2 respectively, the size of the first pin arrangement range is equal to (MULTIPLE1*X_Pitch) * (MULTIPLE2*Y_Pitch). For example, the first predetermined length can represent any predetermined value greater than zero within the range of less than 0.7 millimeters (mm), and the second predetermined length can represent any predetermined value greater than zero within the range of less than 0.6 mm, but the invention is not limited thereto. In other examples, the respective ranges of the first predetermined length and the second predetermined length can be varied.

[0016] In addition, the plurality of vias {VIA} can be arranged to be staggered with the group of first pads {PAD1} along at least one third predetermined direction (e.g., the direction of vector (+1, +1) and the direction of vector (+1, -1), in units of pitch X_Pitch and Y_Pitch in the X-axis direction and Y-axis direction, respectively, to reduce the memory signal via region 702. The size of the memory signal via region 702 can be equal to a third predetermined multiple of the first pitch multiplied by a fourth predetermined multiple of the second pitch. In particular, the third predetermined multiple can be greater than or equal to the first predetermined multiple plus one, and the fourth predetermined multiple can be greater than or equal to the second predetermined multiple plus one. Assuming that the third predetermined multiple and the fourth predetermined multiple can be written as MULTIPLE3 and MULTIPLE4, respectively, the above relationship can be written as MULTIPLE3 ≥ MULTIPLE1 + 1 and MULTIPLE4 ≥ MULTIPLE2 + 1. For example, when MULTIPLE1 = 17 and MULTIPLE2 = 9, MULTIPLE3 ≥ (17 + 1) = 18 and MULTIPLE4 ≥ (9 + 1) = 10. In the case of the closest or more closely spaced arrangements, the third predetermined multiple is equal to the first predetermined multiple plus one, and the fourth predetermined multiple is equal to the second predetermined multiple plus one. For example, when MULTIPLE1 = 17 and MULTIPLE2 = 9, MULTIPLE3 = 18 and MULTIPLE4 = 10.

[0017] Referring to Figures 3 to 7, it can be seen that the vias {VIA} near the boundary of the memory signal via region 702 are arranged in a grid line 700 that surrounds the center of each of the first pads {PAD1}. Regarding the memory signal via region 702: (1) Various VIA-PAD groups corresponding to vias VIA(0), VIA(2), VIA(3) and VIA(4), such as VIA(i)-PAD1 group and VIA(i)-PAD2 group, i ≠ 1, can be regarded as VIA-PAD groups within the region. Among them, the VIA(i)-PAD1-PAD2 group (or "VIA(i)-PAD1 / 2 group") corresponding to vias VIA(0), VIA(2), VIA(3) and VIA(4) can be regarded as an example of VIA-PAD group 101; (2) The VIA(1)-PAD1 group corresponding to via VIA(1) can also be regarded as a VIA-PAD group within the region, and can be regarded as an example of VIA-PAD group 102; and (3) The VIA(1)-PAD2 group corresponding to the through hole VIA(1) can be regarded as the cross-area VIA-PAD group, and the VIA(1)-PAD1-PAD2 group (or "VIA(1)-PAD1 / 2 group") corresponding to the through hole VIA(1) can also be regarded as the cross-area VIA-PAD group; the pad {PAD2} coupled to the through hole VIA(1) can be regarded as the cross-area pad and can be used as an example of pad 103. For any memory signal transmitted by the VIA(1)-PAD1 / 2 group, such as the memory signal on the pad {PAD3} on the periphery of the package #2 of memory 120 (e.g., RAM of LPDDR fifth generation or above), this method can control the signal path to take a short PCB trace from the corresponding pad PAD2 toward the center as shown in Figure 6, and set a via VIA(1) to pass through layer L3 and layer L2 as shown in Figures 5 and 4, so as to reach the corresponding pad PAD1 as shown in Figure 3. Thus, for all memory signals in the predetermined group of memory signals except for power and ground, this method can complete the drilling of multiple vias {VIA} within the memory signal via area 702 (e.g., an area of ​​(18*X_Pitch) * (10*Y_Pitch)), making the memory signal via area 702 much smaller than the mounting area 600 occupied by the original pin layout of LPDDR5 RAM (e.g., an area of ​​(21*X_Pitch) * (15*Y_Pitch)), and allowing the corresponding pads {PAD1} on the top layer, such as layer TOP, and the corresponding pads {PAD0} on the board side area 211 to be completed within the memory signal pad area 701 (e.g., an area of ​​(17*X_Pitch) * (9*Y_Pitch)).

[0018] Some implementation details regarding the cross-area / intra-area VIA-PAD group can be further explained as follows. Assume that the first pad PAD1 and the second pad PAD2 corresponding to (especially, connected to) the via VIA (1) can be referred to as the first pad PAD1 (1) and the second pad PAD2 (1), respectively, and the first pad PAD1 and the second pad PAD2 corresponding to (especially, connected to) the via VIA (i≠1) can be referred to as the first pad PAD1 (i) and the second pad PAD2 (i), respectively, where i ≠ 1. Referring to Figures 6 and 7, it can be seen that the first portion of the second pads {PAD2(i)} in this group of second pads {PAD2} is within the memory signal via region 702, and the second portion of the second pads {PAD2(1)} in this group of second pads {PAD2} is outside the memory signal via region 702. The plurality of vias {VIA} can penetrate the PCB 100 (e.g., PCB... On both sides of 200, a portion of the memory signals in the predetermined memory signal set are allowed to be transmitted between the control circuit 110 and the memory 120 and within and outside the memory signal via area 702 via the first pad {PAD1(1)} in the first pad {PAD1}, the via {VIA(1)} in the plurality of vias {VIA}, and the second portion of the second pad {PAD2(1)}. At the same time, another portion of the memory signals in the predetermined memory signal set (in particular, most of the predetermined memory signals) are allowed to be transmitted between the control circuit 110 and the memory 120 and within the memory signal via area 702 via the first pad {PAD1(i)} in the first pad {PAD1}, the via {VIA(i)} in the plurality of vias {VIA}, and the first portion of the second pad {PAD2(i)}.

[0019] Figure 8 illustrates the control-side pads involved in the circuit architecture control scheme according to an embodiment of the present invention, wherein the control-side pads may include pads {PAD0} in board-side region 211, such as board-side region 800 (which may correspond to the mounting region 300 described above). The package #1 of the control circuit 110 may include: (1) the set of pads {PAD0}, such as pads {PAD0} located in a first sub-region 801 of board-side region 800, used as the control-side memory signal pads {PADM}, wherein the first sub-region 801 of board-side region 800 is used as the first pin arrangement range; and (2) the plurality of other pads {PAD0Other}, such as pads {PAD0} located in a second sub-region 802 of board-side region 800, used as the other purpose pads, wherein the second sub-region 802 and the first sub-region 801 do not overlap. For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0020] For better understanding, the multiple pads of PCB 100 (e.g., PCB 200) may include: (1) the first pad {PAD1}, located within a first sub-region of the first mounting region, such as mounting region 300 (e.g., the sub-region occupied by memory signal pad region 701 in mounting region 300 shown in Figure 7, particularly the sub-region below the upper boundary of memory signal pad region 701), wherein the first sub-region of mounting region 300 corresponds to the first sub-region 801 of board side region 800 and also corresponds to the first pin arrangement range; and (2) The remaining pads in the group {PAD1Other} are located within a second sub-region of the first mounting region, such as mounting region 300 (e.g., a sub-region of mounting region 300 not occupied by memory signal pad region 701, particularly the sub-region above the upper boundary of memory signal pad region 701), wherein the second sub-region of mounting region 300 and the first sub-region of mounting region 300 do not overlap.

[0021] Figure 9 illustrates the memory-side pads involved in the circuit architecture control scheme according to an embodiment of the present invention, wherein these memory-side pads may include pads {PAD3} in board-side region 221, such as board-side region 900 (which may correspond to the mounting region 600 described above). Taking the LPDDR5 layout as an example, the package #2 of memory 120 may include: (21 * 15) = 315 pads {PAD3} such as the pads / balls shown in Table 1, wherein balls A1, AA1, A15 and AA15 are located at the upper left, upper right, lower left and lower right corners of the board-side region 900 shown in Figure 9, respectively. A first sub-region 901 of the board-side region 900 corresponds to the memory signal pad region 701, while a second sub-region 902 of the board-side region 900 is the remaining region in the board-side region 900. For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0022] Figure 10 illustrates a flowchart of the method according to an embodiment of the present invention. Control circuit 110 (or its package #1 together with pads thereon such as pads 111 and 112) and PCB 100 (or its pads such as pads in VIA-PAD groups 101 and 102 and pad 103) may be implemented according to the method.

[0023] In step S11, pads 111 and 112, such as the set of pads {PAD0}, are provided on the board-side region 211 (e.g., board-side region 800) of the package #1 of the control circuit 110. The set of pads {PAD0} corresponds to the set of first pads {PAD1} in the first mounting region, such as mounting region 300, to act as control-side memory signal pads {PADM} for conducting the set of predetermined memory signals.

[0024] In step S12, the plurality of other pads {PAD0Other} are provided on the board-side region 211 (e.g., board-side region 800) of the package #1 of the control circuit 110. The plurality of other pads {PAD0Other} correspond to the group of remaining pads {PAD1Other} in the first mounting region, such as mounting region 300, to serve as pads for other purposes to conduct other signals. The group of second pads {PAD2} in the second mounting region, such as mounting region 600, may be distributed inside and outside the memory signal via region 702. The plurality of vias {VIA}, such as the vias {VIA(0)}, {VIA(1)}, {VIA(2)}, {VIA(3)} and {VIA(4)} mentioned above, may penetrate the PCB 100 (e.g., PCB 800). On both sides of (200), the predetermined memory signals are allowed to be transmitted between the control circuit 110 and the memory 120 via the first pad {PAD1}, the plurality of vias {VIA}, and the second pad {PAD2). The plurality of vias {VIA} can be arranged adjacent to the first pad {PAD1} to reduce the memory signal via area 702, thus providing space for the plurality of other pads {PAD0Other} to improve the flexibility of the control side pin arrangement. For simplicity, similar details are not repeated here in this embodiment.

[0025] For better understanding, the method can be illustrated using the workflow shown in Figure 10. According to certain embodiments, one or more steps may be added, deleted, or modified in the workflow shown in Figure 10.

[0026] According to certain control schemes, assuming a High Density Interconnect (HDI) PCB is used, via-on-pad / via-in-pad vias can be set and coupled to the LPDDR5 RAM and SoC via inner layer traces. The method, control circuit, and PCB of the present invention can solve the problems in related technologies with fewer side effects, while only requiring a low-cost plating through-hole (PTH) PCB process. The above description is only a preferred embodiment of the present invention, and all equivalent variations and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention. [Simplified Explanation of the Diagram]

[0027] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present invention, wherein the electronic device is implemented based on the method of adjusting the control side pin arrangement by reducing the memory signal via area in accordance with a predetermined memory side pin layout to mount a control circuit on a PCB. Figure 2 illustrates a cross-region circuit layout control scheme according to an embodiment of the present invention in its lower half, wherein an intra-region circuit layout control scheme is illustrated in the upper half of Figure 2 for better understanding. Figure 3 illustrates a top layer involved in the circuit architecture control scheme according to an embodiment of the present invention. Figure 4 illustrates a second layer involved in the circuit architecture control scheme. Figure 5 illustrates a third layer involved in the circuit architecture control scheme. Figure 6 illustrates a bottom layer involved in the circuit architecture control scheme. Figure 7 illustrates the grid line, memory signal pad area, and memory signal via area involved in the circuit architecture control scheme. Figure 8 illustrates the control side pad involved in the circuit architecture control scheme according to an embodiment of the present invention. Figure 9 illustrates the memory-side solder pads involved in the circuit architecture control scheme according to an embodiment of the present invention. Figure 10 illustrates a flowchart of the method according to an embodiment of the present invention.

Claims

1. A method for adjusting a control-side ball arrangement to mount a control circuit on a printed circuit board by reducing the memory signal via region in accordance with a predetermined memory-side ball layout, the printed circuit board having a first mounting region and a second mounting region for mounting the control circuit and a memory, the first mounting region and the second mounting region being on opposite sides of the printed circuit board, the opposite sides comprising a first side and a second side, the method comprising: A set of pads is provided on one board-side region of a package of the control circuit. This set of pads corresponds to a set of first pads in the first mounting region and serves as control-side memory signal pads to conduct a predetermined set of memory signals. A plurality of other pads are provided on the board-side region of the package of the control circuit. These other pads correspond to a set of remaining pads in the first mounting region and serve as pads for other purposes to conduct other signals. A set of second pads in the second mounting region is distributed inside and outside the memory signal via region. A plurality of vias on the printed circuit board for conducting the predetermined set of memory signals penetrate both sides of the printed circuit board to allow the predetermined set of memory signals to be transmitted between the control circuit and the memory via the set of first pads, the plurality of vias, and the set of second pads. The plurality of vias are arranged adjacent to the set of first pads to reduce the memory signal via region, thereby providing space for the plurality of other pads and improving the flexibility of the control-side pin arrangement.

2. The method as described in claim 1, wherein the first spacing of the first pads in the first mounting area along a first predetermined direction is equal to a first predetermined length, the second spacing of the first pads in the first mounting area along a second predetermined direction is equal to a second predetermined length, and the size of the first pin arrangement range of the control-side memory signal pads in the board-side area is equal to a first predetermined multiple of the first spacing multiplied by a second predetermined multiple of the second spacing.

3. The method as described in claim 2, wherein the first predetermined direction and the second predetermined direction represent the direction of an X-axis and the direction of a Y-axis, respectively, and the first spacing and the second spacing represent an X-spacing and a Y-spacing, respectively.

4. The method as described in claim 2, wherein the plurality of vias are arranged in a staggered manner with the first set of solder pads along at least a third predetermined direction to reduce the memory signal via area.

5. The method as described in claim 2, wherein the size of the memory signal via region is equal to a third predetermined multiple of the first pitch multiplied by a fourth predetermined multiple of the second pitch.

6. The method as described in claim 5, wherein the third predetermined multiple is greater than or equal to the first predetermined multiple plus one, and the fourth predetermined multiple is greater than or equal to the second predetermined multiple plus one.

7. The method as described in claim 1, wherein the vias near the boundary of the memory signal via region are arranged as a grid line surrounding the center of each of the first pads.

8. The method as described in claim 1, wherein a first portion of the second pads in the set of second pads is within the memory signal via area, and a second portion of the second pads in the set of second pads is outside the memory signal via area; and the plurality of vias penetrate the two sides of the printed circuit board to allow a portion of the predetermined memory signals in the set of memory signals to be transmitted between the control circuit and the memory, and within and outside the memory signal via area, via a portion of the first pads in the set of first pads, a portion of the vias in the plurality of vias, and the second portion of the second pads.

9. A control circuit whose package is implemented according to the method described in claim 1, wherein the package of the control circuit comprises: a set of pads, located in a first sub-region of the board side region, for serving as the control-side memory signal pads, wherein the first sub-region of the board side region is used as a first pin arrangement range of the control-side memory signal pads on the board side region; and a plurality of other pads, located in a second sub-region of the board side region, for serving as the other purpose pads, wherein the second sub-region and the first sub-region do not overlap.

10. A printed circuit board having a plurality of solder pads implemented according to the method described in claim 1, wherein the plurality of solder pads of the printed circuit board comprises: a first set of solder pads located in a first sub-region of a first mounting region, the first sub-region of the first mounting region corresponding to a first pin arrangement range of the control-side memory signal solder pads on the board side region; and the remaining set of solder pads located in a second sub-region of the first mounting region, wherein the second sub-region of the first mounting region and the first sub-region of the first mounting region do not overlap.

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