Product summation device and product summation method

Abstract

This invention provides a product summation apparatus and method that can reduce the error of product summation results. In the synaptic arithmetic unit 12, a plurality of memory cells 17, each storing a load value that constitutes a synaptic composite load, are arranged in a matrix. Output lines MAL1, MAL2, ... are connected to the memory cells 17 in each row, and input lines DL1, DL2, ... are connected to the memory cells 17 in each column. The output lines MAL1, MAL2, ... of the memory cells 17 are pre-charged, and the cell current corresponding to the synaptic composite load flows through each memory cell 17, discharging it and lowering its potential. The memory cells 17 are composed of memory elements, including a memory transistor, a drain-side transistor, and a source-side transistor connected in series, and are connected between the input lines DL1, DL2, ... and the output lines MAL1, MAL2, ... The memory transistor stores the load value using the charge of its charge accumulation layer. Based on the forward current flowing in the diode 16a of the synaptic processing unit 12, the timing of the current in the cell is adjusted according to the temperature of the memory transistor.

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