Pixel circuit and active array

Abstract

A pixel circuit includes a storage capacitor, a charging circuit, and an output circuit. The charging circuit is coupled to a first terminal and a second terminal of the storage capacitor and is configured to periodically change the potentials of the first terminal and the second terminal of the storage capacitor to maintain a storage voltage. The output circuit is coupled between a first system voltage and a second system voltage and is configured to receive the potentials of the first terminal and the second terminal from the storage capacitor to output the first system voltage or the second system voltage. The output circuit includes an output transistor. A first terminal of the output transistor outputs the first system voltage corresponding to the change of potential of the first terminal of the storage capacitor or the second system voltage corresponding to the change of potential of the second terminal of the storage capacitor, a second terminal of the output transistor is coupled to the second system voltage, and a control terminal of the output transistor is coupled to the second terminal of the storage capacitor to stabilize the voltage of the control terminal of the output transistor.

Description

Technical Field

[0001] This disclosure relates to a pixel circuit and an active array. Prior Technology

[0002] In medical testing devices and biochips, pixel circuits control the wettability of droplets through electric fields to achieve precise manipulation of digital microfluidics (DMF), which is widely used in biochemical analysis and detection. On the other hand, in electronic paper technology, pixel circuits control the distribution of electronic ink or electrophoretic particles through electric fields to change the pixel display state.

[0003] However, in practical applications, these pixel circuits often face problems such as insufficient driving force, driving voltage decay, and charge loss due to leakage current, which affect the accuracy of droplet manipulation and the stability of display quality. Summary of the Invention

[0004] Therefore, the embodiments disclosed herein provide a pixel circuit including a storage capacitor, a charging circuit, and an output circuit. The charging circuit is coupled to a first terminal and a second terminal of the storage capacitor and configured to periodically change the potential of the first and second terminals of the storage capacitor to maintain a stored voltage. The output circuit is coupled between a first system voltage and a second system voltage and configured to receive the potential of the first and second terminals from the storage capacitor to determine whether to output the first system voltage or the second system voltage. The output circuit includes an output transistor. The first terminal of the output transistor outputs the first system voltage in response to a change in the potential of the first terminal of the storage capacitor, and outputs the second system voltage in response to a change in the potential of the second terminal of the storage capacitor. The second terminal of the output transistor is coupled to the second system voltage, and its control terminal is coupled to the second terminal of the storage capacitor to stabilize the voltage at the control terminal of the output transistor via the storage capacitor.

[0005] According to an embodiment disclosed herein, the charging circuit includes a first transistor and a second transistor. A first terminal of the first transistor receives a first scan signal, a second terminal of the first transistor is coupled to a first terminal of a storage capacitor, and its control terminal receives a gate signal. A first terminal of the second transistor is coupled to a second terminal of the storage capacitor, a second terminal of the second transistor receives a second scan signal, and its control terminal receives a gate signal, wherein the second scan signal is the inverted signal of the first scan signal.

[0006] According to an embodiment disclosed herein, the output circuit further includes a third transistor and a first capacitor. A first terminal of the third transistor receives a first system voltage, a second terminal of the third transistor is coupled to the first terminal of the output transistor, and its control terminal is coupled to the first terminal of the storage capacitor. A first terminal of the first capacitor receives the first system voltage, and a second terminal of the first capacitor is coupled to the control terminal of the third transistor to stabilize the voltage at the control terminal of the third transistor.

[0007] According to the embodiments disclosed herein, during the gate signal triggering interval of the first frame, the first scan signal is at a low logic level corresponding to the high logic level of the gate signal, and the second scan signal is at a high logic level corresponding to the high logic level of the gate signal.

[0008] According to the embodiments disclosed herein, during the gate signal triggering interval of the first frame, the first transistor is turned on according to the gate signal and the first scan signal, and the second transistor is turned on according to the gate signal and the second scan signal, so as to transmit the second scan signal to the second terminal of the storage capacitor.

[0009] According to the embodiments disclosed herein, the third transistor is turned off in response to the conduction of the first transistor, and the output transistor is turned on in response to a second scan signal transmitted to the second terminal of the storage capacitor, and outputs a second system voltage during the first frame.

[0010] According to the embodiments disclosed herein, during the gate signal triggering interval in the second frame, the first scan signal is at a high logic level corresponding to the high logic level of the gate signal, and the second scan signal is at a low logic level corresponding to the high logic level of the gate signal.

[0011] According to the embodiments disclosed herein, during the gate signal triggering interval of the second frame, the first transistor is turned on according to the gate signal and the first scan signal, and the second transistor is turned on according to the gate signal and the second scan signal, so as to transmit the first scan signal to the first terminal of the storage capacitor.

[0012] According to the embodiments disclosed herein, the output transistor is turned off in response to the conduction of the second transistor, and the third transistor is turned on in response to the first scan signal transmitted to the first end of the storage capacitor, and outputs the first system voltage during the second frame.

[0013] The embodiments disclosed herein provide an active array comprising a plurality of pixel circuits as described above and a plurality of pixel electrodes. The pixel circuits are arranged in an array, and the pixel electrodes are each electrically connected to the pixel circuits to be driven by a first system voltage and a second system voltage periodically output by the pixel circuits. Simple Explanation of the Diagram

[0014] To make the above and other features, advantages and embodiments of the present invention more readily understood, the accompanying drawings are described below: Figure 1 is a schematic diagram of a pixel circuit according to an embodiment of the present invention; Figure 2 is a schematic diagram of the internal architecture of a pixel circuit according to an embodiment of the present invention; Figure 3 is a timing diagram of the drive signals of the pixel circuit according to an embodiment of the present invention; Figure 4 is a schematic diagram illustrating the operation of the pixel circuit during the gate signal triggering interval in the first frame according to an embodiment of the present invention; and Figure 5 is a schematic diagram illustrating the operation of the pixel circuit during the gate signal triggering interval in the second frame according to an embodiment of the present invention. Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided invention. The embodiments of components and configurations described below are merely examples and are not intended to be limiting. Furthermore, for simplicity and clarity, reference numerals and / or designations are repeated in the examples, but this does not itself limit the relationship between the various embodiments and / or components discussed.

[0016] Please refer to Figure 1, which is a schematic diagram of a pixel circuit 100 according to an embodiment of the present invention. The pixel circuit 100 includes a charging circuit 110, a storage capacitor CST, and an output circuit 120 to generate a driving voltage VE to drive the pixel electrode P. Embodiments of the present invention also include an active array, composed of a plurality of the pixel circuits 100 arranged in an array, wherein each pixel circuit 100 is coupled to a corresponding pixel electrode P to drive the pixel electrode P according to the driving voltage VE output by the output circuit 120.

[0017] The charging circuit 110 is coupled to the first terminal N1 and the second terminal N2 of the storage capacitor CST, and is configured to periodically change the potential of the first terminal N1 and the second terminal N2 of the storage capacitor CST to maintain the storage voltage of the storage capacitor CST. For example, during the operation of the pixel circuit 100 in the first frame, the charging circuit 110 changes the potential of the second terminal N2 of the storage capacitor CST; during the operation of the pixel circuit 100 in the second frame, the charging circuit 110 changes the potential of the first terminal N1 of the storage capacitor CST; and during the operation of the pixel circuit 100 in the third frame, the charging circuit 110 again changes the potential of the second terminal N2 of the storage capacitor CST. And so on, corresponding to the switching of the frame number, the charging circuit 110 periodically changes the potential of the first terminal N1 and the second terminal N2 of the storage capacitor CST.

[0018] It is worth noting that although the potentials of the first terminal N1 and the second terminal N2 of the storage capacitor CST change periodically with frame switching, the potential difference (i.e., storage voltage) between the two terminals of the storage capacitor CST remains a fixed value under steady state, but the direction of the potential difference flips with frame switching.

[0019] Output circuit 120 is coupled between a first system voltage VCC and a second system voltage VSS, and has an output terminal to generate a drive voltage VE. Output circuit 120 receives the potentials of a first terminal N1 and a second terminal N2 from a storage capacitor CST, and determines whether to output the first system voltage VCC or the second system voltage VSS corresponding to the potential of the first terminal N1 or the second terminal N2. In an embodiment of the invention, the second system voltage VSS is less than the first system voltage VCC, wherein the first system voltage VCC is a positive voltage to serve as the positive voltage amplitude of the drive voltage VE, and the second system voltage VSS is a negative voltage to serve as the negative voltage amplitude of the drive voltage VE.

[0020] Output circuit 120 includes an output transistor TS. A first terminal of the output transistor TS is coupled to a pixel electrode P and configured to generate a drive voltage VE via the operation of charging circuit 110, storage capacitor CST, and output circuit 120, thereby driving the pixel electrode P. A second terminal of the output transistor TS is coupled to a second system voltage VSS, and a control terminal of the output transistor TS is coupled to a second terminal of the storage capacitor CST, thereby stabilizing the voltage at the control terminal of the output transistor TS. Specifically, the storage capacitor CST is directly coupled to the control terminal of the output transistor TS, which can stabilize the voltage at the control terminal of the output transistor TS, thereby reducing the amplitude attenuation of the output drive voltage VE (e.g., stabilizing the negative voltage amplitude period when the drive voltage VE is the second system voltage VSS).

[0021] In detail, when the potential of the second terminal N2 of the storage capacitor CST is changed by the charging circuit 110, the first terminal of the output transistor TS outputs the second system voltage VSS (e.g., during the first frame), and when the potential of the first terminal N1 of the storage capacitor CST is changed by the charging circuit 110, the first terminal of the output transistor TS outputs the first system voltage VCC (e.g., during the second frame). This process continues, causing the driving voltage VE to change its value with each frame switch.

[0022] Please refer to Figure 2, which is a schematic diagram of the internal architecture of the pixel circuit 100 according to an embodiment of the present invention. The charging circuit 110 includes a first transistor T1 and a second transistor T2. The first terminal of the first transistor T1 receives a first scan signal S1, the second terminal of the first transistor T1 is coupled to the first terminal N1 of the storage capacitor CST, and the control terminal of the first transistor T1 receives a gate signal GT. The first terminal of the second transistor T2 is coupled to the second terminal N2 of the storage capacitor CST, the second terminal of the second transistor T2 receives a second scan signal S2, and the control terminal of the second transistor T2 receives the gate signal GT.

[0023] The output circuit 120 further includes a third transistor T3 and a first capacitor CH. The first terminal of the third transistor T3 receives the first system voltage VCC, the second terminal of the third transistor T3 is coupled to the first terminal of the output transistor TS, and the control terminal of the third transistor T3 is coupled to the first terminal N1 of the storage capacitor CST. The first terminal of the first capacitor CH receives the first system voltage VCC, and the second terminal of the first capacitor CH is coupled to the control terminal of the third transistor T3, thereby stabilizing the voltage at the control terminal of the third transistor T3. Specifically, the first capacitor CH is directly coupled to the control terminal of the third transistor T3, which can stabilize the voltage at the control terminal of the third transistor T3, thereby reducing the amplitude attenuation of the output drive voltage VE (for example, stabilizing the positive voltage amplitude period when the drive voltage VE is the first system voltage VCC). In embodiments of the present invention, the first transistor T1, the second transistor T2, the third transistor T3, and the output transistor TS are all N-type transistors.

[0024] In an embodiment of the present invention, the storage capacitor CST serves as the main capacitor for stabilizing the driving voltage VE, and its capacitance value is designed to be greater than that of the first capacitor CH to avoid amplitude attenuation of the driving voltage VE. In another embodiment, the capacitance value of the storage capacitor CST is at least six times greater than that of the first capacitor CH to maintain a high driving voltage VE and avoid amplitude attenuation of the driving voltage VE. In one embodiment, based on considerations of layout area and cost, the sum of the capacitance values ​​of the storage capacitor CST and the first capacitor CH is 1 picofarad (pF), wherein the capacitance value of the storage capacitor CST is, for example, 0.9 picofarad (pF), and the capacitance value of the first capacitor CH is, for example, 0.1 picofarad (pF), to ensure that the difference between their capacitance values ​​is at least six times, while simultaneously satisfying the condition that the sum of their capacitance values ​​is 1 picofarad (pF).

[0025] Please refer to Figure 3, which is a timing diagram of the drive signals of the pixel circuit 100 according to an embodiment of the present invention. Combined with Figures 4 and 5, which illustrate the operation of the pixel circuit 100 during the gate signal GT triggering intervals in the first frame FN and the second frame FN+1 respectively, the present invention can be better understood. In Figures 4 and 5, transistors marked with an "X" represent the off state, and transistors without an "X" represent the on state.

[0026] It should be understood that the operation of the pixel circuit 100 is cyclical, similar to its operation during the first frame FN and the second frame FN+1. For example, the operation of the pixel circuit 100 during the third frame FN+2 is the same as its operation during the first frame FN, generating a drive voltage VE with a negative voltage amplitude (second system voltage VSSE), while the operation of the pixel circuit 100 during the fourth frame FN+3 (not shown) is the same as its operation during the second frame FN+1, generating a drive voltage VE with a positive voltage amplitude (first system voltage VCCE).

[0027] In an embodiment of the present invention, the second scan signal S2 is the inverted signal of the first scan signal S1. It is noteworthy that the gate signal GT is triggered once per frame and has a high logic level interval tgh. During the first frame FN, when the gate signal GT is triggered, the first scan signal S1 corresponds to a low logic level (e.g., VSST) corresponding to the high logic level (e.g., VGH) of the gate signal GT, and the second scan signal S2 corresponds to a high logic level (e.g., VCCT) corresponding to the high logic level of the gate signal GT. During the second frame FN+1, when the gate signal GT is triggered, the first scan signal S1 corresponds to a high logic level corresponding to the high logic level of the gate signal GT, and the second scan signal S2 corresponds to a low logic level corresponding to the high logic level of the gate signal GT.

[0028] In the low logic level (e.g., VGL) range where the gate signal GT is not triggered, the first scan signal S1 and the second scan signal S2 continue the state in the high logic level range t gh, constantly switching between high and low logic levels (e.g., switching between VCCT and VSST).

[0029] In embodiments of the present invention, although the high logic level of the driving voltage VE is additionally labeled as VCCE, it is essentially the same as the first system voltage VCC, and although the low logic level of the driving voltage VE is additionally labeled as VSSE, it is essentially the same as the second system voltage VSS. The aforementioned "essential" means that, considering the on-resistance of the transistor and line losses, the two values ​​may have slight deviations.

[0030] As shown in Figure 4, corresponding to the high logic level interval tgh of the gate signal GT during the first frame FN period, the first transistor T1 is turned on based on the voltage difference between the gate signal GT and the first scan signal S1, and the second transistor T2 is turned on based on the voltage difference between the gate signal GT and the second scan signal S2, so as to transmit the second scan signal S2 to the second terminal N2 of the storage capacitor CST, so that the second terminal N2 of the storage capacitor CST is a positive voltage VCCT.

[0031] The conduction of the first transistor T1 causes the first scan signal S1 to be written to the control terminal of the third transistor T3, making the first terminal N1 of the storage capacitor CST a negative voltage VSST, and the third transistor T3 is turned off accordingly. The conduction of the second transistor T2 causes the second scan signal S2 to be written to the control terminal of the output transistor TS, and the output transistor TS is turned on accordingly, outputting the second system voltage VSS at the first terminal of the output transistor TS.

[0032] As shown in Figure 5, during the high logic level interval tgh of the gate signal GT during the second frame F N+1, the first transistor T1 is turned on based on the voltage difference between the gate signal GT and the first scan signal S1, and the second transistor T2 is turned on based on the voltage difference between the gate signal GT and the second scan signal S2, so as to transmit the first scan signal S1 to the first terminal N1 of the storage capacitor CST, making the first terminal N1 of the storage capacitor CST a positive voltage VCCT.

[0033] The conduction of the second transistor T2 causes the second scan signal S2 to be written to the control terminal of the output transistor TS, making the second terminal N2 of the storage capacitor CST a negative voltage VSST, and the output transistor TS is turned off accordingly. The conduction of the first transistor T1 causes the first scan signal S1 to be written to the control terminal of the third transistor T3, the third transistor T3 is turned on accordingly, and the first system voltage VCC is output at the first terminal of the output transistor TS.

[0034] It is worth noting that when the pixel circuit 100 operates during the first frame FN, the storage capacitor CST is directly coupled to the control terminal of the output transistor TS, thus preventing the attenuation of the second system voltage VSS of the driving voltage VE. When the pixel circuit 100 operates during the second frame FN+1, the charging path of the storage capacitor CST only needs to pass through the first transistor T1 and the second transistor T2, which can increase the driving force of the first system voltage VCC of the driving voltage VE. With minimal attenuation of the second system voltage VSS and sufficient driving force of the first system voltage VCC, the pixel circuit can improve the accuracy of droplet manipulation or the stability of display quality.

[0035] In summary, the pixel circuit of this invention can effectively solve the problems of insufficient driving force, driving voltage decay, and charge loss caused by leakage current in conventional pixel circuits by shortening the charging path of the storage capacitor and directly coupling the storage capacitor to the control terminal of the output transistor.

[0036] Although the present invention has been disclosed above with various embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0037] 100: Pixel circuit 110: Charging circuit 120: Output Circuit C ST: Storage capacitor CH: First Capacitor FN: First Frame F N+1: Second frame F N+2: Third frame GT: Gate signal N1: First end N2: Second end P: Pixel electrode S1: First scan signal S2: Second scan signal T1: First transistor T2: Second transistor T3: Third transistor TS: Output Transistor t gh: High logic level interval VCC: First System Voltage VE: Driving voltage VSS: Second System Voltage VGH, VCCT, VCCE: High logic levels VGL, VSST, VSSE: Low logic levels

Claims

1. A pixel circuit, comprising: a storage capacitor; a charging circuit coupled to a first terminal and a second terminal of the storage capacitor and configured to periodically change the potential of the first terminal and the second terminal of the storage capacitor to maintain a storage voltage, wherein the charging circuit comprises: a first transistor, the first terminal of which receives a first scan signal, the second terminal of which is coupled to the first terminal of the storage capacitor, and the control terminal of which receives a gate signal; and a second transistor, the first terminal of which is coupled to the second terminal of the storage capacitor, the second terminal of which receives a second scan signal, and the control terminal of which receives the gate signal, wherein the second scan signal is an inverted signal of the first scan signal; and an output circuit coupled between a first system voltage and a second system voltage, and configured to receive the potential of the first terminal and the second terminal of the storage capacitor to determine whether to output the first system voltage or the second system voltage, wherein the output circuit comprises: An output transistor has a first terminal that outputs a first system voltage in response to a potential change at the first terminal of a storage capacitor, or outputs a second system voltage in response to a potential change at the second terminal of a storage capacitor. Its second terminal is coupled to the second system voltage, and its control terminal is coupled to the second terminal of the storage capacitor, so as to stabilize the voltage at the control terminal of the output transistor by means of the storage capacitor.

2. The pixel circuit as claimed in claim 1, wherein the output circuit further comprises: a third transistor having a first terminal receiving the first system voltage, a second terminal coupled to the first terminal of the output transistor, and a control terminal coupled to the first terminal of the storage capacitor; and a first capacitor having a first terminal receiving the first system voltage and a second terminal coupled to the control terminal of the third transistor to stabilize the voltage at the control terminal of the third transistor.

3. The pixel circuit as described in claim 2, wherein during a first frame, the gate signal is triggered in a period where the first scan signal is at a low logic level corresponding to a high logic level of the gate signal, and the second scan signal is at a high logic level corresponding to a high logic level of the gate signal.

4. The pixel circuit as described in claim 3, wherein during the gate signal triggering interval of the first frame, the first transistor is turned on according to the gate signal and the first scan signal, and the second transistor is turned on according to the gate signal and the second scan signal to transmit the second scan signal to the second terminal of the storage capacitor.

5. The pixel circuit as claimed in claim 4, wherein the third transistor is turned off in response to the conduction of the first transistor, and the output transistor is turned on according to the second scan signal transmitted to the second terminal of the storage capacitor, and outputs the second system voltage during the first frame.

6. The pixel circuitry as described in claim 2, wherein during a second frame, the gate signal is triggered in the interval where the first scan signal is at a high logic level corresponding to the high logic level of the gate signal, and the second scan signal is at a low logic level corresponding to the high logic level of the gate signal.

7. The pixel circuit as described in claim 6, wherein during the gate signal triggering interval of the second frame, the first transistor is turned on according to the gate signal and the first scan signal, and the second transistor is turned on according to the gate signal and the second scan signal, so as to transmit the first scan signal to the first terminal of the storage capacitor.

8. The pixel circuit as claimed in claim 7, wherein the output transistor is turned off in response to the conduction of the second transistor, and the third transistor is turned on in accordance with the first scan signal transmitted to the first terminal of the storage capacitor and outputs the first system voltage during the second frame.

9. An active array comprising: a plurality of pixel circuits as described in claim 1, wherein the pixel circuits are arranged in an array; and a plurality of pixel electrodes, each coupled to the pixel circuits, to be driven by a first system voltage and a second system voltage periodically output by the pixel circuits.

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