Semiconductor memory devices and controllers

Abstract

This invention provides a memory system capable of high-speed operation. The semiconductor memory device includes: a first pin for data input / output; a second pin for data input / output; a third pin for receiving a clock signal from a controller; a fourth pin; and a memory cell array comprising a string of multiple memory cell transistors connected in series. The semiconductor memory device is configured to perform: a first data output method, which outputs data from the second pin based on a clock signal input to the third pin, and outputs a strobe signal from the first pin synchronously with the data; and a second data output method, which outputs data from both the first and second pins based on a clock signal input to the third pin, and outputs a strobe signal from the fourth pin synchronously with the data.

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