Memory system

Abstract

A high-speed memory system is provided. It comprises a plurality of semiconductor memory devices and a control device. Each semiconductor memory device includes: a first signal pad on which a first signal is input; a second signal pad on which a second signal is input; a third signal pad on which a third signal is input; a fourth signal pad on which a fourth signal is input; a first input / output circuit that receives the second signal in response to a switching of the first signal; and a second input / output circuit that outputs user data from the fourth signal pad in response to a switching of the third signal; a memory cell array comprising strings; a first switching circuit connecting the third signal pad to the first input / output circuit; a decoding circuit connected to the first switching circuit; and a sequencer comprising a feature register. The decoding circuit controls the ON and OFF states of the first switching circuit in response to the first control parameter displayed by the feature register and the signal from the sequencer when the semiconductor memory device sends out data.

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