Memory device including assist circuit for adjusting voltage level of wordline

Abstract

A memory device includes a memory cell array including memory cells, a row decoder that selects one of wordlines connected to the memory cells, based on an address received from a memory controller, and a wordline voltage generator that provides a wordline voltage to a selected wordline. The wordline voltage generator includes wordline drivers that respectively correspond to the wordlines, and wordline underdrive circuits that respectively correspond to the wordlines and that lower wordline voltage levels that are output by the wordline drivers by different voltage levels based on the address.

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