Hybrid data storage method of flash memory and storage device using the hybrid data storage method

Abstract

A hybrid data storage method of flash memory includes the following steps: using an X-level cell method to store data in at least one memory block of the flash memory; perform automatic error correction code on the at least one memory block to determine whether an error bit rate of at least one word line in the at least one memory block exceeds a threshold value; when it is confirmed that the error bit rate exceeds the threshold value, the data storage method corresponding to the at least one word line in the at least one memory block that meets the error bit rate exceeds the threshold value is used in the X-level cell storage method is converted into a single-level cell method; and when it is confirmed that the error bit rate does not exceed the threshold value, the data storage method corresponding to the at least one word line in the at least one memory block is maintained as the X-level cell storage method. Thus, the hybrid data storage method of flash memory of the present invention can solve the problem of wasting available storage space of the memory. A storage device using the hybrid data storage method is also proposed.

Description

Technical Field

[0001] This invention relates to a method for storing data in flash memory, and more particularly to a hybrid data storage method for flash memory and a storage device employing the hybrid data storage method. Prior Technology

[0002] A solid-state drive (SSD) is a data storage device made of integrated circuits. Common SSD devices use non-volatile memory as the main data storage element.

[0003] In recent years, SSDs have become increasingly popular among users due to their advantages over traditional hard drives, including smaller size, greater durability, lighter weight, greater portability, noiseless operation, and faster access speeds. However, as the memory in an SSD undergoes repeated write and erase operations, its data retention capacity may decrease, and data storage errors may even occur.

[0004] Therefore, memory block management methods are usually used to mark blocks with poor data storage capabilities as "bad blocks" to avoid storing data in the aforementioned "bad blocks," which could lead to errors in read, write, or erase operations. Summary of the Invention

[0005] Because the memory management method described above marks an entire block of data in the SSD's memory with problematic data retention capabilities as a "bad block," the SSD will not use these "bad blocks" to store data. This means that the entire block marked as a "bad block" can no longer be used. However, there is still other usable storage space (e.g., pages) within the "bad block." Therefore, the memory management method described above wastes usable storage space in the memory.

[0006] To address the aforementioned problems, the present invention aims to provide a hybrid data storage method for flash memory, comprising the following steps: storing data in at least one memory block of flash memory using an X-level storage cell method; executing an automatic error correction code (ECC) on the at least one memory block to confirm whether the error bit rate of at least one word line in the at least one memory block exceeds a critical value; when the error bit rate is confirmed to exceed the critical value, converting the data storage method corresponding to the at least one word line in the at least one memory block that meets the condition of the error bit rate exceeding the critical value from the X-level storage cell method to the single-level storage cell (SLC) method; and when the error bit rate is confirmed not to exceed the critical value, maintaining the data storage method corresponding to the at least one word line in the at least one memory block as the X-level storage cell method.

[0007] In one embodiment, after confirming that the error bit rate exceeds the threshold, the step of changing the data storage mode corresponding to at least one word line in at least one memory block that meets the error bit rate exceeding the threshold from the X-level storage unit mode to the single-level storage unit mode, further includes the step of recording the word line corresponding to the single-level storage unit mode in the word line management table.

[0008] In one embodiment, after the step of converting the data storage mode corresponding to at least one word line in at least one memory block that meets the condition of exceeding the critical value from the X-level storage cell mode to the single-level storage cell mode when it is confirmed that the error bit rate exceeds the critical value, the at least one memory block includes word lines using the X-level storage cell mode and word lines using the single-level storage cell mode.

[0009] In one embodiment, the threshold value can be adjusted.

[0010] In one embodiment, the X-level storage cell method is a two-level storage cell (multilevel cell, MLC) method, a three-level storage cell (triple-level cell, TLC) method, a four-level storage cell (quad-level cell, QLC) method, or a five-level storage cell (penta-level cell, PLC) method.

[0011] To address the aforementioned problems, another objective of the present invention is to provide a data storage device employing a hybrid data storage method, comprising: a controller; a memory electrically coupled to the controller and configured to store firmware code; and a plurality of flash memories electrically coupled to and communicating with the controller; wherein, after the firmware code is executed by the controller, the following steps are performed: storing data in at least one memory block of the plurality of flash memories using an X-level storage cell method; executing automatic error correction code on the at least one memory block to confirm whether the error bit rate of at least one word line in the at least one memory block exceeds a critical value; when the error bit rate is confirmed to exceed the critical value, converting the data storage mode corresponding to the at least one word line in the at least one memory block that meets the condition of the error bit rate exceeding the critical value from the X-level storage cell method to a single-level storage cell method; and when the error bit rate is confirmed not to exceed the critical value, maintaining the data storage mode corresponding to the at least one word line in the at least one memory block as the X-level storage cell method.

[0012] In summary, the hybrid data storage method for flash memory and the storage device employing this hybrid data storage method of the present invention check and convert data storage methods on a word-line basis, thereby improving the storage space utilization of each memory block in the data storage device. Furthermore, the present invention dynamically manages the flash memory in the data storage device through the hybrid data storage method, achieving the goals of flexibly improving the data access speed of some word lines (i.e., after being converted to a single-level storage unit mode), improving the durability of some word lines, and extending the lifespan of the data storage device. Simple Explanation of the Diagram

[0013] Figure 1 is a system block diagram showing a data storage device according to an embodiment of the present invention. Figure 2 is a schematic diagram showing the memory block of an embodiment of the present invention. Figure 3 is a schematic diagram showing the word line when the bit rate of a memory block exceeds a critical value in an embodiment of the present invention. Figure 4 is another schematic diagram showing the word line when the bit rate of a memory block exceeds the critical value in an embodiment of the present invention. Figure 5 is a schematic diagram showing the character line management table according to an embodiment of the present invention. Figure 6 is a flowchart illustrating a hybrid data storage method according to an embodiment of the present invention. Figure 7 is a flowchart showing another embodiment of the hybrid data storage method of the present invention. Implementation

[0014] Please refer to Figure 1, which is a system block diagram showing a data storage device 100 according to an embodiment of the present invention. As shown in Figure 1, the data storage device 100 may include a controller 10, a memory 20, and n flash memories FL0~FLn, where n is a natural number greater than or equal to 1.

[0015] The controller 10 is configured to be electrically coupled to and communicate with flash memory FL0~FLn. The controller 10 can control read operations, write operations and erase operations of flash memory FL0~FLn.

[0016] Memory 20 is electrically coupled to controller 10. Memory 20 is configured to store firmware code 22. Memory 20 may be composed of non-volatile memory.

[0017] Firmware code 22 can be stored in memory 20. In other embodiments, firmware code 22 can also be stored in the memory of controller 10 (not shown). After firmware code 22 is executed by controller 10, the following steps can be performed: storing data in one of the memory blocks BLK0 to BLKn of flash memory FL0 to FLn using an X-level storage unit method; executing automatic error correction code on memory blocks BLK0 to BLKn to confirm whether the error bit rate of the word lines in memory blocks BLK0 to BLKn exceeds a critical value; when the error bit rate is confirmed to exceed the critical value, changing the data storage method corresponding to the word lines in memory blocks BLK0 to BLKn that meet the error bit rate exceeding the critical value from the X-level storage unit method to the single-level storage unit method; and when the error bit rate is confirmed not to exceed the critical value, maintaining the data storage method corresponding to the word lines in memory blocks BLK0 to BLKn as the X-level storage unit method, where X is a positive integer.

[0018] Furthermore, in this embodiment, the X-level storage cell method can be, for example, a two-level, three-level, four-level, or five-level storage cell method, or other higher-level data storage cell methods using NAND technology. The aforementioned two-level storage cell method has a higher data access speed than the three-level storage cell method, and a lower data storage capacity than the three-level storage cell method. The aforementioned three-level storage cell method has a higher data access speed than the four-level storage cell method, and a lower data storage capacity than the four-level storage cell method. The aforementioned four-level storage cell method has a higher data access speed than the five-level storage cell method, and a lower data storage capacity than the five-level storage cell method, and so on. In other words, the X-level storage cell method has a higher data access speed than the X+1-level storage cell method, and a lower data storage capacity than the X+1-level storage cell method. Furthermore, the X-level storage unit method described above has a lower data access speed than the single-level storage unit method, and the X-level storage unit method described above has a higher data storage capacity than the single-level storage unit method.

[0019] In other words, single-level storage offers the fastest data access speed compared to X-level storage. Furthermore, single-level storage provides approximately 100,000 programmable iterations (P / E), two-level storage provides approximately 10,000 P / E, three-level storage provides approximately 3,000 P / E, and four-level storage provides approximately 1,000 P / E. Here, P refers to programming and E refers to erasure. Therefore, single-level storage offers superior endurance compared to X-level storage; that is, single-level storage has the highest endurance.

[0020] Flash memories FL0-FLn are electrically coupled to controller 10. Flash memories FL0-FLn can communicate with controller 10. Flash memories FL0-FLn are configured to be controlled by controller 10 to perform data read, write, and erase operations. Flash memory FL0 has a plurality of memory blocks BLK0-BLKn, and so on, each of flash memories FL0-FLn has a plurality of memory blocks BLK0-BLKn.

[0021] In other embodiments, the data storage device 100 further includes a character line management table 30. The character line management table 30 is connected to the controller 10. The character line management table 30 is configured to record information related to character lines used in an X-level storage unit configuration and character lines used in a single-level storage unit configuration. The controller 10 can use the aforementioned information provided by the character line management table 30 to control the flash memory FL0~FLn to perform read, write, and erase operations in specific data storage modes.

[0022] In other embodiments, the character line management table 30 can be stored in memory 20 and connected to controller 10 to provide the aforementioned related information to controller 10. Furthermore, after the step of converting the data storage mode corresponding to the character lines in memory blocks BLK0~BLKn that meet the error bit rate exceeding the threshold from X-level storage unit mode to single-level storage unit mode when the error bit rate is confirmed to exceed the threshold, memory blocks BLK0~BLKn include character lines using X-level storage unit mode and character lines using single-level storage unit mode, i.e., a hybrid data storage mode.

[0023] Please refer to Figure 2, which is a schematic diagram showing memory blocks BLK0~BLKn according to an embodiment of the present invention. As shown in Figure 2, each of the memory blocks BLK0~BLKn in the data storage device 100 includes a plurality of word lines WL0~WLn and a plurality of bit lines BL0~BLn. Regions where the plurality of word lines WL0~WLn and the plurality of bit lines BL0~BLn intersect each other perpendicularly can form a plurality of memory cells (not labeled in the figure). The aforementioned memory cell refers to the smallest structure used for accessing data.

[0024] In the preset data storage mode of the data storage device 100, memory blocks BLK0~BLKn can be configured to provide storage capacity with the same capacity as each other. For example, memory block BLK0 can provide storage capacity Y0, memory block BLK1 can provide storage capacity Y0, ..., memory block BLKn can provide storage capacity Y0.

[0025] Please refer to Figure 3, which is a schematic diagram illustrating the word line in memory blocks BLK0~BLKn where the error bit rate exceeds a threshold value according to an embodiment of the present invention. As shown in Figure 3, after the automatic error correction code is executed in memory blocks BLK0~BLKn, and it is confirmed that the error bit rate (e.g., 50.1%) of word line WL5 in memory block BLK0 exceeds the threshold value (e.g., 50%), the controller 10 can change the data storage mode corresponding to word line WL5 in memory block BLK0 where the error bit rate exceeds the threshold value from X-level storage unit mode to single-level storage unit mode. The aforementioned word line WL5 can be labeled as a high error bit rate word line SL0. In other embodiments, the threshold value can be set and adjusted by the user, that is, the threshold value is adjustable, and the threshold value can be between 20% and 80% of the number of error correction bits, but is not limited thereto.

[0026] After word line WL5 in memory block BLK0 is marked as word line SL0 with a high error bit rate, the storage capacity provided by memory block BLK0 changes from storage capacity Y0 to storage capacity Y1, where storage capacity Y1 is less than storage capacity Y0. Since no word lines with error bit rates exceeding the critical value occur in memory blocks BLK1 to BLKn, memory blocks BLK1 continue to provide storage capacity Y0, ..., and memory blocks BLKn continue to provide storage capacity Y0.

[0027] It is worth noting that since some memory cells can still be used in the word line SL0 with a high error bit rate, the embodiment of the present invention can continue to use the word line SL0 with a high error bit rate in the memory block BLK0 to access data. Compared with the conventional memory management method, which marks the entire block with data retention problems in the memory of the SSD device as a "bad block" and then the SSD device will not use the aforementioned "bad block" to store data, the embodiment of the present invention has a higher storage space utilization rate.

[0028] In addition, when the high error rate word line SL0 is changed from the X-level storage cell method to the single-level storage cell method, although the overall data storage capacity of the high error rate word line SL0 decreases, the data access speed is significantly improved, and the durability is also improved.

[0029] In other words, the embodiments of the present invention perform inspection and conversion on a word line-by-word basis to improve the storage space utilization of memory blocks BLK0~BLKn in the data storage device 100, and can flexibly improve the data access speed of some word lines (i.e. after being converted to single-level storage unit mode), as well as improve the durability of some word lines and extend the service life of the data storage device 100.

[0030] Please refer to Figure 4, which is another schematic diagram illustrating how, according to an embodiment of the present invention, when the error bit rate of word lines in memory blocks BLK0~BLKn exceeds a critical value, the error bit rate of word line WL5 (e.g., 50.1%) and the error bit rate of word line WL0 (e.g., 53%) in memory blocks BLK0~BLKn both exceed the critical value (e.g., 50%). The controller 10 can then convert the data storage mode corresponding to word lines WL5 and WL0 in memory block BLK0, which have error bit rates exceeding the critical value, from an X-level storage unit mode to a single-level storage unit mode. The aforementioned word line WL5 can be labeled as a high error bit rate word line SL0, and the aforementioned word line WL0 can be labeled as a high error bit rate word line SL1.

[0031] After word line WL5 in memory block BLK0 is marked as a high error rate word line SL0, and word line WL0 is marked as a high error rate word line SL1, the storage capacity available for memory block BLK0 changes from storage capacity Y0 to storage capacity Y2, where storage capacity Y2 is less than storage capacity Y0. Since no word lines in memory blocks BLK1~BLKn have an error rate exceeding the critical value, memory blocks BLK1 continue to provide storage capacity Y0, ..., and memory blocks BLKn continue to provide storage capacity Y0.

[0032] Please refer to Figure 5, which is a schematic diagram showing the character line management table 30 of an embodiment of the present invention. As shown in Figure 5, the character line management table 30 can record the data storage method used by character lines WL0~WLn in memory blocks BLK0~BLKn. When the data storage method corresponding to a character line in memory blocks BLK0~BLKn that meets the error bit rate exceeding the threshold value is changed from X-level storage cell mode to single-level storage cell mode, the controller 10 can update the character line management table 30 and control the data storage device 100 to operate with the updated character line management table 30.

[0033] Please refer to Figure 6, which is a flowchart showing the hybrid data storage method according to an embodiment of the present invention. As shown in Figure 6, in step S600, the controller 10 stores data in memory blocks BLK0~BLKn of flash memory FL0~FLn using an X-level storage unit method.

[0034] In step S602, the controller 10 executes automatic error correction code on memory blocks BLK0~BLKn.

[0035] Step S604: Confirm whether the error bit rate of word lines WL0~WLn in memory blocks BLK0~BLKn exceeds the critical value. If the determination is "No", proceed to step S608. If the determination is "Yes", proceed to step S606.

[0036] Step S606: When it is confirmed that the error bit rate exceeds the critical value, the data storage mode corresponding to the word lines WL0~WLn in memory blocks BLK0~BLKn that meet the error bit rate exceeding the critical value is changed from the X-level storage unit mode to the single-level storage unit mode.

[0037] Step S608: When it is confirmed that the error bit rate has not exceeded the critical value, the data storage mode corresponding to the word lines WL0~WLn in the memory blocks BLK0~BLKn is maintained as the X-level storage unit mode, and the process returns to step S600.

[0038] Please refer to Figure 7, which is a flowchart showing another embodiment of the hybrid data storage method of the present invention. The difference between the embodiment in Figure 7 and the embodiment in Figure 6 is that after step S606 in Figure 7, step S610 is also included. The remaining steps are the same as or similar to those in Figure 6, and will not be described again here.

[0039] In step S610, the controller 10 records the character lines corresponding to the single-level storage unit method in the character line management table 30. Therefore, the controller 10 can control the data storage device 100 to perform data read, write, or erase operations by updating the character line management table 30.

[0040] In summary, the hybrid data storage method for flash memory and the storage device employing this hybrid data storage method of the present invention check and convert data storage methods on a word-line basis, thereby improving the storage space utilization of each memory block in the data storage device. Furthermore, the present invention dynamically manages the flash memory in the data storage device through the hybrid data storage method, achieving the goals of flexibly improving the data access speed of some word lines (i.e., after being converted to a single-level storage unit mode), improving the durability of some word lines, and extending the lifespan of the data storage device.

[0041] 10: Controller 20: Memory 22: Firmware Code 30: Character Line Management Table 100: Data storage device BL0: Bitline BL1: Bitline BL2: Bitline BL3: Bitline BLn: Bitline BLK0: Memory block BLK1: Memory Block BLKn: Memory Block FL0: Flash Memory FLn: Flash Memory SL0: Word line with high error bit rate SL1: Word line with high error bit rate WL0: Character Line WL1: Character Line WL2: Character Line WL3: Character Line WL4: Character Line WL5: Character Line WL6: Character Line WL7: Character Line WL8: Character Line WLn: Character Line S600, S602, S604, S606, S608, S610: Steps

Claims

1. A hybrid data storage method for flash memory, comprising the following steps: storing data in at least one memory block of the flash memory using an X-level storage cell method, where X is a positive integer; executing automatic error correction code on the at least one memory block to confirm whether an error bit rate of at least one word line in the at least one memory block exceeds a threshold value; when confirming that the error bit rate exceeds the threshold value, converting the data storage method corresponding to the at least one word line in the at least one memory block that meets the condition of the error bit rate exceeding the threshold value from the X-level storage cell method to a single-level storage cell method; and when confirming that the error bit rate does not exceed the threshold value, maintaining the data storage method corresponding to the at least one word line in the at least one memory block as the X-level storage cell method.

2. The hybrid data storage method for flash memory as described in claim 1, wherein after confirming that the error bit rate exceeds the threshold, the step of converting the data storage mode corresponding to the at least one word line in the at least one memory block that meets the condition of the error bit rate exceeding the threshold from the X-level storage cell mode to a single-level storage cell mode, the method further includes the step of recording the word line corresponding to the single-level storage cell mode in a word line management table.

3. The hybrid data storage method for flash memory as described in claim 1, wherein after the step of converting the data storage mode corresponding to the at least one word line in the at least one memory block that meets the condition that the error bit rate exceeds the threshold from the X-level storage cell mode to a single-level storage cell mode when it is confirmed that the error bit rate exceeds the threshold, the at least one memory block includes word lines using the X-level storage cell mode and word lines using the single-level storage cell mode.

4. The hybrid data storage method for flash memory as described in claim 1, wherein the threshold value is adjustable.

5. The hybrid data storage method for flash memory as described in claim 1, wherein the X-level storage unit is a first-second-level storage unit, a first-third-level storage unit, a first-fourth-level storage unit, or a first-fifth-level storage unit.

6. A data storage device employing a hybrid data storage method, comprising: One controller; A memory, electrically coupled to the controller, is configured to store firmware code; A plurality of flash memories are electrically coupled to and communicate with the controller; wherein, after the firmware code is executed by the controller, the following steps are performed: Data is stored in at least one memory block of the plurality of flash memories using an X-level storage cell method, where X is a positive integer; Automatic error correction code is executed on the at least one memory block to confirm whether the error bit rate of at least one word line in the at least one memory block exceeds a threshold value; and when it is confirmed that the error bit rate exceeds the threshold value, the data storage method corresponding to the at least one word line in the at least one memory block that meets the condition of the error bit rate exceeding the threshold value is changed from the X-level storage cell method to a single-level storage cell method; When it is confirmed that the error bit rate does not exceed the threshold value, the data storage method corresponding to the at least one word line in the at least one memory block is maintained as the X-level storage cell method.

7. The data storage device employing a hybrid data storage method as described in claim 6, wherein after the step of converting the data storage mode corresponding to the at least one word line in the at least one memory block that meets the condition of the error bit rate exceeding the threshold from the X-level storage cell mode to a single-level storage cell mode when it is confirmed that the error bit rate exceeds the threshold, the device further includes the step of recording the word line corresponding to the single-level storage cell mode in a word line management table.

8. The data storage device employing a hybrid data storage method as described in claim 6, wherein after the step of converting the data storage mode corresponding to the at least one word line in the at least one memory block that meets the condition that the error bit rate exceeds the threshold from the X-level storage cell mode to a single-level storage cell mode when it is confirmed that the error bit rate exceeds the threshold, the at least one memory block includes word lines using the X-level storage cell mode and word lines using the single-level storage cell mode.

9. A data storage device employing a hybrid data storage method as described in claim 6, wherein the threshold value is adjustable.

10. The data storage device employing a hybrid data storage method as described in claim 6, wherein the X-level storage unit configuration is a first-second-level storage unit configuration, a first-third-level storage unit configuration, a first-fourth-level storage unit configuration, or a first-fifth-level storage unit configuration.

Images