Fast program of non-volatile memory cells
TW202640620APending Publication Date: 2026-10-01SILICON STORAGE TECHNOLOGY INC
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Patent Information
- Application Number
- TW115104536
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-05-14
- Filing Date
- 2026-02-05
- Publication Date
- 2026-10-01
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Abstract
A method of operating a semiconductor device by applying positive voltages to a select gate and to a source region wherein current flows from the source region, through a channel region and to a bit line to increase a voltage on the bit line, after which a drain program voltage is maintained on the bit line whereby electrons from the current through the channel region are injected onto the floating gate. A method can include applying positive voltages to the select gate and to the source region and electrically coupling a voltage source to the bit line to decrease a voltage on the bit line, after which a drain program voltage is maintained on the bit line whereby current flows from the source region, through the channel region and to the bit line, and electrons from the current through the channel region are injected onto the floating gate.
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