Memory device

Abstract

This invention provides a semiconductor memory device that can improve operating speed. The semiconductor memory device 1 of one embodiment includes peripheral circuitry 13, a memory cell array 10, upper component lines (BLU), and first and second connection portions (RCU1 and RCU2). The memory cell array 10 is disposed on the peripheral circuitry 13 and includes a first region R1 and a second region R2. The upper component lines (BLU) are disposed on the memory cell array 10 along a first direction D1. The first and second connection portions (RCU1 and RCU2) each include contact plugs (CP1) arranged along a second direction D2 orthogonal to the first direction D1, and each is disposed between the first and second regions R1 and R2. The upper component lines (BLU) include: a first upper component line (odd-numbered bit line) connected to the peripheral circuitry 13 via the first connection portion (RCU1); and a second upper component line (even-numbered bit line) connected to the peripheral circuitry 13 via the second connection portion (RCU2).

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