Method and circuit for bit read during non-volatile memory power-on-reset

Abstract

Embodiments of the present disclosure provide a memory circuit, including: a non-volatile memory; a one-time-programmable memory; a sense amplifier coupled to the non-volatile memory and the one-time-programmable memory; a digital register coupled to an output of the sense amplifier for storing reference resistance bits; control logic coupled to an output of the digital register; a decoder coupled to an output of the control logic; and a controller for outputting a control signal to the control logic to select a first reference resistance for the sense amplifier from the decoder for a reading of bits from the one-time-programmable memory, and to select a second reference resistance for the sense amplifier from the decoder for a reading of bits from the non-volatile memory.

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