Extending the stop fine mode for improving performance and power by reducing verify and scan operations

Abstract

A memory apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to data states. The data states include a highest data state in which the threshold voltage of the memory cells associated therewith is higher than for others of the data states. A control means is configured to apply each of a series of programming pulses of a program voltage followed by verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines to program and verify the memory cells connected thereto during each of a plurality of program loops of a program operation. The control means is also configured to skip verification of the memory cells targeted for at least one of the others of the data states in at least one of the plurality of program loops.

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