Semiconductor memory devices

Abstract

This invention improves reliability. According to one embodiment, the semiconductor memory device includes: a memory cell array comprising memory cells; word lines connected to the memory cells; a column decoder connected to the word lines; a first wiring connected to the column decoder; a voltage generation circuit that charges and discharges the word lines via the first wiring and the column decoder; a detection circuit included in the voltage generation circuit that outputs a first signal based on the discharge of the word lines; and a determination circuit that determines whether the word lines are good or defective based on the first signal.

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