Failure bits detection circuit, failure bits detection method, and memory device

Abstract

A failure bits detection circuit, a failure bits detection circuit method, and a memory device are provided herein. A current mirror includes a first end coupled to a page buffer of a memory device and a second end coupled to a criteria generator, and mirrors a sensing current at the first end to generate a criteria current at the second end during a read mode. The criteria generator provides a criteria load between the second end and a reference ground end according to a criteria code. A comparator compares a first voltage at a first input end of the comparator with a second voltage at a second input end of the comparator to generate a detection result at the output end for determining a failure bits number of the memory device. In this manner, a 3D NAND flash memory with high capacity and high performance is achieved.

Description

Technical Field

[0001] This disclosure relates to an error bit detection circuit; and more particularly to an error bit detection circuit, an error bit detection method, and a memory device. Prior Technology

[0002] With technological advancements, memory devices often increase memory cell density by stacking multiple layers of memory cells. As the number of memory cells increases significantly, fault bit detection mechanisms become crucial. Summary of the Invention

[0003] This disclosure relates to an error bit detection circuit, an error bit detection method, and a memory device to improve the accuracy and speed of error bit detection in a memory device.

[0004] This disclosure provides an error bit detection circuit. The error bit detection circuit includes a current mirror, an index generator, and a comparator. The current mirror includes a first terminal coupled to a page buffer of a memory device and a second terminal coupled to the index generator, and is configured to mirror a sensed current at the first terminal of the current mirror during a read mode of the memory device to generate an index current at the second terminal of the current mirror. The index generator is configured to provide an index load between the second terminal of the current mirror and a reference ground terminal according to an index code. The comparator includes a first input terminal coupled to the first terminal of the current mirror, a second input terminal coupled to the second terminal of the current mirror, and an output terminal. The index generator is configured to compare a first voltage at the first input terminal with a second voltage at the second input terminal to generate a detection result at the output terminal for determining the number of error bits in the memory device.

[0005] This disclosure provides an error bit detection method. The error bit detection method includes the following steps: during a read mode of a memory device, a sensed current at a first end of a current mirror is mirrored to generate an index current at a second end of the current mirror, wherein the first end of the current mirror is coupled to a page buffer of the memory device, and the second end of the current mirror is coupled to an index generator; an index load is provided between the second end of the current mirror and a reference ground terminal according to an index code; a first voltage at a first input terminal of a comparator is compared with a second voltage at a second input terminal of the comparator to generate a detection result for determining the number of error bits in the memory device.

[0006] This disclosure provides a memory device. The memory device includes a plurality of memory cell segments and a plurality of error bit detection circuits. Each of the plurality of segments includes a page buffer. Each of the plurality of error bit detection circuits is respectively coupled to the page buffer. Each of the plurality of error bit detection circuits includes a current mirror, an index generator, and a comparator. The current mirror includes a first terminal coupled to the page buffer of the memory device and a second terminal coupled to the index generator, and is configured to mirror a sensed current at the first terminal of the current mirror during a read mode of the memory device to generate an index current at the second terminal of the current mirror. The index generator is configured to provide an index load between the second terminal of the current mirror and a reference ground terminal according to an index code. The comparator includes a first input terminal coupled to the first terminal of the current mirror, a second input terminal coupled to the second terminal of the current mirror, and an output terminal. The index generator is configured to compare a first voltage at the first input terminal with a second voltage at the second input terminal to generate a detection result at the output terminal for determining the number of error bits in the memory device.

[0007] Based on the above, the accuracy of error bit detection is improved and high-speed performance without additional timing overhead is achieved by using the error bit detection circuit, the error bit detection method, and the memory device.

[0008] To make the above easier to understand, several embodiments of the accompanying drawings are described in detail below. Simple Explanation of the Diagram

[0009] Figure 1 is a schematic diagram of a memory device according to an embodiment of the present disclosure. Figure 2 is a schematic diagram of a memory device according to an embodiment of the present disclosure. Figure 3 is a timing diagram of a memory device according to an embodiment of the present disclosure. Figure 4 is a schematic diagram of a memory device according to an embodiment of the present disclosure. Figure 5 is a flowchart of an error bit detection method according to an embodiment of the present disclosure. Implementation

[0010] Reference will now be made in detail to exemplary embodiments of the present disclosure, and these embodiments are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar components.

[0011] The specifications and claims disclosed herein use certain terms to refer to specific components. Those skilled in the art will understand that electronic device manufacturers may refer to the same components under different names. This document is not intended to distinguish between components that have the same function but different names. In the following descriptions and claims, words such as "comprising" and "including" are open-ended terms and should be interpreted as "including but not limited to...".

[0012] The term "coupled (or connected)" as used throughout this disclosure (including the claims) may refer to any direct or indirect connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or certain connection methods. The terms "first," "second," and similar terms used throughout this application (including the supplementary claims) are used only to name discrete elements or to distinguish different embodiments or scopes. Therefore, these terms should not be considered as an upper or lower limit on the number of elements, nor should they be used to limit the order in which elements are arranged. Furthermore, where possible, elements / components / steps using the same reference numbers in the illustrations and embodiments represent the same or similar parts. Related descriptions of elements / components / steps using the same reference numbers or the same terms in different embodiments may be referenced to each other.

[0013] It should be noted that in the following embodiments, the technical features of several different embodiments can be replaced, recombined, and mixed without departing from the spirit of this disclosure to complete other embodiments. Features of each embodiment can be used in any combination as long as they do not violate the spirit of this disclosure or conflict with each other.

[0014] With technological advancements, the number of stacked layers in devices is increasing to enhance bit density and enable NAND flash memory to achieve greater storage capacity. It's worth noting that this increased density makes NAND flash memory more susceptible to data retention issues. Valley search is an effective method for addressing data retention problems, involving increasing or decreasing the read voltage at specific intervals until an optimal value is found. However, traditional error bit detection systems applied to valley search suffer from long settling times due to the heavy load of error bits and multiple changes in the criterion code, further increasing the time required to find the final criterion code. Furthermore, traditional error bit detection systems can only detect the maximum number of failure bits across multiple segments of memory cells, rather than the actual number of failure bits in each segment of the memory device.

[0015] In this disclosure, a first voltage caused by the sensing current due to error bits is compared with a reference voltage (for example, a second voltage) to determine the actual number of error bits in each segment of the memory cell in the memory device, rather than the maximum number of error bits in multiple segments of the memory device. Furthermore, while the error bit detection circuit of the current segment is changing the reference code of the reference voltage, the error bit detection circuit of the next segment to be detected is pre-charged, thereby achieving parallel operation. Therefore, the accuracy of error bit detection is improved, and high-speed performance without additional timing overhead is achieved. This enables 3D NAND flash memory with high capacity and high performance.

[0016] Figure 1 is a schematic diagram of a memory device according to an embodiment of the present disclosure. The memory device 10 includes an error bit detection circuit 100, control logic 140, and a page buffer PB. The error bit detection circuit 100 includes a current mirror 110, an index generator 120, and a comparator 130. In one embodiment, the control logic 140 may be part of the error bit detection circuit 100. In another embodiment, the control logic 140 may be an external component of the error bit detection circuit 100. However, the present disclosure is not limited thereto.

[0017] In one embodiment, the current mirror 110 includes a first terminal E1 coupled to the page buffer PB and a second terminal E2 coupled to the index generator 120. Furthermore, the current mirror 110 is configured to receive a power supply voltage VDD. Moreover, during read mode of the memory device, the current mirror 110 is configured to mirror the sensed current ISEN at its first terminal E1 to generate an index current ICR at its second terminal E2. The read mode is performed based on a valley search algorithm.

[0018] In one embodiment, index generator 120 is configured to provide an index load between the second terminal E2 of current mirror 110 and the reference ground terminal VSS according to the index code (CCODE). That is, by changing the index code CCODE, the index load of index generator 120 is changed, thereby adjusting the index voltage (i.e., the second voltage VN) provided by index generator 120.

[0019] In one embodiment, comparator 130 includes a first input terminal coupled to a first terminal E1 of current mirror 110, a second input terminal coupled to a second terminal E2 of current mirror 110, and an output terminal. For example, the first input terminal of comparator 130 can be a positive input terminal, and the second input terminal of comparator 130 can be a negative input terminal. Furthermore, comparator 130 is configured to compare a first voltage VP at the first input terminal with a second voltage VN (also called an index voltage) at the second input terminal to generate a detection result DET at the output terminal, and the detection result DET is used to determine the number of error bits FBN of memory device 10. It is worth noting that the first voltage VP is determined by multiplying the sensed current ISEN by the page buffer load of the page buffer PB, and the page buffer load is determined based on the number of error bits of memory device 10. Furthermore, the second voltage VN is determined by multiplying the index current ICR by the index load of index generator 120.

[0020] Specifically, the page buffer PB is coupled to a memory cell of a segment of memory device 10. Furthermore, the page buffer PB is coupled between the first terminal E1 of the current mirror 110 and the reference ground terminal VSS. The page buffer PB can receive error bit information DB1~DBK. The error bit information DB1~DBK can represent the number of error bits FBN (also called the failure bit count) in the memory segment. The page buffer PB can provide a page buffer load based on the error bit information DB1~DBK. In other words, the page buffer PB can be configured to receive error bit information DB1~DBK and provide a page buffer load between the first terminal E1 of the current mirror 110 and the reference ground terminal VSS based on the error bit information DB1~DBK. Therefore, the page buffer PB can adjust the magnitude of the first voltage VP at the first terminal E1 of the current mirror 110 according to the number of error bits FBN represented by the error bit information DB1~DBK. Accordingly, comparator 130 can generate a detection result DET of the number of error bits FBN based on the comparison result of the first voltage VP and the second voltage VN.

[0021] Furthermore, the second voltage VN can be generated based on the indicator code CCODE. More specifically, the indicator load of indicator generator 120 is determined based on the indicator code CCODE. Further, the second voltage VN is obtained by multiplying the indicator current ICR by the indicator load of indicator generator 120. The indicator code CCODE can be a multi-bit digital code and can be provided by control logic 140. The indicator code CCODE can be determined based on the number of target error bits that control logic 140 needs to detect.

[0022] For example, when the target error bit count is 5, the four bits of the indicator code CCODE can be set to 0, 1, 0, and 1 respectively. Furthermore, when the error bit information DB1~DBK indicates that the actual error bit count FBN is greater than 5, the comparator 130 can generate a detection result DET equal to the logic value 0. On the other hand, when the error bit information DB1~DBK indicates that the actual error bit count FBN is not greater than 5, the comparator 130 can generate a detection result DET equal to the logic value 1. That is, in response to the first voltage VP being less than the second voltage VN, the detection result DET is configured to indicate that the error bit count FBN is greater than the indicator code CCODE. On the other hand, in response to the first voltage VP not being less than the second voltage VN, the detection result DET is configured to indicate that the error bit count FBN is not greater than the indicator code CCODE. However, this disclosure is not limited to this.

[0023] In other words, by adjusting the second voltage VN by changing the indicator code CCODE, the detection result DET can indicate whether the indicator code CCODE is close to or far from the actual number of error bits FBN. For example, for the initial detection of the number of error bits FBN, the indicator code CCODE can be set to the middle number of the maximum allowable error bits to detect the approximate order of the actual number of error bits FBN. Then, when the current detection result DET indicates that the number of error bits FBN is greater than the current indicator code CCODE, the next indicator code CCODE can be increased to make the indicator code CCODE closer to the actual number of error bits FBN. On the other hand, when the current detection result DET indicates that the number of error bits FBN is not greater than the current indicator code CCODE, the next indicator code CCODE can be decreased to make the indicator code CCODE closer to the actual number of error bits FBN. Therefore, the actual number of error bits FBN can be obtained through continuous approximation.

[0024] For example, control logic 140 may be coupled between the output of comparator 130 and the control terminal of index generator 120. Furthermore, control logic 140 may be configured to determine an index code CCODE and provide the index code CCODE to index generator 120. Further, control logic 140 may be configured to increment the index code CCODE in response to a first voltage VP being less than a second voltage VN. Conversely, control logic 140 may be configured to decrement the index code CCODE in response to a first voltage VP not being less than the second voltage VN. Additionally, the number of error bits FBN is determined in response to the index code CCODE being provided to index generator 120 a predetermined number of times (e.g., N times). However, this disclosure is not limited to this.

[0025] In this way, what is obtained is the actual number of error bits (FBN) in each segment of the memory cell in the memory device 10, rather than the maximum number of error bits in multiple segments of the memory cell in the memory device 10. Therefore, the accuracy of error bit detection is improved.

[0026] Figure 2 is a schematic diagram of a memory device according to an embodiment of the present disclosure. Referring to Figures 1 and 2, the memory device 20 in Figure 2 is an exemplary embodiment of the memory device 10 in Figure 1. For the sake of brevity, similar configurations and connections can be referred to the description in Figure 1, and details will not be repeated here.

[0027] Referring now to Figure 2, the memory device 20 includes memory cells of multiple segments 22 and control logic 240. For example, the memory device 20 may include M memory cells of segments 22 as shown in Figure 2, but this disclosure is not limited thereto. Each segment 22 may include an error bit detection circuit 200 and a page buffer PB. The error bit detection circuit 200 includes a current mirror 210, an index generator 220, a comparator 230, a precharge circuit MP, and a clamp transistor MC. In addition, the control logic 240 is coupled to the error bit detection circuit 200 of each segment 22 of the memory device 20 to detect the number of error bits FBN of each segment 22 of the memory device 20.

[0028] In one embodiment, the current mirror 210 includes a first transistor M1, a second transistor M2, a first switch LPEN, and a second switch LPENB. The first transistor M1 includes a first terminal configured to receive a power supply voltage VDD, a second terminal coupled to a first terminal E1 of the current mirror 210, and a control terminal. The second terminal of the first transistor M1 is the first terminal E1 of the current mirror 210. The second transistor M2 includes a first terminal configured to receive a power supply voltage VDD, a second terminal coupled to a second terminal E2 of the current mirror 210, and a control terminal. The second terminal of the second transistor M2 is the second terminal E2 of the current mirror 210. The control terminal of the first transistor M1 is coupled to the control terminal of the second transistor M2. The first switch LPEN is coupled between the second terminal of the first transistor M1 and the control terminal of the first transistor M1. The second switch LPENB is coupled between the second terminal of the second transistor M2 and the control terminal of the second transistor M2.

[0029] It should be noted that, as shown in FIG2, during the read mode of the memory device 20, the first switch LPEN is configured to be on, and the second switch LPENB is configured to be off. On the other hand, as shown in FIG4, during the write mode of the memory device 20, the first switch LPEN is configured to be off, and the second switch LPENB is configured to be on. That is, during the read mode of the memory device 20, the current mirror 210 is configured to mirror the sensing current ISEN at the first terminal E1 of the current mirror 210 to generate an index current ICR at the second terminal E2 of the current mirror 210, thereby detecting the number of faulty bits FBN in the memory cell segment 22. On the other hand, during the write mode of the memory device 20, the current mirror 210 is configured to mirror the index current ICR at the second terminal E2 of the current mirror 210 to generate a sensing current ISEN at the first terminal E1 of the current mirror 210, thereby writing to the memory cell segment 22. In this way, the error bit detection circuit 200 can provide different functions during different modes of the memory device 20, thereby reducing the need for area overhead and achieving power saving.

[0030] In one embodiment, the index generator 220 includes at least one first transistor M3 and a second transistor Mb1. The first transistor M3 includes a first terminal coupled to a second terminal E2 of the current mirror 210 and a control terminal configured to receive an index code CCODE. The second transistor Mb1 is coupled between a second terminal of the first transistor M3 and a reference ground terminal VSS via its first and second terminals, and is controlled by a bias voltage Vbias via the control terminal of the second transistor Mb1. It is worth noting that the number of first transistors M3 may be the same as the number of bits in the index code CCODE, and may be one or more. However, this disclosure is not limited thereto.

[0031] In one embodiment, comparator 230 may be implemented using an operational amplifier. Its hardware architecture is well known to those skilled in the art and therefore will not be described in detail here. Comparator 230 includes a first input terminal coupled to a second terminal of a second transistor M2 coupled to a current mirror 210, a second input terminal coupled to a first terminal of a first transistor M1 coupled to an index generator 220, and an output terminal.

[0032] In one embodiment, the page buffer PB includes multiple pull-down transistors MPB1~MPBK and multiple bias transistors Mb21~Mb2K. The pull-down transistors MPB1~MPBK are connected in series with the bias transistors Mb21~Mb2K, forming multiple transistor strings. The transistor strings are coupled to the error bit detection circuit 200 through a wiring resistor R2. Furthermore, the transistor strings are connected in parallel between the wiring resistor R2 and the reference ground terminal VSS through a wiring resistor R1. The control terminals of the pull-down transistors MPB1~MPBK are configured to receive error bit information DB1~DBK respectively, and the control terminals of the bias transistors Mb21~Mb2K are configured to collectively receive the bias voltage Vbias.

[0033] In this embodiment, taking pull-down transistor MPB1 as an example, when the error bit information DB1 corresponding to pull-down transistor MPB1 is represented as an error bit, pull-down transistor MPB1 can be turned on according to the error bit information DB1 and can provide pull-down current IS1 to reduce the page buffer load provided by page buffer PB. In other words, when the number of error bits FBN represented by error bit information DB1~DBK exceeds a certain number, the page buffer load provided by page buffer PB can be reduced to a certain value. In this way, comparator 230 can compare the first voltage VP to the second voltage VN and can generate a detection result DET with a logic value of 0.

[0034] Furthermore, in one embodiment, by configuring a clamping transistor MC between the page buffer PB and the first terminal E1 of the current mirror 210, an isolation effect can be achieved between the page buffer PB, which has a relatively large load, and the current mirror 210. For example, the clamping transistor MC is coupled between the page buffer PB and the first terminal E1 of the current mirror 210. Further, the control terminal of the clamping transistor MC can be configured to receive a bias voltage Vclamp, and the bias voltage Vclamp can be less than the supply voltage VDD.

[0035] Furthermore, in one embodiment, the precharge circuit MP includes a first terminal configured to receive a power supply voltage, a second terminal coupled to a first terminal E1 of the current mirror 210, and a control terminal configured to receive a precharge signal PRE. Based on the power supply voltage VDD, the precharge circuit MP is configured to precharge the first terminal E1 of the current mirror 210 during the precharge cycle according to the precharge signal PRE. The precharge cycle may occur within the initial time interval of the error bit detection operation of the error bit detection circuit 200, and the first voltage VP may be quickly pulled up to be equal to the power supply voltage VDD. For example, when the precharge signal PRE is a logic value 0, the precharge circuit MP may be turned on, and the voltage of the first terminal E1 of the current mirror 210 may be pulled up to the power supply voltage VDD.

[0036] It is worth noting that the control logic 240 is coupled to an error bit detection circuit 200 for each segment 22 of the memory cell of the memory device 20 to detect the number of error bits (FBN) in each segment 22 of the memory cell of the memory device 20. For example, the error bit detection circuit 200 may include a first error bit detection circuit (for example, error bit detection circuit 200) and a second error bit detection circuit (for example, additional error bit detection circuit 200). The first bit detection circuit may be coupled to a first page buffer of a first segment of the memory device 20, and the second bit detection circuit may be coupled to a second page buffer of a second segment of the memory device 20.

[0037] Furthermore, during the pre-charge cycle of the second error bit detection circuit, control logic 240 can be configured to pre-charge the first terminal E1 of the current mirror 210 of the second error bit detection circuit. Simultaneously, during the pre-charge cycle of the second error bit detection circuit, control logic 240 can be configured to change the index code CCODE of the first error bit detection circuit. That is, in response to the pre-charging of the first terminal E1 of the current mirror 210 of the second error bit detection circuit, control logic 240 can be configured to change the index code CCODE of the first error bit detection circuit and provide the index code CCODE to the index generator 220 of the first error bit detection circuit.

[0038] In other words, the error bit detection circuit 200 of the next segment 22 to be detected is pre-charged while the error bit detection circuit 200 of the current segment 22 is changing the index code CCODE, thereby achieving parallel operation. In this way, the accuracy of error bit detection is improved, and high-speed performance without additional timing overhead is achieved.

[0039] Figure 3 is a schematic timing diagram of a memory device according to an embodiment of the present disclosure. Referring to Figures 2 and 3, timing diagram 30 illustrates the sequence in which error bit detection operations of multiple segments 22 are performed by control logic 240 during the read mode of the memory device 20. In this embodiment, the memory device 20 includes eight segments 22 (e.g., segments 1 to 8). However, the present disclosure is not limited thereto.

[0040] In one embodiment, at time t1s, control logic 240 is configured to precharge the error bit detection circuit 200 of segment 1 and sense a first voltage caused by the sensed current ISEN of segment 1. At time t2s, control logic 240 is configured to change the index code CCODE of segment 1 N times to determine the actual number of error bits FBN of segment 1. At time t1e, after changing the index code N times, control logic 240 is configured to generate the number of error bits FBN. Simultaneously, at time t2s, control logic 240 is configured to precharge the error bit detection circuit 200 of segment 2 and sense a first voltage caused by the sensed current ISEN of segment 2. That is, during the precharge mode of segment 2, the index code CCODE of segment 1 is continuously changed to determine the number of error bits FBN of segment 1, thereby achieving parallel operation.

[0041] Similarly, as shown in Figure 3, from time t3s to time t8e, the pre-charging of segments 3-8 is performed when the indicator codes CCODE of segments 2-7 change respectively. For the sake of brevity, similar details of these operations can be found in the descriptions of segments 1 and 2, and will not be repeated here.

[0042] Figure 4 is a schematic diagram of a memory device according to an embodiment of the present disclosure. Referring to Figures 2 and 4, the memory device 40 in Figure 4 is similar to the memory device 20 in Figure 2. The difference is that the memory device 20 is in read mode, while the memory device 40 is in write mode.

[0043] Specifically, instead of turning on the first switch LPEN and turning off the second switch LPENB, the first switch LPEN is turned off and the second switch LPENB is turned on. That is, the current mirror 110 is not configured to mirror the sensing current ISEN to generate an index current ICR to detect the number of erroneous bits FBN in the memory cell segment 22, but rather to mirror the index current ICR to generate a sensing current ISEN to detect the number of erroneous bits FBN read after the memory cell segment 22 has been written, thereby determining whether the data has been correctly written to the memory cell segment 22.

[0044] In this way, the error bit detection circuit 200 can provide different functions during different modes of the memory device 40, thereby reducing the need for area overhead and achieving power saving.

[0045] Figure 5 is a schematic flowchart of an error bit detection method according to an embodiment of the present disclosure. Referring to Figures 1 and 5, the error bit detection method 50 includes steps S510 to S530.

[0046] In step S510, during the read mode of memory device 10, the sensed current ISEN at the first terminal E1 of current mirror 110 is mirrored to generate an index current ICR at the second terminal E2 of current mirror 110. Furthermore, the first terminal E1 of current mirror 110 is coupled to the page buffer PB of memory device 10, while the second terminal E2 of current mirror 110 is coupled to index generator 120. In step S520, an index load is provided between the second terminal E2 of current mirror 110 and the reference ground terminal VSS according to the index code CCODE. In step S530, the first voltage VP at the first input terminal of comparator 130 is compared with the second voltage VN at the second input terminal of comparator 130 (and after changing the index code CCODE N times) to generate a detection result for determining the number of error bits FBN in memory device.

[0047] Furthermore, the implementation details of the error bit detection method 50 can be found in the descriptions of Figures 1 to 4 for sufficient teaching, advice and implementation examples, without repeating the details here.

[0048] In summary, based on the error bit detection circuit, error bit detection method, and memory device, the actual number of error bits in each memory cell segment of the memory device is obtained. Furthermore, while the error bit detection circuit of the current segment is changing the index code of the index voltage, the error bit detection circuit of the next segment to be detected is pre-charged, thereby achieving parallel operation. Therefore, the accuracy of error bit detection is improved, and high-speed performance without additional timing overhead is achieved.

[0049] Those skilled in the art will readily recognize that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of this disclosure. In view of the foregoing, this disclosure is intended to cover modifications and variations falling within the scope of the following claims and their equivalents.

[0050] 10, 20, 40: Memory devices 22: Section 30: Time Series Diagram 50: Error Bit Detection Method 100, 200: Error bit detection circuit 110, 210: Current mirror 120, 220: Indicator Generator 130, 230: Comparators 140, 240: Control Logic CCODE: Indicator Code DB1~DBK: Error bit information E1: First end E2: Second end FBN: Number of error bits ICR: Indicator Current IS1: Pull-down current ISEN: Sensing Current LPEN: First switch LPENB: Second Switch M1, M3: First transistor M2, Mb1: Second transistor MC: Clamping Transistor MP: Precharge circuit MPB1~MPBK: Pull-down transistors Mb21~Mb2K: Bias transistors PB: Buffer PRE: Precharge signal R1, R2: Wiring resistors DET: Detection Results S510, S520, S530: Steps VDD: Power supply voltage VN: Second voltage VP: First voltage VSS: Reference ground terminal t1e~t8e, t1s~t9s: Time

Claims

1. An error bit detection circuit, comprising: A current mirror, including a first end coupled to a page buffer of a memory device and a second end coupled to an index generator, is configured to: mirror a sensed current at the first end of the current mirror during a read mode of the memory device to generate an index current at the second end of the current mirror; the index generator is configured to: provide an index load between the second end of the current mirror and a reference ground according to an index code; and a comparator, including a first input coupled to the first end of the current mirror, a second input coupled to the second end of the current mirror, and an output, is configured to: compare a first voltage at the first input with a second voltage at the second input to generate a detection result at the output for determining the number of error bits in the memory device, wherein the detection result is configured to indicate that the number of error bits is greater than the index code in response to the first voltage being less than the second voltage; And in response to the first voltage being not less than the second voltage, the detection result is configured to indicate that the number of error bits is not greater than the indicator code.

2. The error bit detection circuit as described in claim 1, wherein the read mode is performed based on a valley search algorithm.

3. The error bit detection circuit as described in claim 1 further includes: The control logic, coupled between the output of the comparator and the control terminal of the indicator generator, is configured to: determine the indicator code and provide the indicator code to the indicator generator; and determine the number of error bits in response to a predetermined number of times the indicator code is provided to the indicator generator.

4. The error bit detection circuit as claimed in claim 3, wherein the control logic is further configured to: increment the indicator code in response to the first voltage being less than the second voltage; and decrement the indicator code in response to the first voltage being not less than the second voltage.

5. The error bit detection circuit as claimed in claim 3, wherein the error bit detection circuit is coupled to a first page buffer of a first segment of the memory device, an additional error bit detection circuit is coupled to a second page buffer of a second segment of the memory device, and the control logic is further configured to: precharge a first terminal of a current mirror of the additional error bit detection circuit; and in response to the precharging of the first terminal of the current mirror of the additional error bit detection circuit, change the index code of the error bit detection circuit and provide the index code to the index generator of the error bit detection circuit.

6. The error bit detection circuit as claimed in claim 1, wherein the first voltage is determined by multiplying the sensed current by the page buffer load of the page buffer, and the page buffer load is determined based on the number of error bits in the memory device.

7. The error bit detection circuit as claimed in claim 1, wherein the second voltage is determined by multiplying the index current by the index load.

8. The error bit detection circuit as claimed in claim 1, wherein the current mirror is further configured to: mirror the index current at the second terminal of the current mirror during a write mode of the memory device to generate the sensing current at the first terminal of the current mirror.

9. The error bit detection circuit as claimed in claim 1, wherein the current mirror further comprises: A first transistor includes a first terminal configured to receive a power supply voltage, a second terminal coupled to the first terminal of the current mirror, and a control terminal; a second transistor includes a first terminal configured to receive the power supply voltage, a second terminal coupled to the second terminal of the current mirror, and a control terminal, wherein the control terminal of the first transistor is coupled to the control terminal of the second transistor; a first switch is coupled between the second terminal of the first transistor and the control terminal of the first transistor; And a second switch, coupled between the second terminal of the second transistor and the control terminal of the second transistor.

10. The error bit detection circuit of claim 9, wherein during the read mode of the memory device, the first switch is configured to be turned on and the second switch is configured to be turned off, and during the write mode of the memory device, the first switch is configured to be turned off and the second switch is configured to be turned on.

11. The error bit detection circuit as claimed in claim 1, wherein the index generator comprises: At least one first transistor includes a first terminal coupled to the second terminal of the current mirror and a control terminal configured to receive the index code; And a second transistor, coupled between the second terminal of the at least one first transistor and the reference ground terminal, and controlled by a bias voltage.

12. The error bit detection circuit as described in claim 1, further comprising: A pre-charge circuit, coupled to the first terminal of the current mirror, is configured to pre-charge the first terminal of the current mirror during a pre-charge cycle according to a pre-charge signal.

13. The error bit detection circuit as described in claim 1, further comprising: A clamping transistor is coupled between the page buffer and the first end of the current mirror.

14. The error bit detection circuit of claim 1, wherein the page buffer is configured to: receive error bit information and, based on the error bit information, provide a page buffer load between the first terminal of the current mirror and the reference ground terminal.

15. A method for detecting faulty bits, comprising: During the read mode of the memory device, the sensed current at the first end of the mirror current mirror is used to generate an index current at the second end of the current mirror, wherein the first end of the current mirror is coupled to the page buffer of the memory device and the second end of the current mirror is coupled to an index generator; an index load is provided between the second end of the current mirror and a reference ground terminal according to an index code. And compare a first voltage at a first input terminal of the comparator with a second voltage at a second input terminal of the comparator to generate a detection result for determining the number of error bits in the memory device, wherein in response to the first voltage being less than the second voltage, the detection result is configured to indicate that the number of error bits is greater than the index code; And in response to the first voltage being not less than the second voltage, the detection result is configured to indicate that the number of error bits is not greater than the indicator code.

16. The error bit detection method as described in claim 15, wherein the read mode is performed based on a valley search algorithm.

17. A memory device, comprising: A memory cell comprising multiple segments, wherein each of the multiple segments includes a page buffer; The memory device includes a plurality of error bit detection circuits, each of which is coupled to the page buffer and includes: a current mirror, including a first end coupled to the page buffer of the memory device and a second end coupled to an index generator, and configured to: mirror a sense current at the first end of the current mirror during a read mode of the memory device to generate an index current at the second end of the current mirror; and the index generator, configured to: provide an index load between the second end of the current mirror and a reference ground according to an index code; and a comparator, including a first input coupled to the first end of the current mirror, a second input coupled to the second end of the current mirror, and an output, and configured to: compare a first voltage at the first input with a second voltage at the second input to generate a detection result at the output for determining the number of error bits in the memory device, wherein the detection result is configured to indicate that the number of error bits is greater than the index code in response to the first voltage being less than the second voltage. And in response to the first voltage being not less than the second voltage, the detection result is configured to indicate that the number of error bits is not greater than the indicator code.

18. The memory device of claim 17, wherein the plurality of error bit detection circuits include a first error bit detection circuit and a second error bit detection circuit, and the memory device further includes: Control logic, coupled to the plurality of error bit detection circuits, is configured to: precharge the first terminal of the current mirror of the second error bit detection circuit; and, in response to the precharging of the first terminal of the current mirror of the second error bit detection circuit, change the index code of the first error bit detection circuit and provide the index code to the index generator of the first error bit detection circuit.

Images