Memory device
TW202640639APending Publication Date: 2026-10-01WINBOND ELECTRONICS CORP
View PDF 0 Cites 0 Cited by
Patent Information
- Application Number
- TW115101940
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-02-10
- Filing Date
- 2026-01-19
- Publication Date
- 2026-10-01
Smart Images
Figure 00000000_0000_ABST
Abstract
The memory device is provided. The memory device includes at least one core die and a logic die. The at least one core die provides at least two state signals based on error check and correction (ECC) operation. The logic die is coupled to the least one core die. The logic die generates severity (SEV) signals based on the state signals. A number of the state signals is lower than a number of the SEV signals.
Need to check novelty before this filing date? Find Prior Art