Electronic device

Abstract

An electronic device includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first end, a second end, and a control end, and its second end is electrically connected to a ground end, and its control end receives a control signal. The second transistor includes a first end, a second end, and a control end, and its first end receives a driving voltage, and its second end is electrically connected to the first transistor’s first end. The third transistor includes a first end, a second end, and a control end, and its first end is electrically connected to the first transistor’s control end, its second end is electrically connected to the second transistor’s control end, and its control end is electrically connected to the ground end. The first transistor’s threshold voltage is higher than zero. The second transistor’s threshold voltage and the third transistor’s threshold voltage are lower than zero.

Description

[Technical Field]

[0001] This disclosure relates to electronic devices, and in particular to common-source common-gate amplifiers. [Previous Technology]

[0002] A common cascode amplifier includes a normally off transistor (E-mode) and a normally open transistor (D-mode). The normally open transistor is electrically connected between the drive voltage and the normally off transistor. The normally off transistor is electrically connected between the normally open transistor and ground. The gate of the normally open transistor is electrically connected to ground. The gate of the normally off transistor receives the control signal. However, when the gate voltage of the normally off transistor is 0V, the normally open transistor will repeatedly turn on or off due to the voltage oscillation at the source of the normally off transistor. [Summary of the Invention]

[0003] An electronic device according to an embodiment of the present disclosure includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first terminal, a second terminal, and a control terminal. The second terminal of the first transistor is electrically connected to a ground terminal. The control terminal of the first transistor receives a control signal. The second transistor includes a first terminal, a second terminal, and a control terminal. The first terminal of the second transistor receives a driving voltage. The second terminal of the second transistor is electrically connected to the first terminal of the first transistor. The third transistor includes a first terminal, a second terminal, and a control terminal. The first terminal of the third transistor is electrically connected to the control terminal of the first transistor. The second terminal of the third transistor is electrically connected to the control terminal of the second transistor. The control terminal of the third transistor is electrically connected to a ground terminal. The threshold voltage of the first transistor is greater than zero, and the threshold voltages of the second and third transistors are both less than zero.

[0004] In the electronic device described above, the highest voltage received by the control terminal of the second transistor is equal to the absolute value of the critical voltage of the third transistor.

[0005] In the electronic device described above, the rated voltage of the first transistor is equal to the absolute value of the critical voltage of the second transistor plus the first voltage. The first voltage is between 10V and 15V.

[0006] In the electronic device described above, when the first transistor and the second transistor are turned on simultaneously, the second transistor reduces the on-resistance formed when the first transistor and the second transistor are turned on.

[0007] In the electronic device described above, when the driving voltage is higher than the second voltage, the third transistor suppresses the voltage at the first terminal of the first transistor from oscillating.

[0008] In the electronic device described above, the second voltage is equal to 10V.

[0009] In the electronic device described above, the first transistor, the second transistor, and the third transistor are packaged in a chip using semiconductor packaging technology.

[0010] As described above, the electronic device is a common-source common-gate amplifier.

[0011] An electronic device according to an embodiment of the present disclosure includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first terminal, a second terminal, and a control terminal. The second terminal of the first transistor is electrically connected to a ground terminal. The control terminal of the first transistor receives a control signal. The second transistor includes a first terminal, a second terminal, and a control terminal. The first terminal of the second transistor receives a driving voltage. The second terminal of the second transistor is electrically connected to the first terminal of the first transistor. The third transistor includes a first terminal, a second terminal, and a control terminal. The first terminal of the third transistor is electrically connected to a ground terminal. The second terminal of the third transistor is electrically connected to the control terminal of the second transistor. The control terminal of the third transistor is electrically connected to the control terminal of the first transistor. The threshold voltage of the first transistor is greater than zero, and the threshold voltages of the second and third transistors are both less than zero.

[0012] In the electronic device described above, when the control terminal of the first transistor is 0V and the first transistor is off, the third transistor prevents the second transistor from repeatedly turning on or off due to voltage oscillation at the second terminal of the first transistor.

[0013] In the electronic device described above, the first transistor, the second transistor, and the third transistor are packaged in a chip using semiconductor packaging technology.

[0014] As described above, the electronic device is a common-source common-gate amplifier.

Implementation Method

[0015] Reference will now be made in detail to the exemplary embodiments disclosed herein, examples of which are illustrated in the drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0016] Certain terms are used throughout this specification and the appended claims to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same components. This document is not intended to distinguish between components that function identically but have different names. In the following specification and claims, words such as "cover," "contain," and "comprise" are open-ended terms and should therefore be interpreted as "containing but not limited to...".

[0017] The terms “approximately,” “equal to,” “equivalent to,” “same,” “substantially,” or “probably” are generally interpreted as being within 20% of a given value or range, or as being within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range.

[0018] The ordinal numbers used in the specification and claims, such as "first" and "second," to modify elements do not inherently imply or represent any prior ordinal number for that element (or those elements), nor do they represent the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another element with the same name. The claims and specification may not use the same terminology; therefore, a first component in the specification may be a second component in the claims.

[0019] The electrical connections or couplings described in this disclosure can refer to direct connections or indirect connections. In the case of a direct connection, the endpoints of the components on two circuits are directly connected or connected to each other by a conductor segment. In the case of an indirect connection, there is a switch, diode, capacitor, inductor, resistor, other suitable components, or combinations of the above components between the endpoints of the components on two circuits, but not limited to these.

[0020] In this disclosure, the thickness, length, and width can be measured using an optical microscope, while the thickness or width can be measured from a cross-sectional image in an electron microscope, but are not limited thereto. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. Additionally, the terms "equal to," "equivalent to," "identical," "substantially," or "approximately" used in this disclosure generally mean falling within 10% of a given value or range. Moreover, the phrases "given range is from the first value to the second value" and "given range falls within the range of the first value to the second value" indicate that the given range includes the first value, the second value, and other values ​​in between.

[0021] It should be understood that the features in the following embodiments can be replaced, reorganized, or mixed to complete other embodiments without departing from the spirit of this disclosure. Features between embodiments can be arbitrarily mixed and combined as long as they do not violate the spirit of the disclosure or conflict with it.

[0022] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It is understood that such terms, for example, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0023] Figure 1 is a schematic diagram of an electronic device 100 according to an embodiment of the present disclosure. As shown in Figure 1, the electronic device 100 includes a first transistor Q1, a second transistor Q2, and a third transistor Q3. In some embodiments, the electronic device 100 is a common-source common-gate amplifier used to amplify a control signal RF, and the amplified control signal RF is output by node B. The first transistor Q1 includes a drain D1, a source S1, and a gate G1. The source S1 is electrically connected to a ground terminal GND. The gate G1 receives the control signal RF. The second transistor Q2 includes a drain D2, a source S2, and a gate G2. The drain D2 receives a drive voltage HV. The source S2 is electrically connected to the drain D1 of the first transistor Q1.

[0024] The third transistor Q3 includes a drain D3, a source S3, and a gate G3. The drain D3 is electrically connected to the gate G1 of the first transistor Q1. The source S3 is electrically connected to the gate G2 of the first transistor Q1. The gate G3 is electrically connected to the ground terminal GND. That is, the gate G3 is also electrically connected to the source S1 of the first transistor Q1. The threshold voltage of the first transistor Q1 is greater than 0. The threshold voltages of the second transistor Q2 and the third transistor Q3 are both less than 0. In other words, the first transistor Q1 is a normally off transistor. The second transistor Q2 and the third transistor Q3 are normally on transistors.

[0025] In some embodiments, a normally-off transistor is in the off state when no gate voltage is applied, and a sufficiently positive voltage must be applied to the normally-off transistor to turn it on. This sufficiently positive voltage is called the threshold voltage. Conversely, a normally-on transistor must be applied with a sufficiently negative voltage to turn it off. In some embodiments, the first transistor Q1 is a low-voltage normally-off transistor. The second transistor Q2 and the third transistor Q3 are high-voltage normally-on transistors. In some embodiments, the first transistor Q1, the second transistor Q2, and the third transistor Q3 are all N-type transistors, but this disclosure is not limited to these.

[0026] In some embodiments, the highest voltage (i.e., its withstand voltage) received by the gate G2 of the second transistor Q2 is equal to the absolute value of the critical voltage of the third transistor Q3. In some embodiments, the rated voltage of the first transistor Q1 is equal to the absolute value of the critical voltage of the second transistor Q2 plus a first voltage. The first voltage may be, for example, between 10V and 15V, but this disclosure is not limited thereto.

[0027] In some embodiments, when the first transistor Q1 and the second transistor Q2 are simultaneously turned on, the second transistor Q2 can reduce the on-resistance Ron formed when the first transistor Q1 and the second transistor Q2 are turned on. When the on-resistance Ron is reduced, the drive current flowing from the drive voltage HV through the first transistor Q1 and the second transistor Q2 to the ground terminal GND can be correspondingly increased to increase the power gain of the electronic device 100. For example, compared with the common-source common-gate amplifier in the prior art, the electronic device 100 disclosed herein can reduce the on-resistance Ron from 299mΩ to 283mΩ (a reduction of about 5%), thereby increasing the drive current from 16A to 17A (an increase of about 5%).

[0028] In some embodiments, when the driving voltage HV is higher than the second voltage, the third transistor Q3 can suppress voltage oscillations on the drain D1 of the first transistor Q1. That is, the third transistor Q3 can suppress high-voltage oscillations on node B. The second voltage may be, for example, 10V, but this disclosure is not limited thereto. The driving voltage HV is the voltage across node A and ground GND. In some embodiments, voltage oscillations on node B can cause the second transistor Q2 to turn on or off incorrectly. The voltage on node B is the voltage across node B and ground GND. In some embodiments, the high-voltage oscillations on node B are caused by the coupling between parasitic inductance and parasitic capacitance in the path of the second transistor Q2.

[0029] Figure 2 is a schematic diagram of an electronic device 200 according to an embodiment of the present disclosure. As shown in Figure 2, the electronic device 200 includes a first transistor Q1, a second transistor Q2, and a third transistor Q3. In some embodiments, the electronic device 200 is a common-source common-gate amplifier used to amplify a control signal RF, and the amplified control signal RF is output from the source S2 of the second transistor Q2. The first transistor Q1 includes a drain D1, a source S1, and a gate G1. The source S1 is electrically connected to the ground terminal GND. The gate G1 receives the control signal RF. The second transistor Q2 includes a drain D2, a source S2, and a gate G2. The drain D2 receives a drive voltage HV. The source S2 is electrically connected to the drain D1 of the first transistor Q1.

[0030] The third transistor Q3 includes a drain D3, a source S3, and a gate G3. The drain D3 is electrically connected to the ground terminal GND. That is, the drain D3 is electrically connected to the source S1 of the first transistor Q1. The source S3 is electrically connected to the gate G2 of the second transistor Q2. The gate G3 is electrically connected to the gate G1 of the first transistor Q1. In other words, the gate G3 of the third transistor Q3 is the same as the gate G1 of the first transistor Q1, and it also receives the control signal RF and controls the turning on or off of the third transistor Q3 and the first transistor Q1 respectively according to the control signal RF. The threshold voltage of the first transistor Q1 is greater than 0. The threshold voltages of the second transistor Q2 and the third transistor Q3 are both less than 0.

[0031] In some embodiments, the first transistor Q1 is a normally off transistor. The second transistor Q2 and the third transistor Q3 are normally on transistors. The second transistor Q2 and the third transistor Q3 are high-voltage normally on transistors. In some embodiments, the first transistor Q1, the second transistor Q2, and the third transistor Q3 are all N-type transistors, but this disclosure is not limited thereto.

[0032] In some embodiments, when the first transistor Q1 and the second transistor Q2 are simultaneously turned on, the second transistor Q2 can reduce the on-resistance Ron formed when the first transistor Q1 and the second transistor Q2 are turned on. When the on-resistance Ron is reduced, the drive current flowing from the drive voltage HV through the first transistor Q1 and the second transistor Q2 to the ground terminal GND can be increased accordingly, thereby increasing the power gain of the electronic device 200.

[0033] In some embodiments, when the control terminal of the first transistor is 0V and the first transistor Q1 is off, the third transistor Q3 prevents the second transistor Q2 from repeatedly turning on or off due to the voltage oscillation of the source S1 of the first transistor Q1.

[0034] Figure 3 is a schematic diagram of the layout, packaging, and wire bonding of the electronic device 300 according to an embodiment of the present disclosure. As shown in Figure 3, the electronic device 300 includes a gate drive circuit 310, solder pads 302, 304, 306, and a chip 308. In some embodiments, the first transistor Q1, the second transistor Q2, and the third transistor Q3 in the electronic device 100 of Figure 1 are packaged in the chip 308 using semiconductor packaging technology. In the embodiment of Figure 3, the chip 308 includes eight pins, but the present disclosure is not limited thereto. The gate drive circuit 310 is electrically connected to the solder pads 302. The solder pads 302 are electrically connected to the gate G1 of the first transistor Q1 and the drain D3 of the third transistor Q3. The gate G1 of the first transistor Q1 is electrically connected to the solder pads 302 through a single pin and wire bonding. The drain D3 of the third transistor Q3 is electrically connected to the solder pads 302 through a single pin and wire bonding. Pad 302 is used to receive control signals RF.

[0035] Pad 304 is electrically connected to the ground terminal GND. Pad 304 is electrically connected to the source S1 of the first transistor Q1 via two pins and wire bonding. Pad 306 receives the drive voltage HV. Pad 306 is electrically connected to the drain D2 of the second transistor via four pins. The drain D1 of the first transistor Q1 is electrically connected to the source S2 of the second transistor Q2 via wire bonding. The source S1 of the first transistor Q1 is electrically connected to the gate G3 of the third transistor Q3 via wire bonding. The source S3 of the third transistor Q3 is electrically connected to the gate S2 of the second transistor Q2 via wire bonding. The gate drive circuit 310 is used to output a control signal RF to the chip 308.

[0036] In some embodiments, when the user does not use the third transistor Q3, the user can disconnect the diagonal portion of the pad 302 from the body of the pad 302, or change the shape of the pad 302 so that the pad 302 is not connected to the drain D3 of the third transistor Q3. In this way, the chip 308 can also be used in the existing common-source common-gate amplifier architecture.

[0037] Figure 4 is a schematic diagram of the layout, packaging, and wire bonding of the electronic device 400 according to an embodiment of the present disclosure. As shown in Figure 4, the electronic device 400 includes a gate drive circuit 410, solder pads 402, 404, 406, and a chip 408. In some embodiments, the first transistor Q1, the second transistor Q2, and the third transistor Q3 in the electronic device 200 of Figure 2 are packaged in the chip 408 using semiconductor packaging technology. In the embodiment of Figure 4, the chip 408 includes eight pins, but the present disclosure is not limited thereto. The gate drive circuit 410 is electrically connected to the solder pads 402. The solder pads 402 are electrically connected to the gate G1 of the first transistor Q1 and the gate G3 of the third transistor Q3 through a single pin and wire bonding. The solder pads 402 receive control signals RF.

[0038] Pad 404 is electrically connected to the ground terminal GND. Pad 404 is electrically connected to the drain D3 of the third transistor Q3 via a single pin and wire bonding. Pad 404 is electrically connected to the source S1 of the first transistor Q1 via two pins and wire bonding. Pad 406 receives the drive voltage HV. Pad 406 is electrically connected to the drain D2 of the second transistor Q2 via four pins and wire bonding. The gate G2 of the second transistor Q2 is electrically connected to the source S3 of the third transistor Q3 via wire bonding. The gate drive circuit 410 is used to output a control signal RF to the chip 408.

[0039] In some embodiments, when the user does not use the third transistor Q3, the user can disconnect the diagonal portion of the pad 404 from the body of the pad 404, or change the shape of the pad 404 so that the pad 404 is not connected to the drain D3 of the third transistor Q3. In this way, the chip 408 can also be used in the existing common-source common-gate amplifier architecture.

[0040] The electronic devices 100 and 200 of this disclosure maintain the high voltage withstand characteristics of the second transistor Q2. By using a common gate structure to increase the voltage and turn on the second transistor Q2, the on-resistance of the second transistor Q2 can be further reduced and the on-current increased. The electronic devices 100 and 200 of this disclosure prevent high voltage interference from the second transistor Q2 through the connection of the third transistor Q3.

[0041] Although the implementations of this disclosure are as described above, it should be understood that what is presented above is merely exemplary and not a limitation. Many modifications to the above exemplary embodiments can be made without departing from the spirit and scope of the disclosure. Therefore, the breadth and scope of this disclosure should not be limited by the embodiments described above. Rather, the scope of this disclosure should be defined by the following claims and their equivalents. Although the above disclosure has been illustrated and depicted by one or more related implementations, equivalent changes and modifications will be conceived by others skilled in the art based on the above specifications and drawings. Furthermore, although a particular feature of this disclosure has been demonstrated by one of the related implementations, such feature may be combined with one or more other features to meet the needs and facilitate any known or particular application.

[0042] The technical terms used in this specification are for the purpose of describing particular embodiments only and are not intended to be limiting of this disclosure. Unless the context clearly indicates otherwise, the singular form used herein, as well as the plural form, also includes the meaning of the above. Furthermore, the terms "comprising," "including," "(having)," "equipped with," or variations thereof are used either as part of a detailed description or as part of the scope of the claims. The above terms mean "comprising" and are to some extent equivalent to the term "comprising." Unless otherwise defined, all terms used herein (including technical or scientific terms) are to be understood by one of ordinary skill in the art disclosed above. We should further understand that the above terms, as defined in commonly used dictionaries, should be interpreted as having the same meaning in the context of the relevant art. Unless expressly defined herein, the above terms are not to be interpreted as having an idealized or overly formal meaning. [Simplified Explanation of the Diagram]

[0043] Figure 1 is a schematic diagram of the electronic device 100 according to an embodiment of the present disclosure. Figure 2 is a schematic diagram of the electronic device 200 according to an embodiment of the present disclosure. Figure 3 is a schematic diagram of the layout, packaging, and wire bonding of the electronic device 300 according to an embodiment of the present disclosure. Figure 4 is a schematic diagram of the layout, packaging, and wire bonding of the electronic device 400 according to an embodiment of the present disclosure.

Claims

1. An electronic device comprising: A first transistor includes a first terminal, a second terminal, and a control terminal; wherein its second terminal is electrically connected to a ground terminal, and its control terminal receives a control signal; a second transistor includes a first terminal, a second terminal, and a control terminal; wherein its first terminal receives a driving voltage, and its second terminal is electrically connected to the first terminal of the first transistor; and a third transistor includes a first terminal, a second terminal, and a control terminal; wherein its first terminal is electrically connected to the control terminal of the first transistor, its second terminal is electrically connected to the control terminal of the second transistor, and its control terminal is electrically connected to the ground terminal; wherein the threshold voltage of the first transistor is greater than zero, and the threshold voltages of the second transistor and the third transistor are both less than zero.

2. The electronic device as described in claim 1, wherein, The highest voltage received at the control terminal of the second transistor is equal to the absolute value of the critical voltage of the third transistor.

3. The electronic device as described in claim 1, wherein, The rated voltage of the first transistor is equal to the absolute value of the critical voltage of the second transistor plus a first voltage; the first voltage is between 10V and 15V.

4. The electronic device as described in claim 1, wherein, When the first transistor and the second transistor are both turned on, the second transistor reduces the on-resistance formed when the first transistor and the second transistor are turned on.

5. The electronic device as described in claim 1, wherein, When the driving voltage is higher than a second voltage, the third transistor suppresses the voltage oscillation at the first terminal of the first transistor.

6. The electronic device as described in claim 5, wherein, The second voltage is equal to 10V.

7. The electronic device as claimed in claim 1, wherein, The first transistor, the second transistor, and the third transistor are packaged in a single chip using semiconductor packaging technology.

8. The electronic device as claimed in claim 1, wherein, The electronic device is a common-source, common-gate amplifier.

9. An electronic device comprising: A first transistor includes a first terminal, a second terminal, and a control terminal; wherein its second terminal is electrically connected to a ground terminal, and its control terminal receives a control signal; a second transistor includes a first terminal, a second terminal, and a control terminal; wherein its first terminal receives a driving voltage, and its second terminal is electrically connected to the first terminal of the first transistor; and a third transistor includes a first terminal, a second terminal, and a control terminal; wherein its first terminal is electrically connected to the ground terminal, its second terminal is electrically connected to the control terminal of the second transistor, and its control terminal is electrically connected to the control terminal of the first transistor; wherein the threshold voltage of the first transistor is greater than zero, and the threshold voltages of the second transistor and the third transistor are both less than zero.

10. The electronic device as claimed in claim 9, wherein, When the control terminal of the first transistor is 0V and the first transistor is off, the third transistor prevents the second transistor from repeatedly turning on or off due to voltage oscillations at the second terminal of the first transistor.

11. The electronic device as claimed in claim 9, wherein, The first transistor, the second transistor, and the third transistor are packaged in a single chip using semiconductor packaging technology.

12. The electronic device as claimed in claim 9, wherein, The electronic device is a common-source, common-gate amplifier.

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