Signal receiving device

Abstract

A signal receiving device includes an analog front end circuit, a plurality of adders, a plurality of first slicer sets, a plurality of second slicer sets, a clock recovery circuit and a decision feedback equalizer. Each of the adders adds each of fist signal pairs with first coefficients to generate each of a plurality of second signal pairs. Selected slicer sets of the second slicer sets, based on a calibrated coefficient, sample corresponding second signal pair to generate first error information according to a reference voltage pair. Un-selected slicer sets of the second slicer set, based on a second coefficient, samples corresponding second signal pair to generate a second error information according to the reference voltage pair. The clock recovery circuit and the decision feedback equalizer generate a plurality of received data corresponding to the input signal according to the first error information and the second error information, respectively.

Description

Technical Field

[0001] This invention relates to a signal receiving device, and more particularly to a signal receiving device that effectively reduces logic conflicts that occur during the convergence process of clock recovery circuits and feedback equalizers. Prior Technology

[0002] In conventional signal receiving devices, during the convergence process, the clock recovery circuit and the decision feedback equalizer may experience logical conflicts because the convergence loop cannot be separated, which may cause the clock recovery circuit to lock the sampling clock in an unsuitable phase.

[0003] To resolve the aforementioned logical conflict, in the prior art, an offset value can be added to the digital logic circuit to adjust the sampling position of the clock recovery circuit. However, this approach may cause relatively severe jitter when the clock recovery circuit performs a locking action. Summary of the Invention

[0004] This invention provides a signal receiving device that effectively reduces the possibility of logic conflicts occurring in the clock recovery circuit and feedback equalizer during the convergence process.

[0005] The signal receiving apparatus of the present invention includes an analog front-end circuit, a plurality of adders, a plurality of first divider groups, a plurality of second divider groups, a clock recovery circuit, and a decision feedback equalizer. The analog front-end circuit processes the input signal to generate a plurality of first signal pairs. Each adder receives a first signal pair and adds each first signal pair to a plurality of first parameters to generate each of a plurality of second signal pairs. Each first divider group corresponds to an adder and, based on second parameters, samples the second signal pairs according to a reference data pair to generate a plurality of sampled data. Each second divider group corresponds to an adder. A plurality of selected divider groups in a portion of the second divider groups generate a plurality of first error information based on a correction parameter and a reference voltage pair, sampling the corresponding second signal pairs; at least one unselected divider group in the second divider group generates second error information based on the second parameters and a reference voltage pair, sampling the corresponding second signal pairs. The clock recovery circuit and the decision feedback equalizer generate a plurality of received data corresponding to the input signal based on the first error information and the second error information, respectively.

[0006] Based on the above, the present invention generates first error information by having a portion of the second divider group generate corresponding second signal pairs based on a second parameter and a reference voltage pair, and generates multiple second error information by another portion of the second divider group based on a correction parameter and the corresponding second signal pairs. The correction parameter is different from the second parameter. Furthermore, the clock recovery circuit generates multiple received data corresponding to the input signal based on the second error information, and the decision feedback equalizer generates corresponding first error information. Thus, by providing different error information to the clock recovery circuit and the decision feedback equalizer respectively, the clock recovery circuit and the decision feedback equalizer can have different convergence messages without causing logical conflicts between them. Simple Explanation of the Diagram

[0007] Figure 1 illustrates a schematic diagram of a signal receiving device according to an embodiment of the present invention. Figure 2 illustrates a schematic diagram of an embodiment of the divider in the signal receiving device of the present invention. Figure 3 shows a schematic diagram of the three-stage voltage division waveform of the divider in the embodiment of Figure 2. Figure 4 illustrates a schematic diagram of an embodiment of the divider in the signal receiving device of the present invention. Figure 5 shows a schematic diagram of the three-stage voltage division waveform of the divider in the embodiment of Figure 4. Implementation

[0008] Please refer to Figure 1, which illustrates a schematic diagram of a signal receiving device according to an embodiment of the present invention. The signal receiving device 100 includes an analog front-end circuit 110, adders 121-124, divider groups SC11-SC14, SC21-SC24, a clock recovery circuit 130, and a decision feedback equalizer 140. The analog front-end circuit 110 receives the input signal SIN and processes it to generate multiple signal pairs S11-S14. In this embodiment, the signal pairs S11-S14 may each have different phases; specifically, the signal pairs S11-S14 may be four-phase signal pairs. Furthermore, each signal pair S11-S14 may be a differential signal pair, that is, each signal pair S11-S14 may have a first signal and a second signal that are differential signals to each other.

[0009] In this embodiment, the analog front-end circuit 110 can perform continuous-time linear equalization (CTLE) on the received input signal SIN and perform variable gain amplification (VGA) to generate signal pairs S11 to S14.

[0010] Furthermore, adders 121-124 receive signal pairs S11-S14 respectively. Adders 121-124 are used to add signal pairs S11-S14 with parameters H2-H8 respectively, thereby generating signal pairs S21-S24 respectively. Similarly, each signal pair S21-S24 can also be a differential signal pair.

[0011] In this embodiment, divider groups SC11-SC14 correspond to adders 121-124, respectively. Divider groups SC11-SC14 can generate multiple sampled data SD1-SD4 based on parameter H1 and by sampling the corresponding signal pairs S21-S24 from the reference data pair DR. On the other hand, divider groups SC21-SC24 also correspond to adders 121-124, and can be distinguished as selected divider groups and unselected divider groups. In this embodiment, divider group SC24 is an unselected divider group, while divider groups SC21-SC23 are selected divider groups. Divider groups SC21-SC23 jointly receive correction parameter AXH1 and reference voltage pair VR, and each receives signal pairs S21-S23. Divider groups SC21-SC23, based on correction parameter AXH1 and by sampling the corresponding signal pairs S21-S23 from the reference voltage pair VR, generate error information Er1-Er3. The divider group SC24 receives parameter H1 and reference voltage pair VR, and also receives signal pair S24. Based on parameter H1, the divider group SC24 samples the corresponding signal pair S24 according to the reference voltage pair VR to generate error information Er4.

[0012] In this embodiment, the correction parameter AXH1 can be equal to the parameter H1 multiplied by the coefficient A, where A is a real number not equal to 1.

[0013] It is worth noting that in this embodiment, error information Er4 is used as the convergence information of the decision feedback equalizer 130, while error information Er1~Er3 is used as the convergence information of the clock recovery circuit 140. Specifically, in this embodiment, the signal receiving device 100 uses the error information Er1~Er3 output by three of the four splitters SC21~SC23 as the convergence information of the clock recovery circuit 130, and uses the error information Er4 output by one of the four splitters SC21~SC24 as the convergence information of the decision feedback equalizer 140. In this way, the convergence information of the clock recovery circuit 130 and the decision feedback equalizer 140 are different, and no conflict will occur. In addition, in this embodiment, the phase locked by the clock recovery circuit 130 can be adjusted by changing the value of parameter A. Parameter A can be greater than 1 or less than 1, but not equal to 1.

[0014] In this embodiment, the clock recovery circuit 130 can be a Baud rate clock and data recovery circuit.

[0015] It is worth noting that in other embodiments of the present invention, the selected splitter can be any three of the four-way splitters SC21 to SC24, and is not limited to splitters SC21 to SC23. Furthermore, the number of unselected splitters is not limited to one; in some embodiments of the present invention, the unselected splitter can also be any two of the four-way splitters SC21 to SC24, without any particular limitation.

[0016] Incidentally, the circuit architectures of the adders 121-124, the clock recovery circuit 130, and the decision feedback equalizer 140 of the present invention can all be implemented using circuit architectures well known to those skilled in the art, without any fixed limitations.

[0017] Furthermore, the parameters H1~H4 in this embodiment of the invention can be provided by the clock recovery circuit and the decision feedback equalizer 140. The clock recovery circuit 130 and the decision feedback equalizer 140 jointly generate the output signal DOUT.

[0018] Please refer to Figure 2, which illustrates a schematic diagram of an implementation of a divider group in a signal receiving device according to an embodiment of the present invention. Divider 200 is a single-feedback divider. Divider group 200 can be applied to any of the divider groups SC11-SC24 in the embodiment of Figure 1. Divider group 200 includes a first part circuit 210 and a second part circuit 220. The first part circuit 210 is used to provide a first bias voltage PP and a second bias voltage PN based on parameter H1 and a correction parameter. The correction parameter is equal to the product of parameter H1 and coefficient A, which can be provided through parameter TAP1P. The second part circuit 220 is coupled to the first part circuit 210 and, based on the first bias voltage PP and the second bias voltage PN, compares the corresponding signal pair S2X with the reference data pair DR or the reference voltage pair VR to generate corresponding sampled data SDP, SDN, or sub-error data ErP, ErN.

[0019] In this embodiment, the first part of the circuit 210 includes transistors M21 to M27, wherein transistors M22 and M23 form a first transistor pair; transistors M24 and M25 form a second transistor pair; and transistors M26 and M27 form a third transistor pair. The first terminal of transistor M21 receives the power supply voltage VPP; the second terminal of transistor M21 is coupled to the first transistor pair; and the control terminal of transistor M21 receives the clock signal CK. In the first transistor pair, the first terminals of transistors M22 and M23 are coupled to the second terminal of transistor M21, and transistors M22 and M23 are respectively controlled by sub-parameters H1HP and H1LN in parameter H1, wherein sub-parameters H1HP and H1LN form a sub-parameter pair. The second terminals of transistors M22 and M23 are respectively coupled to the second transistor pair and the third transistor pair.

[0020] In the second transistor pair, the first terminals of transistors M24 and M25 are coupled to the second terminal of transistor M22. Transistors M24 and M25 are controlled by sub-parameters TAP1P and TAP1N, respectively, which form a sub-parameter pair. Sub-parameters TAP1P and TAP1N are generated according to the aforementioned correction parameters. The second terminals of transistors M24 and M25 generate a first bias voltage PP and a second bias voltage PN, respectively.

[0021] In the third transistor pair, the first terminals of transistors M26 and M27 are coupled to the second terminal of transistor M23; transistors M26 and M27 are controlled by sub-parameters TAP1N and TAP1P, respectively; the second terminals of transistors M26 and M27 generate a first bias voltage PP and a second bias voltage PN, respectively.

[0022] In this embodiment, the sub-parameters TAP1N and TAP1P can be complementary to each other.

[0023] Furthermore, in this embodiment, one of transistors M22 and M23 can be turned on according to sub-parameters H1HP and H1LN, while the other is turned off. Alternatively, transistors M22 and M23 can be turned off simultaneously according to sub-parameters H1HP and H1LN. One of transistors M24 and M25 can be turned on according to sub-parameters TAP1N and TAP1P, while the other is turned off; one of transistors M26 and M27 can be turned on according to sub-parameters TAP1N and TAP1P, while the other is turned off.

[0024] On the other hand, the second part of the circuit 220 includes transistors M28-M33, inverters IV1 and IV2, and multiple pull-down transistors MD1-MD4. The first terminals of transistors M28 and M29 jointly receive the power supply voltage VPP; transistors M28 and M29 are jointly controlled by the clock signal CK; the second terminal of transistor M28 is coupled to transistors M30 and M32, while the second terminal of transistor M29 is coupled to transistors M31 and M33.

[0025] The first terminal of transistor M30 is coupled to the second terminal of transistor M28; transistor M30 is controlled by the first sub-signal DINP of signal pair S2X; the second terminal of transistor M30 receives the first bias voltage PP and serves as the power supply terminal of inverter IV1. The first terminal of transistor M31 is coupled to the second terminal of transistor M29; transistor M31 is controlled by the sub-reference data DRHN of reference data pair DR or the sub-reference voltage VRHN of reference voltage pair VR; the second terminal of transistor M31 is coupled to the second terminal of transistor M30.

[0026] The first terminal of transistor M33 is coupled to the second terminal of transistor M29; transistor M33 is controlled by the second sub-signal DINN of signal pair S2X; the second terminal of transistor M33 receives the second bias voltage PN and serves as the power supply terminal of inverter IV2. The first terminal of transistor M32 is coupled to the second terminal of transistor M28; transistor M32 is controlled by the sub-reference data DRHP of reference data pair DR or the sub-reference voltage VRHP of reference voltage pair VR; the second terminal of transistor M32 is coupled to the second terminal of transistor M33.

[0027] Inverter IV1 is coupled between the second terminals of transistors M32 and M33 and the reference ground voltage VSS, and inverter IV2 is coupled between the second terminals of transistors M31 and M34 and the reference ground voltage VSS. The output of inverter IV1 is coupled to the input of inverter IV2 and generates sub-sampled data SDP or sub-error data ErP. The output of inverter IV2 is coupled to the input of inverter IV1 and generates sub-sampled data SDN or sub-error data ErN. Inverters IV1 and IV2 can form a latch-up circuit to latch the generated sub-sampled data SDP, SDN, or sub-error data ErP, ErN.

[0028] Incidentally, pull-down transistors MD1 and MD2 are coupled between the second terminals of transistors M30 and M32 and the reference ground voltage VSS, and are controlled by the clock signal CK. When pull-down transistors MD1 and MD2 are turned on according to the clock signal CK, the voltage at the second terminals of transistors M30 and M32 can be reset to the reference ground voltage VSS. Pull-down transistors MD3 and MD4 are coupled between the output terminals of inverters IV1 and IV2 and the reference ground voltage VSS, and are controlled by the clock signal CK. When pull-down transistors MD3 and MD4 are turned on according to the clock signal CK, the latched data in the latch formed by inverters IV1 and IV2 of transistors M30 and M32 can be reset.

[0029] Please refer to Figure 3, which illustrates a schematic diagram of the three-level voltage segmentation waveform of the divider group in the embodiment of Figure 2. When the data receiving device of the present invention is applied to the encoding and decoding technology of three-level pulse amplitude modulation (PAM3), when the sub-parameters H1HP and H1LN are logic values ​​1 and 0 respectively, it corresponds to the highest voltage level L1; when the sub-parameters H1HP and H1LN are both logic values ​​1 and 0 respectively, it corresponds to the middle voltage level L2; and when the sub-parameters H1HP and H1LN are logic values ​​0 and 1 respectively, it corresponds to the lowest voltage level L3.

[0030] Based on voltage levels L1~L3, the encoding and decoding of three-level pulse amplitude modulation can be completed.

[0031] Please refer to Figure 4, which illustrates a schematic diagram of an embodiment of the divider group in the signal receiving device of the present invention. The divider group 400 is a double feedback end divider group. The divider group 400 can also be applied to any of the divider groups SC11 to SC24 in the embodiment of Figure 1. The divider group 400 includes a first part circuit 410 and a second part circuit 220.

[0032] In this embodiment, the second part of the circuit 220 in the divider group 400 is the same as the second part of the circuit 220 in the embodiment of FIG2, and the relevant details will not be described in detail.

[0033] In this embodiment, the first part of the circuit 410 is constructed using a dual-ended feedback method. The first part of the circuit 410 includes transistors M41 to M54. Transistors M41 and M42 form a transistor pair, wherein the first terminals of transistors M41 and M42 jointly receive the power supply voltage VPP; the control terminals of transistors M41 and M42 jointly receive the clock signal CK. Transistors M43 and M44 form a transistor pair and are coupled to the second terminal of transistor M41. The control terminal of transistor M43 receives the sub-parameter pair H1HP of parameter H1; the control terminal of transistor M44 receives the sub-parameter pair H1HN of parameter H1. Transistors M45 and M46 form a transistor pair and are coupled to the second terminal of transistor M42. The control terminal of transistor M45 receives the sub-parameter pair H1LP of parameter H1; the control terminal of transistor M46 receives the sub-parameter pair H1LN of parameter H1.

[0034] Transistors M47 to M54 form a pair. Transistors M47 and M48 are coupled to the second terminal of transistor M43. The control terminals of transistors M47 and M48 receive parameters TAP1P and TAP1N, respectively. The second terminals of transistors M47 and M48 provide a first bias voltage PP and a second bias voltage PN, respectively. Transistors M49 and M50 are coupled to the second terminal of transistor M44. The control terminals of transistors M49 and M50 receive parameters TAP1N and TAP1P, respectively. The second terminals of transistors M49 and M50 provide a first bias voltage PP and a second bias voltage PN, respectively.

[0035] On the other hand, transistors M51 and M52 are coupled to the second terminal of transistor M45. The control terminals of transistors M51 and M52 receive parameters TAP1P and TAP1N, respectively, and the second terminals of transistors M51 and M52 provide a first bias voltage PP and a second bias voltage PN, respectively. Transistors M53 and M54 are coupled to the second terminal of transistor M46. The control terminals of transistors M53 and M54 receive parameters TAP1N and TAP1P, respectively, and the second terminals of transistors M53 and M54 provide a first bias voltage PP and a second bias voltage PN, respectively.

[0036] Please refer to Figure 5 below. Figure 5 shows a schematic diagram of the three-level voltage segmentation waveform of the divider group in the embodiment of Figure 4. When the data receiving device of the present invention is applied to the encoding and decoding technology of three-level pulse amplitude modulation (PAM3), when the sub-parameters H1HP, H1HN, H1LP, and H1LN are logic values ​​1, 0, 1, and 0 respectively, it corresponds to the highest voltage level L1; when the sub-parameters H1HP, H1HN, H1LP, and H1LN are logic values ​​0, 1, 1, and 0 respectively, it corresponds to the middle voltage level L2; when the sub-parameters H1HP, H1HN, H1LP, and H1LN are logic values ​​0, 1, 0, and 1 respectively, it corresponds to the lowest voltage level L3.

[0037] In summary, the signal receiving device of the present invention provides different error information to the clock recovery circuit and the decision feedback equalizer, allowing the clock recovery circuit and the decision feedback equalizer to have different convergence messages. In this way, logical operation conflicts between the clock recovery circuit and the decision feedback equalizer can be avoided, effectively improving the operating performance of the signal receiving device.

[0038] 100: Signal receiving device 110: Analog front-end circuit 121~124: Adders 130: Clock Recovery Circuit 140: Judgment Feedback, Equalizer 200, 400: Divider group 210, 410: First part of the circuit 220, 420: Second part of the circuit AXH1: Correction parameter CK: Clock signal DOUT: Output signal DR: References DRHP, DRHN: Sub-references Er1~Er4: Error Information ErP, ErN: Sub-error data H1~H8: Parameters H1HP, H1HN, H1LP, H1LN, TAP1P, TAP1N: Sub-parameters SIN: Input signal IV1, IV2: Inverters L1~L3: Voltage Levels M21~M54: Transistors PP, PN: Bias voltage S11~S14, S21~S24: Signal pairs SC11~SC14, SC21~SC24: Divider Group SD1~SD4: Sampled data SDP, SDN: Post-sampling data TAP1P, TAP1N: Parameters VPP: Power supply voltage VR: Reference voltage pair VSS: Reference ground voltage

Claims

1. A signal receiving device, comprising: An analog front-end circuit processes an input signal to generate multiple first signal pairs with different phases; A plurality of adders, each receiving the first signal pairs, each adder adding each of the first signal pairs to a plurality of first parameters to generate each of a plurality of second signal pairs; a plurality of first divider groups, each corresponding to the adders, sampling the second signal pairs based on a second parameter and a reference data pair to generate a plurality of sampled data; a plurality of second divider groups, each corresponding to the adders, a plurality of selected divider groups of a portion of the second divider groups, sampling the corresponding second signal pairs based on a correction parameter and a reference voltage pair to generate a plurality of first error information; at least one unselected divider group of the second divider groups, sampling the corresponding second signal pairs based on the second parameter and the reference voltage pair to generate a second error information; a clock recovery circuit and a decision feedback equalizer, each generating a plurality of received data corresponding to the input signal based on the first error information and the second error information.

2. The signal receiving apparatus as claimed in claim 1, wherein the correction parameter is A times the second parameter, where A is a positive real number not equal to 1.

3. The signal receiving apparatus as claimed in claim 1, wherein the second error information is used as convergence information for the decision feedback equalizer, and the first error information is used as convergence information for the clock recovery circuit.

4. The signal receiving apparatus as claimed in claim 1, wherein the first signals have different phases.

5. The signal receiving apparatus as claimed in claim 1, wherein the first signal pair and the second signal pair are both differential signal pairs.

6. The signal receiving apparatus of claim 1, wherein the reference data pair includes a first reference data and a second reference data, the first reference data and the second reference data being complementary; the reference voltage pair includes a first reference voltage and a second reference voltage, the first reference voltage being greater than the second reference voltage.

7. The signal receiving apparatus as claimed in claim 1, wherein each of the first divider groups and the second divider groups comprises: A first part of the circuit is used to provide a first bias voltage and a second bias voltage according to the second parameter and the correction parameter; And a second part of the circuit, coupled to the first part of the circuit, generates corresponding sampled data, second error information or first error information by comparing the corresponding second signal pairs with the reference data pairs or the reference voltage pairs based on the first bias and the second bias.

8. The signal receiving apparatus as claimed in claim 7, wherein the first part of the circuitry includes: A first transistor pair receives a power supply voltage and is turned on or off according to a clock signal; A second transistor pair and a third transistor pair are coupled to the first transistor pair, wherein the second transistor pair selects the conduction path according to the first sub-parameter pair of the second parameter, and the third transistor pair selects the conduction path according to the second sub-parameter pair of the second parameter; And a fourth to a seventh transistor pair, wherein the fourth transistor pair is coupled to the fifth transistor pair to the second transistor pair, the sixth transistor pair is coupled to the seventh transistor pair to the third transistor pair, and each of the fourth to the seventh transistor pairs selects a conduction path according to a sub-parameter pair generated by the correction parameter, thereby generating the first bias voltage and the second bias voltage.

9. The signal receiving apparatus as claimed in claim 7, wherein the first part of the circuitry includes: A first transistor receives a power supply voltage and is turned on or off according to a clock signal; A first transistor pair is coupled to the first transistor, wherein the first transistor pair selects the conduction path according to the first sub-parameter pair of the second parameter; A second transistor pair and a third transistor pair are coupled to the first transistor pair, and the conduction path is selected according to the sub-parameter pair of the correction parameters, thereby generating the first bias voltage and the second bias voltage.

10. The signal receiving apparatus as claimed in claim 7, wherein the second part of the circuitry includes: A first transistor and a second transistor receive a power supply voltage and are turned on or off according to a clock signal; A third transistor and a fourth transistor, each having a first terminal coupled to the first transistor and the second transistor respectively, the third transistor being controlled by a first sub-signal of each of the second signal pairs, the fourth transistor being controlled by a first sub-reference data of the reference data pair or a first sub-reference voltage of the reference voltage pair, the second terminals of the third transistor and the fourth transistor being mutually coupled and receiving the first bias voltage; a fifth transistor and a sixth transistor, each having a first terminal coupled to the first transistor and the second transistor respectively, the fifth transistor being controlled by a first sub-signal of each of the second signal pairs, the fourth transistor being controlled by a first sub-reference data of the reference data pair or a first sub-reference voltage of the reference voltage pair, the second terminals of the fifth transistor and the sixth transistor being mutually coupled and receiving the second bias voltage; a first inverter and a second inverter, the power supply terminal of the first inverter being coupled to the second terminals of the third transistor and the fourth transistor; the third transistor... The power supply terminals of the two inverters are coupled to the second terminals of the fifth and sixth transistors. The output terminal of the first inverter is coupled to the input terminal of the second inverter and generates the first sub-sampled data of each sampled data, the first sub-error data of each first error information, or the first sub-error data of the second error information. The input terminal of the first inverter is coupled to the output terminal of the second inverter and generates the second sub-sampled data of each sampled data, the second sub-error data of each first error information, or the second sub-error data of the second error information.

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