Silicon-on-insulator (SOI) replacement for 4f2 dram using sacrificial silicon germanium and bottom-up dielectric

TW202641003APending Publication Date: 2026-10-01APPLIED MATERIALS INC
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Patent Information

Application Number
TW114139503
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Priority Date
2025-03-28
Filing Date
2025-10-14
Publication Date
2026-10-01

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Abstract

Silicon substrates may be used with a silicon germanium layer on the substrate instead of Silicon-on-Insulator (SOI) substrates. Shallow Trench Isolation (STI) trenches may include a dielectric such as silicon oxide at the bottom of the trench, with the remainder of the trench filled with silicon germanium or other materials that can be dry etched with silicon in a silicon etch chemistry, and that can also be removed selective to silicon by other dry or wet etch methods. Channel etches may then be configured to remove the silicon and silicon germanium while leaving the silicon oxide intact and avoids etching silicon and oxide simultaneously. The dielectric may also provide structural support throughout the manufacturing process. The silicon germanium layer adjacent to the silicon substrate may then be removed and replaced with a stronger layer stop layer for a backside etch.
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