SRAM macro design architecture

TW202641005APending Publication Date: 2026-10-01APPLE INC
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Patent Information

Application Number
TW115104347
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Priority Date
2023-08-11
Filing Date
2023-09-15
Publication Date
2026-10-01

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Abstract

A memory device layout that implements SRAM cells with stacked transistors is disclosed. The memory utilizes both topside metal routing and backside metal routing for routing of bitlines between bit cells with stacked transistors and logic cells coupled to the bit cells.
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