Semiconductor memory devices

Abstract

This invention provides a semiconductor memory device capable of suppressing substrate undercut. One embodiment of the semiconductor memory device includes a first stacked layer, a second stacked layer, memory pillars, a first contact, a first break portion, a second contact, and a second break portion. The first stacked layer includes a plurality of first wiring layers and a plurality of first insulating layers disposed on the same layer as the plurality of first wiring layers. The second stacked layer includes a plurality of second wiring layers and a plurality of second insulating layers disposed on the same layer as the plurality of second wiring layers, and is disposed above the first stacked layer. The memory pillars penetrate the plurality of first and second wiring layers. The first contact penetrates the second stacked layer and is connected to a third wiring layer among the plurality of first wiring layers. The first break portion breaks the plurality of first wiring layers. The second contact is connected to a fourth wiring layer among the plurality of second wiring layers. The second segment divides multiple second wiring layers. The second segment does not overlap with the first segment.

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