Semiconductor devices and semiconductor memory

Abstract

This reduces contact resistance and increases the withstand voltage between the two transistors. The semiconductor device 1 of this embodiment includes a substrate 20, insulating films 60 and 70, conductive layers 62 and 72, and first to third contact plugs CP. The substrate includes a diffusion region NM2 and a diffusion region NP0-1. The diffusion region NM2 corresponds to one end of transistors T9 and T10. The diffusion region NP0-1 has a higher impurity concentration than the diffusion region NM2. A siliconized portion 51 is formed on the upper part of the diffusion region NP0-1. The conductive layer 62 corresponds to the gate electrode GEa of the first transistor. A siliconized portion 63 is formed on the upper part of the conductive layer 62, except for a portion thereof. The conductive layer 72 corresponds to the gate electrode GEb of transistor T10. A siliconized portion 73 is formed on the upper part of the conductive layer 72. When viewed from above, a portion of the conductive layer 62 is disposed between the two siliconized portions 51 and 63.

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