Semiconductor device and method for fabricating the same

Abstract

A method for fabricating a semiconductor device includes the steps of first forming a trench in a substrate, forming a gate dielectric layer in the trench, forming a liner on the gate dielectric layer, forming a gate structure on the liner, forming a source electrode on the substrate, and then forming a drain electrode on a backside of the substrate. Preferably, the gate dielectric layer includes a U-shape cross-section and the liner includes a reverse T-shape cross-section.

Description

Technical Field

[0001] This invention relates to a semiconductor device and its fabrication method, particularly a silicon carbide metal oxide semiconductor field-effect transistor (SiC MOSFET) and its fabrication method. Prior Technology

[0002] Power semiconductor devices include insulated gate bipolar transistors (IGBTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs). Silicon carbide MOSFETs have critical breakdown strength, can operate at higher temperatures, provide higher current density, and support higher switching frequencies. While metal-oxide-semiconductor (MOSFETs) possess the aforementioned advantages, the thin gate oxide layer and low oxide quality make the gate oxide layer of silicon carbide (SiO2) MOSFETs relatively fragile during operation and electrostatic discharge (ESD) stress, due to voltage surges induced by gate bias. In the prior art, additional devices can be added to semiconductor devices to protect the gate oxide layer from voltage overshoot and ESD stress. However, these additional devices require additional space to accommodate the structures, thereby increasing the cell spacing of the semiconductor device. Since the existing manufacturing methods for SiO2 MOSFETs still have many problems, providing a SiO2 MOSFET and its manufacturing method to address the shortcomings of the prior art and enhance its practical industrial application is an important current issue. Summary of the Invention

[0003] One embodiment of the present invention discloses a method for fabricating a semiconductor device, which mainly involves first forming a groove in a substrate, then forming a gate dielectric layer in the groove, forming a pad layer on the gate dielectric layer, forming a gate structure on the pad layer, forming a source electrode on the substrate, and finally forming a drain electrode on the back side of the substrate. The gate dielectric layer comprises a U-shape, while the pad layer comprises an inverted T-shape.

[0004] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a groove disposed in a substrate, a gate dielectric layer disposed in the groove, a pad layer disposed on the gate dielectric layer, a gate structure disposed on the pad layer, a source electrode disposed on the substrate, and a drain electrode disposed on the back side of the substrate.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a groove disposed in a substrate, a doped region disposed below the groove, a gate dielectric layer disposed in the groove, a gate structure disposed on the gate dielectric layer, a source electrode disposed on the substrate, and a drain electrode disposed on the back side of the substrate. Simple Explanation of the Diagram

[0006] Figures 1 to 9 are schematic diagrams illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figures 10 to 14 are schematic diagrams illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Implementation

[0007] Although this document discusses specific configurations and arrangements, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0008] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include those specific features, structures, or characteristics. Furthermore, such terms do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0009] Generally, terms can be understood, at least in part, based on their usage in context. For example, the term “one or more” (at least in part, depending on context) as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or to describe a plural combination of features, structures, or characteristics. Similarly, terms such as “a,” “an,” or “the” can again be understood to express a singular usage or to convey a plural usage, at least in part, depending on context. Furthermore, the term “based on” can be understood to not necessarily convey an exclusive set of factors, and can conversely allow for additional factors that are not necessarily explicitly described, at least in part, depending on context.

[0010] It should be readily understood that the meanings of “on top of,” “above,” and “above” in the disclosed content of this case should be interpreted in the broadest sense, such that “on top of” not only means “directly” on something, but also includes the meaning of being on something and having intermediate features or layers between them, and that “above” or “above” not only means being on or above something, but also includes the meaning of not having intermediate features or layers (i.e., being directly on something).

[0011] Furthermore, for ease of description, as illustrated in the figures, spatial relative terms such as "below," "under," "lower," "above," and "higher" can be used to describe the relationship of one or more elements or features to another. In addition to the orientations depicted in the figures, the spatial relative terms are intended to encompass different orientations of elements in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptions used herein can be interpreted accordingly.

[0012] As used herein, the term "substrate" refers to the material on which layers of material are subsequently added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0013] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entire lower or upper layer structure, or may have a extent smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes between the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on and / or below it. A single layer may contain multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0014] Please refer to Figures 1 to 9, which are schematic diagrams illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. As shown in Figure 1, a substrate 12 made of semiconductor material is first provided. The substrate 12 preferably includes a silicon carbide (SiC) substrate, but is not limited thereto. According to other embodiments of the present invention, the substrate 12 may also be a semiconductor substrate such as a silicon substrate, an epitaxial silicon substrate, or even a substrate made of silicon-on-insulator (SOI). These material choices are all within the scope of the present invention.

[0015] A drift region 14 is then formed within the substrate 12. A portion of the substrate 12 or the drift region 14 is then removed using a photolithography and etching process to form a groove 16. Preferably, the bottom surface of the groove 16 is higher than the bottom surface of the drift region 14. In this embodiment, the drift region 14 preferably includes an N-drift region, but is not limited to this.

[0016] As shown in Figure 2, a gate dielectric layer 18 is then sequentially formed in the groove 16 and a pad layer 20 is formed on the gate dielectric layer 18, wherein the gate dielectric layer 18 and the pad layer 20 may have approximately the same thickness. In addition, the gate dielectric layer 18 formed in this stage preferably contains silicon oxide and the pad layer 20 preferably contains silicon nitride (SiN).

[0017] Subsequently, as shown in Figure 3, an organic dielectric layer (ODL) 22 is formed in the groove 16, wherein the organic dielectric layer 22 preferably fills the groove 16 and covers the surface of the padding layer 20 on both sides of the groove 16.

[0018] As shown in Figure 4, the organic dielectric layer 22 within the groove 16 and all organic dielectric layers 22 on both sides of the groove 16 are then removed using an etch-back method, leaving the remaining organic dielectric layer 22 only on the surface of the padding layer 20 within the groove 16. Preferably, the top surface of the remaining organic dielectric layer 22 in this stage is lower than the surfaces of the substrate 12 or drift region 14 on both sides of the groove 16, or even lower than half the overall depth of the groove 16. Preferably, the organic dielectric layer 22 has a straight-line cross-section, and its thickness can be approximately equal to the thickness of the padding layer 20 and / or the gate dielectric layer 18.

[0019] Subsequently, as shown in Figure 5, an etching process is performed, for example, using wet etching to remove all the pad layers 20 on both sides of the groove 16 and part of the pad layers 20 on both sides of the organic dielectric layer 22, so that the remaining pad layers 20 are disposed on the gate dielectric layers 18 directly below and on both sides of the organic dielectric layer 22. Preferably, the remaining pad layers 20 in this stage have an inverted T-shaped cross-section and the sidewalls of the organic dielectric layer 22 are preferably flush with the sidewalls of the pad layers 20 directly below it.

[0020] As shown in Figure 6, another etching process is then performed to completely remove the organic dielectric layer 22 and expose the surface of the pad layer 20.

[0021] Next, as shown in Figure 7, a gate structure 24 is formed within the groove 16. In this embodiment, the gate structure 24 can be formed by first forming a gate material layer (not shown) within the groove 16 and filling the groove 16, and then removing part of the gate material layer and part of the gate dielectric layer 18 on both sides of the groove 16 by means such as etching to form a gate structure 24 or gate electrode composed of a patterned gate material layer. In this embodiment, the gate material layer or gate structure 24 may contain polysilicon or metal, but is not limited to these.

[0022] Subsequently, as shown in Figure 8, a well region 26 is formed in the substrate 12 or drift region 14 on both sides of the groove 16 or gate structure 24. A first doped region 30 and a second doped region 32 are formed in the well region 26 on one side of the groove 16, as shown on the left. A third doped region 34 and a fourth doped region 36 are formed in the well region 26 on the other side of the groove 16, as shown on the right. Then, an interlayer dielectric layer 40 is formed on the substrate 12 and covers the gate structure 24, the gate dielectric layer 18, part of the second doped region 32, and part of the third doped region 34. The interlayer dielectric layer 40 can be formed by first depositing a dielectric layer (not shown) composed of oxide on the substrate 12, and then removing part of the dielectric layer using a photolithography and etching process to form the interlayer dielectric layer 40.

[0023] In this embodiment, the drift region 14 and the well region 26 preferably have different conductivity types, the first doped region 30 and the second doped region 32 have different conductivity types, and the third doped region 34 and the fourth doped region 36 have different conductivity types. The drift region 14 preferably includes an N-drift region, the well region 26 includes a P-well, the first doped region 30 includes a P+ doped region, the second doped region 32 includes an N+ doped region, the third doped region 34 includes an N+ doped region, and the fourth doped region 36 includes a P+ doped region. The interlayer dielectric layer 40 may include silicon oxide, such as tetraethyl orthosilicate (TES), but is not limited to this.

[0024] Then, as shown in Figure 9, a source electrode 42 is formed on the gate structure 24, covering the first doped region 30, the second doped region 32, the third doped region 34, and a fourth doped region 36. In this embodiment, the source electrode 42 may contain conductive or metallic materials such as aluminum, titanium, or titanium nitride. Finally, the substrate 12 can be flipped and a deposition process performed to form a metal layer as a drain electrode 44 on the back side or bottom surface of the substrate 12. In this embodiment, the drain electrode 44 may contain the same or different materials as the source electrode 42; for example, the drain electrode 44 may contain conductive or metallic materials such as aluminum, titanium, or titanium nitride. This completes the fabrication of a semiconductor device or silicon carbide gold-oxide-semiconductor field-effect transistor of the present invention.

[0025] Please refer to Figures 10 to 14, which are schematic diagrams illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. To correspond with the aforementioned embodiments, the same components in this embodiment are preferably numbered the same as those in the previous embodiments. As shown in Figure 10, a substrate 12 made of semiconductor material is first provided. The substrate 12 preferably comprises a silicon carbide (SiC) substrate, but is not limited thereto. According to other embodiments of the present invention, the substrate 12 may also be a semiconductor substrate such as a silicon substrate, an epitaxial silicon substrate, or even a substrate composed of silicon-on-insulator (SOI). These material choices are all within the scope of the present invention.

[0026] Then, a drift region 14 is formed within the substrate 12. A patterned mask 46 is used as a mask to perform an etching process to remove part of the substrate 12 or the drift region 14 to form a groove 16, wherein the bottom surface of the groove 16 is preferably higher than the bottom surface of the drift region 14. Subsequently, an ion implantation process 50 is performed using the same patterned mask 46 as a mask to implant the dopant into the substrate 12 at the bottom of the groove 16 or on the surface of the drift region 14 to form a doped region 48. The drift region 14 and the doped region 48 preferably contain different conductivity types. For example, in this embodiment, the drift region 14 preferably contains an N-drift region and the doped region 48 preferably contains a P-type doped region, but it is not limited to this.

[0027] As shown in Figure 12, the patterned mask 46 is then removed, and a gate dielectric layer 18 is sequentially formed within the groove 16, and a gate structure 24 is formed on the gate dielectric layer 18. Preferably, the gate dielectric layer 18 contacts the doped region 48 located directly below it within the substrate 12. As in the aforementioned embodiment, the gate dielectric layer 18 preferably comprises silicon oxide, while the gate structure 24 may comprise polycrystalline silicon or a metal, but is not limited thereto. Furthermore, the overall thickness of the doped region 48 may be approximately less than, equal to, or greater than the thickness of the gate dielectric layer 18, and the sidewalls of the doped region 48 may be either flush with or not flush with the sidewalls of the groove 16 above it.

[0028] Subsequently, as shown in Figure 13, a well region 26 is formed in the substrate 12 or drift region 14 on both sides of the groove 16 or gate structure 24. A first doped region 30 and a second doped region 32 are formed in the well region 26 on one side of the groove 16, as shown on the left. A third doped region 34 and a fourth doped region 36 are formed in the well region 26 on the other side of the groove 16, as shown on the right. Then, an interlayer dielectric layer 40 is formed on the substrate 12 and covers the gate structure 24, the gate dielectric layer 18, part of the second doped region 32, and part of the third doped region 34. The interlayer dielectric layer 40 can be formed by first depositing a dielectric layer (not shown) composed of oxide on the substrate 12, and then removing part of the dielectric layer using a photolithography and etching process to form the interlayer dielectric layer 40.

[0029] As in the aforementioned embodiments, the drift region 14 and the well region 26 preferably have different conductivity types, the first doped region 30 and the second doped region 32 have different conductivity types, and the third doped region 34 and the fourth doped region 36 have different conductivity types. The drift region 14 preferably includes an N-drift region, the well region 26 includes a P-well, the first doped region 30 includes a P+ doped region, the second doped region 32 includes an N+ doped region, the third doped region 34 includes an N+ doped region, and the fourth doped region 36 includes a P+ doped region. The interlayer dielectric layer 40 may include silicon oxide, such as tetraethyl orthosilicate (TES), but is not limited to this.

[0030] Then, as shown in Figure 14, a source electrode 42 is formed on the gate structure 24, covering the first doped region 30, the second doped region 32, the third doped region 34, and a fourth doped region 36. In this embodiment, the source electrode 42 may contain conductive or metallic materials such as aluminum, titanium, or titanium nitride. Finally, the substrate 12 can be flipped and a deposition process performed to form a metal layer as a drain electrode 44 on the back side or bottom surface of the substrate 12. In this embodiment, the drain electrode 44 may contain the same or different materials as the source electrode 42; for example, the drain electrode 44 may contain conductive or metallic materials such as aluminum, titanium, or titanium nitride. This completes the fabrication of a semiconductor device or silicon carbide gold-oxide-semiconductor field-effect transistor of the present invention.

[0031] In summary, this invention mainly discloses a silicon carbide metal-oxide-semiconductor (SiC MOSFET) with a trench gate and its fabrication method. As shown in the embodiments of Figures 1 to 9, a trench is first formed in the substrate, followed by the sequential formation of a gate dielectric layer and a pad layer within the trench. An organic dielectric layer 22 is then used to remove the pad layers on both sides of the trench, and finally, a gate structure is formed within the trench. Alternatively, as shown in the embodiments of Figures 10 to 14, a trench is formed in the substrate, a doped region 48 is formed in the substrate directly below the trench using an ion implantation process, and then the gate dielectric layer and gate structure are sequentially formed within the trench. According to the preferred embodiments of this invention, the trench gate prepared using the above two methods can improve the peak electric field directly below the gate structure, thereby increasing device density, reducing channel resistance, and improving switching speed. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0032] 12: Base 14: Drift Zone 16: Groove 18: Gate dielectric layer 20: Padding layer 22: Organic dielectric layer 24: Gate Structure 26: Well Area 30: First doped region 32: Second doped region 34: Third doped region 36: Fourth doped region 40: Interlayer dielectric layer 42: Source electrode 44: Drain electrode 46: Patterned Mask 48: Doped region 50: Ion implantation process

Claims

1. A method for fabricating a semiconductor device, characterized in that it comprises: forming a recess in a substrate; forming a gate dielectric layer in the recess; forming a pad layer on the gate dielectric layer; forming a gate structure on the pad layer; forming a source electrode on the substrate; and forming a drain electrode on the back side of the substrate.

2. The method as described in claim 1, further comprising: forming the gate dielectric layer in the groove and disposed on the substrate on both sides of the groove; forming the pad layer on the gate dielectric layer; patterning the pad layer; forming the gate structure on the pad layer; forming a well region on both sides of the groove; forming a first doped region and a second doped region on one side of the groove; forming a third doped region and a fourth doped region on the other side of the groove; forming an interlayer dielectric layer on the gate structure; and forming the source electrode on the first doped region, the second doped region, the third doped region, the fourth doped region, and the interlayer dielectric layer.

3. The method as described in claim 2, wherein patterning the pad layer further comprises: forming an organic dielectric layer on the pad layer within the groove; and removing the pad layer from both sides of the organic dielectric layer.

4. The method as described in claim 2, wherein the first doped region and the second doped region comprise different conductivity types.

5. The method as described in claim 2, wherein the third doped region and the fourth doped region comprise different conductivity types.

6. The method as described in claim 1, wherein the gate dielectric layer comprises a U-shape.

7. The method as described in claim 1, wherein the padding layer comprises an inverted T-shape.

8. A semiconductor device, characterized in that it comprises: a recess disposed in a substrate; a gate dielectric layer disposed in the recess; a pad layer disposed on the gate dielectric layer; a gate structure disposed on the pad layer; a source electrode disposed on the substrate; and a drain electrode disposed on the back side of the substrate.

9. The semiconductor device as described in claim 8 further comprises: a well region disposed on both sides of the groove; a first doped region and a second doped region disposed on one side of the groove; a third doped region and a fourth doped region disposed on the other side of the groove; and an inter-dielectric layer disposed on the gate structure.

10. The semiconductor device as described in claim 9, wherein the source electrode overlaps the first doped region, the second doped region, the third doped region, the fourth doped region, and the interlayer dielectric layer.

11. The semiconductor device as described in claim 9, wherein the first doped region and the second doped region comprise different conductivity types.

12. The semiconductor device as described in claim 9, wherein the third doped region and the fourth doped region comprise different conductivity types.

13. The semiconductor device as described in claim 8, wherein the gate dielectric layer comprises a U-shape.

14. The semiconductor element as described in claim 8, wherein the pad layer comprises an inverted T shape.

15. A semiconductor device, characterized in that it comprises: a recess disposed within a substrate; a doped region disposed below the recess; a gate dielectric layer disposed within the recess; a gate structure disposed on the gate dielectric layer; a source electrode disposed on the substrate; and a drain electrode disposed on the back side of the substrate.

16. The semiconductor device as described in claim 15 further comprises: a drift region disposed below the groove; a well region disposed on both sides of the groove; a first doped region and a second doped region disposed on one side of the groove; a third doped region and a fourth doped region disposed on the other side of the groove; and an inter-dielectric layer disposed on the gate structure.

17. The semiconductor device as described in claim 16, wherein the drift region and the doped region comprise different conductivity types.

18. The semiconductor device as described in claim 16, wherein the source electrode overlaps the first doped region, the second doped region, the third doped region, the fourth doped region, and the interlayer dielectric layer.

19. The semiconductor device as described in claim 16, wherein the first doped region and the second doped region comprise different conductivity types.

20. The semiconductor device as described in claim 16, wherein the third doped region and the fourth doped region comprise different conductivity types.

Images