Semiconductor structure

Abstract

The present disclosure provides a semiconductor structure. The semiconductor structure may be included in a memory device. The memory device is, for example, a 3D NAND flash memory and provides a storage media with high-performance and high-capacity. The semiconductor structure includes a substrate including an active region and a source region, a drain region and at least one lightly doped region disposed in the active region, a gate layer disposed over the active region, and a dummy gate layer disposed over the lightly doped region and electrically connected to the gate layer. The source region and the drain region are disposed at opposite sides of the gate layer in a first direction, and the lightly doped region is configured between the gate layer and the drain region.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure, and more particularly to a semiconductor structure for use in high-voltage semiconductor devices. Prior Technology

[0002] High-voltage semiconductor devices are power devices commonly used in analog and / or digital circuits. They can be categorized into planar and vertical power semiconductor devices based on the direction of current flow. In planar power semiconductor devices, increasing the gate-to-drain distance is one method to improve the operating voltage. However, this method also faces some problems. For example, as the gate-to-drain distance increases, the drive voltage (Ion) of the power semiconductor device will be affected by the increased resistance. Conversely, methods to reduce resistance, such as increasing the doping concentration in lightly doped regions, can lead to a decrease in the breakdown voltage of the power semiconductor device, thus affecting its operating voltage.

[0003] Therefore, those skilled in the art continue to improve high-voltage semiconductor devices. Summary of the Invention

[0004] This disclosure provides a semiconductor structure in which a dummy gate layer is configured above a lightly doped region and electrically connected to the gate layer, which helps to improve the breakdown voltage and prevent the driving voltage of high-voltage semiconductor devices containing the semiconductor structure from being affected.

[0005] One embodiment of this disclosure provides a semiconductor structure including a substrate, a gate layer, and a dummy gate layer. The substrate includes an active region and a source region, a drain region, and at least one lightly doped region disposed within the active region. The gate layer is disposed above the active region, wherein the source region and the drain region are disposed on opposite sides of the gate layer in a first direction, and the lightly doped region is disposed between the gate layer and the drain region. The dummy gate layer is disposed above the lightly doped region and is electrically connected to the gate layer.

[0006] Another embodiment of this disclosure provides a semiconductor structure including a substrate, a gate layer, and a plurality of dummy gate layers. The substrate includes an active region and a first source / drain region, a second source / drain region, and a plurality of lightly doped regions disposed within the active region. The gate layer is disposed above the active region, wherein the first source / drain region and the second source / drain region are disposed on opposite sides of the gate layer in a first direction, and the plurality of lightly doped regions are respectively disposed between the gate layer and the first source / drain region and between the gate layer and the second source / drain region. The plurality of dummy gate layers are respectively disposed above the plurality of lightly doped regions of the substrate and are electrically connected to the gate layer.

[0007] Another embodiment of this disclosure provides a semiconductor structure including a substrate, a gate structure, and a dummy gate structure. The substrate includes an active region and a source region, a drain region, and at least one lightly doped region disposed within the active region, wherein the lightly doped region is disposed between the source region and the drain region in a first direction. The gate structure is disposed on the active region and includes a gate layer and a gate insulating layer between the gate layer and the substrate, wherein the source region and the drain region are disposed on opposite sides of the gate layer in the first direction, and the lightly doped region is disposed between the gate layer and the drain region. The dummy gate structure is disposed on the lightly doped region and includes a dummy gate layer and a dummy gate insulating layer between the dummy gate layer and the substrate, wherein the dummy gate layer is electrically connected to the gate layer.

[0008] Based on the above, in the semiconductor structure disclosed herein, the dummy gate layer is configured above the lightly doped region and electrically connected to the gate layer. This can reduce the impact on the breakdown voltage while increasing the doping concentration of the lightly doped region, thereby enabling the high-voltage semiconductor device containing this semiconductor structure to simultaneously have the desired drive voltage and breakdown voltage.

[0009] To make the above-mentioned features and advantages disclosed herein more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0010] Figure 1A shows a three-dimensional structural diagram of a memory block in a memory device according to an embodiment of the present disclosure. Figure 1B shows a partial structural diagram of a memory block according to an embodiment of the present disclosure. Figure 2A shows a top view of the semiconductor structure of the first embodiment disclosed herein. Figure 2B shows a top view taken along line A-A' of Figure 2A in one embodiment of the present disclosure. Figure 3 shows a top view of the semiconductor structure of the second embodiment disclosed herein. Figure 4 shows a top view of the semiconductor structure of the third embodiment disclosed herein. Figure 5 shows a top view of the semiconductor structure of the fourth embodiment of this disclosure. Figure 6 shows a top view of the semiconductor structure of the fifth embodiment disclosed herein. Figure 7A shows a top view of the semiconductor structure of the sixth embodiment of this disclosure. Figure 7B shows a top view of an embodiment disclosed herein, taken along line A-A' of Figure 7A. Figure 7C shows a top view taken along line A-A' of Figure 7A in another embodiment of the present disclosure. Figure 8A shows a three-dimensional schematic diagram of the semiconductor structure of the seventh embodiment of this disclosure. Figure 8B shows a top view of an embodiment disclosed herein, taken along line B-B' of Figure 8A. Figure 9A shows a three-dimensional schematic diagram of the semiconductor structure of the eighth embodiment of this disclosure. Figure 9B shows a top view of an embodiment disclosed herein, taken along line C-C' of Figure 9A. Implementation

[0011] The invention is described more fully with reference to the drawings of this embodiment. However, the invention may be embodied in various different forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings is enlarged for clarity. The same or similar reference numerals denote the same or similar elements, which will not be repeated in the following paragraphs.

[0012] It should be understood that when an element is referred to as being "on" or "connected" to another element, it may be directly on or connected to the other element, or there may be an intermediate element present. If an element is referred to as being "directly on" or "directly connected" to another element, there is no intermediate element present. As used herein, "connection" may refer to a physical and / or electrical connection, while "electrical connection" or "coupling" may mean that there are other elements between the two elements.

[0013] As used herein, “about,” “approximately,” or “substantially” includes the average of the mentioned value and a specific value that can be determined by someone of ordinary skill in the art, within an acceptable range of deviations, taking into account the measurement under discussion and a specific number of errors associated with the measurement (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the use of “about,” “approximately,” or “substantially” herein may be chosen based on the optical, etched, or other properties to select a more acceptable range of deviations or standard deviations, and may not require a single standard deviation to apply to all properties.

[0014] The terminology used herein is for illustrative purposes only and is not intended to limit the scope of this disclosure. In this context, the singular form includes the plural form unless the context otherwise requires.

[0015] The semiconductor structure disclosed herein can be incorporated, for example, into a memory device. The memory device disclosed herein can be, for example, a 3D NAND flash memory, which possesses high performance and high capacity characteristics.

[0016] Please refer to Figures 1A and 1B. Figure 1A shows the equivalent circuit of block 10 of the memory device in a three-dimensional manner. Figure 1B shows the equivalent circuit of memory cell M0 in block 10 in one embodiment. The memory cell M0 in Figure 1A is arranged in the XYZ three-dimensional coordinate system of block 10, but this disclosure is not limited thereto. In this example, block 10 can be divided into four sub-blocks Sub0 to Sub3, and each sub-block Sub0 to Sub3 can be controlled independently.

[0017] Taking sub-block Sub0 as an example, in Figure 1A, each string 11, 12, 13 includes multiple memory cells M0 connected in series along the Z direction. Each memory cell M0 on each string 11, 12, 13 corresponds to a word line WLj among word lines WL1~WLm. Word line WLj can be a word line layer in the XY plane. In this embodiment, j is any positive integer greater than or equal to 1 and less than or equal to m. Memory cell M1 can be configured as a string select transistor coupled to string select line SSL0, and memory cell M2 can be configured as a ground select transistor coupled to ground select line GSL. The string select transistor and the ground select transistor are respectively disposed on opposite sides of the multiple memory cells M0 on each string 11, 12, 13. In this example, strings 11, 12, 13 coupled to the same string select line SSL0 in the same plane (e.g., the plane defined by the X and Z directions) can be defined as sub-block Sub0.

[0018] Strings 11, 12, and 13 are connected to bit lines BL1, BL2, and BL3 respectively via corresponding string select transistors on string select line SSL0. In different sub-blocks, strings in the same row are connected to the same bit line in the Y direction. String select line SSL0 can be a conductor or layer formed above the topmost word line WL1. Each string 11, 12, and 13 can be connected to the same common source line CSL via corresponding ground select transistors on ground select line GSL. Ground select line GSL can be a conductor or layer formed below the bottommost word line WLm. Common source line CSL can be a conductive layer formed above the substrate of the memory device.

[0019] In block 10, the string selection line SSL0 of sub-block Sub0, the string selection line SSL1 of sub-block Sub1, the string selection line SSL2 of sub-block Sub2, and the string selection line SSL3 of sub-block Sub3 can be located on the same conductive layer, but they will be separated into individual stripes. Each separate strip on the same conductive layer can independently control the operation of the corresponding sub-block in block 10.

[0020] In some embodiments, memory cells M0 of the same word line WLj or word line layer coupled to sub-block Sub0 can be defined as one page (in single-level cell (SLC) mode) or three pages (in triple-level cell (TLC) mode). In TLC mode, three pages include a high page, a middle page, and a low page. Memory cells M0 on the same word line WLj are subjected to the same voltage. Each word line WLj can be connected to a driving circuit, such as an X-decoder or a scan driver.

[0021] In some embodiments, within subblock Sub0, one or more dummy lines or layers (not shown) are disposed between string select line SSL0 and the corresponding topmost character line WL1 and / or between ground select line GSL and the bottommost character line WLm. In another embodiment, within subblock Sub0, one or more dummy lines or layers (not shown) are disposed in the middle portions of strings 11, 12, and 13.

[0022] In some embodiments, as shown in FIG1A, bit lines BL1, BL2, and BL3 may be connected to a high-voltage semiconductor element HV1 to block erase bias from entering the sense amplifier (not shown). In some embodiments, as shown in FIG1B, word line WLj corresponding to memory cell M0 may be connected to a high-voltage semiconductor element HV2 to transmit program bias. In some embodiments, the high-voltage semiconductor element HV2 may be a pass transistor. In some embodiments, the pre-charge transistor used to activate the pass transistor may also be a high-voltage element (high-voltage semiconductor element HV3 shown in FIG1B).

[0023] The semiconductor structure disclosed herein is described below. In some embodiments, the semiconductor structure disclosed herein can be applied to at least one of high-voltage semiconductor element HV1, high-voltage semiconductor element HV2, and high-voltage semiconductor element HV3.

[0024] Figure 2A shows a top view of the semiconductor structure according to the first embodiment of this disclosure. Figure 2B shows a top view of an embodiment of this disclosure taken along line A-A' of Figure 2A. For ease of explanation, Figure 2A only shows the active region AA1, source region SR1, drain region DR1, gate layer GL1, dummy gate layer DGL1, drain conductive contact DCT1, and source conductive contact SCT1.

[0025] Please refer to Figures 2A and 2B. The semiconductor structure 100 includes a substrate SUB1, a gate layer GL1, and a dummy gate layer DGL1.

[0026] The substrate SUB1 includes an active region AA1 and a source region SR1, a drain region DR1, and at least one lightly doped region LDD1 disposed within the active region AA1. The substrate SUB1 may include a semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. The semiconductor material in the semiconductor substrate or SOI substrate may include elemental semiconductors (e.g., Si, Ge), alloy semiconductors (e.g., SiGe), or compound semiconductors (e.g., III-V group semiconductors). The semiconductor material may be doped with P-type or N-type dopants to give the substrate SUB1 a P-type or N-type conductivity type.

[0027] A gate layer GL1 is disposed above the active region AA1. A source region SR1 and a drain region DR1 are disposed on opposite sides of the gate layer GL1 in the first direction D1, and at least one lightly doped region LDD1 is disposed between the gate layer GL1 and the drain region DR1. The gate layer GL1 may include a conductive material suitable for serving as a gate, such as polycrystalline silicon. In this embodiment, at least one lightly doped region LDD1 may be configured as multiple regions, respectively located between the gate layer GL1 and the drain region DR1 and between the gate layer GL1 and the source region SR1.

[0028] A dummy gate layer DGL1 is disposed above and electrically connected to the lightly doped region LDD1 and the gate layer GL1. This allows for an increase in the doping concentration of the lightly doped region LDD1 while mitigating the impact on the breakdown voltage. Consequently, the high-voltage semiconductor device (such as the high-voltage semiconductor device HV1 in Figure 1A or the high-voltage semiconductor device HV2 or HV3 in Figure 1B) containing the semiconductor structure 100 can simultaneously possess the desired drive voltage and breakdown voltage. The dummy gate layer DGL1 may comprise a conductive material, such as polysilicon. In some embodiments, the dummy gate layer DGL1 may be formed simultaneously with the gate layer GL1 in the same process. That is, the dummy gate layer DGL1 and the gate layer GL1 may be made of the same material.

[0029] In this embodiment, as shown in FIG2A, the dummy gate layer DGL1 can be electrically connected to the gate layer GL1 through direct contact. In this embodiment, the dummy gate layer DGL1 may include a first portion LP1 extending in a first direction D1 and a second portion VP1 extending in a second direction D2 different from the first direction D1. In some embodiments, the first direction D1 may be perpendicular to the second direction D2. The second portion VP1 may span over the active region AA1 and contact the gate layer GL1 through the first portion LP1. In this embodiment, the first portion LP1 may be disposed outside the active region AA1, thereby reducing the influence of the first portion LP1 of the dummy gate layer DGL1 on the lightly doped region LDD1 during the formation of the lightly doped region LDD1.

[0030] In this embodiment, the dummy gate layer DGL1 may include a plurality of first portions LP1 respectively disposed at opposite ends of the second portion VP1 in the second direction D2.

[0031] In some embodiments, the semiconductor structure 100 may include a gate insulating layer GI1 disposed between the gate layer GL1 and the substrate SUB1, and a dummy gate insulating layer DGI1 disposed between the dummy gate layer DGL1 and the substrate SUB1. The gate insulating layer GI1 may contain any material suitable as a gate dielectric layer, such as an oxide (e.g., silicon oxide). The dummy gate insulating layer DGI1 may contain any suitable insulating material. In some embodiments, the gate insulating layer GI1 and the dummy gate insulating layer DGI1 may be formed simultaneously in the same process. That is, the gate insulating layer GI1 and the dummy gate insulating layer DGI1 may be made of the same material.

[0032] In some embodiments, the semiconductor structure 100 may include a dielectric layer IL1 disposed on a substrate SUB1 and covering a gate layer GL1 and a dummy gate layer DGL1. The dielectric layer IL1 may include any suitable dielectric material such as an oxide (e.g., silicon oxide).

[0033] In some embodiments, the semiconductor structure 100 may include a drain conductive contact DCT1 disposed on and electrically connected to the drain region DR1, a source conductive contact SCT1 disposed on and electrically connected to the source region SR1, and a gate conductive contact GCT1 disposed on and electrically connected to the gate layer GL1. The drain conductive contact DCT1, the source conductive contact SCT1, and the gate conductive contact GCT1 may be disposed or embedded in the dielectric layer IL1 and may each include a suitable conductive material such as a metal or a metal alloy. The metal and metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof. In this embodiment, a dummy gate layer DGL1 may be disposed between the gate layer GL1 and the drain conductive contact DCT1, and between the gate layer GL1 and the source conductive contact SCT1.

[0034] In some embodiments, the semiconductor structure 100 may include a wiring layer ML1 disposed on a dielectric layer IL1. The wiring layer ML1 may include wiring electrically connected to a gate layer GL1 and wiring electrically connected to a drain conductive contact DCT1 and a source conductive contact SCT1. The wiring layer ML1 may include a suitable conductive material such as a metal or metal alloy. The metal and metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof.

[0035] Figure 3 shows a top view of the semiconductor structure according to the second embodiment of this disclosure. The semiconductor structure 200 shown in Figure 3 is similar to the semiconductor structure 100 shown in Figure 2A, the main difference being that the dummy gate layer DGL2 of the semiconductor structure 200 is different from the dummy gate layer DGL1 of the semiconductor structure 100. Other identical or similar elements are represented by the same or similar element symbols, and will not be described again here.

[0036] Referring to Figure 3, the dummy gate layer DGL2 of the semiconductor structure 200 may include a first portion LP2 extending in the first direction D1 and a second portion VP2 extending in the second direction D2 and spanning over the active region AA1. In this embodiment, the dummy gate layer DGL2 may include a plurality of second portions VP2 arranged in the first direction D1, wherein each second portion VP2 contacts the gate layer GL1 through the first portion LP1 to be electrically connected to the gate layer GL1. This helps to adjust the potential distribution in the lightly doped region LDD1, thereby increasing the doping concentration of the lightly doped region LDD1 while reducing the impact on the breakdown voltage, so that the high-voltage semiconductor device containing the semiconductor structure 200 (such as the high-voltage semiconductor device HV1 in Figure 1A or the high-voltage semiconductor device HV2 or HV3 shown in Figure 1B) can simultaneously have the desired drive voltage and breakdown voltage.

[0037] Figure 4 shows a top view of the semiconductor structure according to the third embodiment of this disclosure. The semiconductor structure 300 shown in Figure 4 is similar to the semiconductor structure 100 shown in Figure 2A, the main difference being that the dummy gate layer DGL3 of the semiconductor structure 300 is different from the dummy gate layer DGL1 of the semiconductor structure 100. Other identical or similar elements are represented by the same or similar element symbols, and will not be described again here.

[0038] Referring to Figure 4, the dummy gate layer DGL3 of the semiconductor structure 300 may include a first portion LP3 extending in the first direction D1 and a second portion VP3 extending in the second direction D2 and spanning over the active region AA1. In this embodiment, the dummy gate layer DGL3 may be disposed only between the gate layer GL1 and the drain conductive contact DCT1, which helps to reduce the horizontal area of ​​the semiconductor structure 300.

[0039] Figure 5 shows a top view of the semiconductor structure according to the fourth embodiment of this disclosure. The semiconductor structure 400 shown in Figure 5 is similar to the semiconductor structure 100 shown in Figure 2A, the main difference being that the dummy gate layer DGL4 of the semiconductor structure 400 is different from the dummy gate layer DGL1 of the semiconductor structure 100. Other identical or similar elements are represented by the same or similar element symbols, and will not be described again here.

[0040] Referring to Figure 5, the dummy gate layer DGL4 of the semiconductor structure 400 may include a first portion LP4 extending in the first direction D1 and a second portion VP4 extending in the second direction D2 and spanning over the active region AA1. In this embodiment, the first portion LP4 of the dummy gate layer DGL4 may be disposed only at one end of the second portion VP4 in the second direction D2.

[0041] Figure 6 shows a top view of the semiconductor structure according to the fifth embodiment of this disclosure. The semiconductor structure 500 shown in Figure 6 is similar to the semiconductor structure 300 shown in Figure 4, the main difference being that the dummy gate layer DGL5 of the semiconductor structure 500 is different from the dummy gate layer DGL3 of the semiconductor structure 300. Other identical or similar components are represented by the same or similar component symbols, and will not be described again here.

[0042] Referring to Figure 6, the dummy gate layer DGL5 of the semiconductor structure 500 may include a first portion LP5 extending in the first direction D1 and a second portion VP5 extending in the second direction D2 and spanning over the active region AA1. In this embodiment, the first portion LP5 of the dummy gate layer DGL5 may be disposed only at one end of the opposite ends of the second portion VP5 in the second direction D2.

[0043] Figure 7A shows a top view of the semiconductor structure according to the sixth embodiment of this disclosure. Figure 7B shows a top view of one embodiment of this disclosure taken along line A-A' of Figure 7A. Figure 7C shows a top view of another embodiment of this disclosure taken along line A-A' of Figure 7A. The semiconductor structure 600 shown in Figure 7A is similar to the semiconductor structure 100 shown in Figure 2A, the main difference being that the dummy gate layer DGL6 of the semiconductor structure 600 is different from the dummy gate layer DGL1 of the semiconductor structure 100. Other identical or similar elements are represented by the same or similar element symbols, and will not be described again here.

[0044] Referring to Figure 7A, the dummy gate layer DGL6 of the semiconductor structure 600 may consist only of a second portion VP6 extending in the second direction D2 and spanning over the active region AA1. In other words, the dummy gate layer DGL6 may be spaced apart from the gate layer GL1 in the first direction D1. In this embodiment, the wiring layer ML1 may be disposed above the gate layer GL1, and the dummy gate layer DGL6 may be electrically connected to the gate layer GL1 through the wiring layer ML1. In some embodiments, as shown in Figure 7B, the top surface of the dummy gate layer DGL6 may be in direct contact with the wiring layer ML1. In other embodiments, as shown in Figure 7C, the semiconductor structure 600 may include a conductive contact DGCT1 disposed on the dummy gate layer DGL6 and electrically connecting the dummy gate layer DGL6 to the wiring layer ML1. The conductive contact DGCT1 may be disposed or embedded in the dielectric layer IL1 and may include a suitable conductive material such as a metal or metal alloy. Metals and metal alloys may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof.

[0045] Figure 8A shows a three-dimensional schematic diagram of the semiconductor structure according to the seventh embodiment of this disclosure. Figure 8B shows a top view of an embodiment of this disclosure taken along line B-B' of Figure 8A. The semiconductor structure 700 shown in Figure 8A is similar to the semiconductor structure 100 shown in Figure 2A, the main difference being that the substrate SUB2 of the semiconductor structure 700 is different from the substrate SUB1 of the semiconductor structure 100. Therefore, the lightly doped region LDD2 formed in the active region AA2 of the substrate SUB2, and the gate insulating layer GI2, dummy gate insulating layer DGI2, gate layer GL2, and dummy gate layer DGL7 formed on the substrate SUB2 are different from the lightly doped region LDD1 formed in the active region AA1 of the substrate SUB1 of the semiconductor structure 100, and the gate insulating layer GI1, dummy gate insulating layer DGI1, gate layer GL1, and dummy gate layer DGL1 formed on the substrate SUB1. Other identical or similar elements are represented by the same or similar element symbols, and will not be repeated here.

[0046] Referring to Figure 8A, the substrate SUB2 may include a trench TCH1 with an active region AA2 formed thereon, wherein the gate layer GL2 and the dummy gate layer DGL7 may each include portions covering the bottom surface and sidewalls of the trench TCH1. A gate insulating layer GI2 may be disposed between the gate layer GL2 and the substrate SUB2, while the dummy gate insulating layer DGI2 may be disposed between the dummy gate layer DGL7 and the substrate SUB2. In this embodiment, the active region AA2 may include a source / drain region S / D and a lightly doped region LDD2 disposed between the source / drain region S / D and the gate layer GL2. The source / drain region S / D shown in Figure 8A may be electrically connected to a conductive contact S / D_CT, wherein the source / drain region S / D may correspond to the source region SR1 or drain region DR1 shown in Figure 2A, and the conductive contact S / D_CT may correspond to the source conductive contact SCT1 or drain conductive contact DCT1 shown in Figure 2A. In this embodiment, the lightly doped region LDD2 may include a side portion LDD2a formed on the sidewall of the trench TCH1 and a bottom portion LDD2b formed on the bottom surface of the trench TCH1.

[0047] In this embodiment, the dummy gate layer DGL7 can be disposed above the lightly doped region LDD2 and electrically connected to the gate layer GL2. This can increase the doping concentration of the lightly doped region LDD2 while mitigating the impact on the breakdown voltage, thereby enabling the high-voltage semiconductor device containing the semiconductor structure 700 (such as the high-voltage semiconductor device HV1 in Figure 1A or the high-voltage semiconductor device HV2 or HV3 in Figure 1B) to simultaneously possess the desired drive voltage and breakdown voltage. In other words, the semiconductor structure 700 can also be applied to semiconductor devices with trench architectures.

[0048] Figure 9A shows a three-dimensional schematic diagram of the semiconductor structure of the eighth embodiment of this disclosure. Figure 9B shows a top view of an embodiment of this disclosure taken along line C-C' of Figure 9A. The semiconductor structure 800 shown in Figure 9A is similar to the semiconductor structure 100 shown in Figure 2A. The main difference is that the substrate SUB3 of the semiconductor structure 800 is different from the substrate SUB1 of the semiconductor structure 100. Therefore, the lightly doped region LDD3 formed in the active fin AF of the substrate SUB3 and the gate insulating layer GI3, dummy gate insulating layer DGI3, gate layer GL3, and dummy gate layer DGL8 formed on the substrate SUB3 are different from the lightly doped region LDD1 formed in the active region AA1 of the substrate SUB1 of the semiconductor structure 100 and the gate insulating layer GI1, dummy gate insulating layer DGI1, gate layer GL1, and dummy gate layer DGL1 formed on the substrate SUB1. Other identical or similar elements are represented by the same or similar element symbols and will not be repeated here.

[0049] Referring to Figure 9A, the substrate SUB3 may include an active fin AF protruding from the top surface of the substrate SUB3 and having an active region therein. The gate layer GL3 and the dummy gate layer DGL8 may each include a portion of the top surface and sidewalls covering the active fin AF. A gate insulating layer GI3 may be disposed between the gate layer GL3 and the substrate SUB3, while the dummy gate insulating layer DGI3 may be disposed between the dummy gate layer DGL8 and the substrate SUB3. In this embodiment, the active fin AF may include a source / drain region S / D and a lightly doped region LDD3 disposed between the source / drain region S / D and the gate layer GL3. The source / drain region S / D shown in Figure 9A may be electrically connected to a conductive contact S / D_CT, where the source / drain region S / D may correspond to the source region SR1 or drain region DR1 shown in Figure 2A, and the conductive contact S / D_CT may correspond to the source conductive contact SCT1 or drain conductive contact DCT1 shown in Figure 2A. In this embodiment, the lightly doped region LDD3 may be formed in the active fin AF. In some embodiments, the semiconductor structure 800 may include an isolation structure IS formed on the substrate SUB3. The isolation structure IS may include any suitable insulating material such as an oxide (e.g., silicon oxide).

[0050] In this embodiment, the dummy gate layer DGL8 can be disposed above the lightly doped region LDD3 and electrically connected to the gate layer GL3. This can increase the doping concentration of the lightly doped region LDD3 while mitigating the impact on the breakdown voltage, thereby enabling the high-voltage semiconductor device containing the semiconductor structure 800 (such as the high-voltage semiconductor device HV1 in Figure 1A or the high-voltage semiconductor device HV2 or HV3 in Figure 1B) to simultaneously possess the desired drive voltage and breakdown voltage. In other words, the semiconductor structure 800 can also be applied to semiconductor devices with fin-type architectures.

[0051] In some embodiments, the semiconductor structure (e.g., 100, 200, 400, 600, 700, 800) may include a substrate (e.g., SUB1, SUB2, SUB3), a gate layer (e.g., GL1, GL2, GL3), and multiple dummy gate layers (e.g., DGL1, DGL2, DGL4, DGL6, DGL7, DGL8). The substrate may include an active region (e.g., AA1, AA2, AA3) and a first source / drain region (e.g., one of drain region DR1 and source region SR1 or source / drain region S / D) disposed in the active region, a second source / drain region (e.g., the other of drain region DR1 and source region SR1 or source / drain region S / D), and multiple lightly doped regions (e.g., LDD1, LDD2, LDD3). The gate layer can be disposed above the active region, wherein the first source / drain region and the second source / drain region can be disposed on opposite sides of the gate layer in a first direction (e.g., D1), and multiple lightly doped regions can be disposed between the gate layer and the first source / drain region and between the gate layer and the second source / drain region, respectively. Multiple dummy gate layers can be disposed above multiple lightly doped regions of the substrate and electrically connected to the gate layer.

[0052] In some embodiments, a plurality of dummy gate layers (e.g., DGL1, DGL2, DGL4, DGL6, DGL7, DGL8) may be in direct contact with a gate layer (e.g., GL1, GL2, GL3). In some embodiments, each dummy gate layer (e.g., DGL1, DGL2, DGL4, DGL7, DGL8) may include at least one first portion (e.g., LP1, LP2, LP4) extending in a first direction (e.g., D1) and at least one second portion (e.g., VP1, VP2, VP4) extending in a second direction different from the first direction (e.g., D2). The second portion may span over the active region and contact the gate layer through the first portion.

[0053] In some embodiments, each dummy gate layer (e.g., DGL1, DGL2, DGL7, DGL8) may include a plurality of first portions (e.g., LP1, LP2) respectively disposed at opposite ends of the second portions (e.g., VP1, VP2) in a second direction (e.g., D2). In some embodiments, each dummy gate layer (e.g., DGL2) may include a plurality of second portions (e.g., VP2) arranged in a first direction (e.g., D1).

[0054] In some embodiments, the semiconductor structure (e.g., 100, 200, 300, 400, 500, 600, 700, 800) may include a substrate (e.g., SUB1, SUB2, SUB3), a gate structure, and a dummy gate structure. The substrate may include an active region (e.g., AA1, AA2, AA3) and a source region (e.g., SR1 or S / D), a drain region (e.g., DR1 or S / D), and at least one lightly doped region (e.g., LDD1, LDD2, LDD3) disposed within the active region, wherein the lightly doped region may be disposed between the source and drain regions in a first direction (e.g., D1). The gate structure may be disposed on the active region and may include a gate layer (e.g., GL1, GL2, GL3) and a gate insulating layer (e.g., GI1, GI2, GI3) between the gate layer and the substrate, wherein the source and drain regions may be disposed on opposite sides of the gate layer in the first direction, and the lightly doped region is disposed between the gate layer and the drain region. The dummy gate structure can be disposed on a lightly doped region and may include a dummy gate layer (e.g., DGL1, DGL2, DGL3, DGL4, DGL5, DGL6, DGL7, DGL8) and a dummy gate insulating layer (e.g., DGI1, DGI2, DGI3) between the dummy gate layer and the substrate, wherein the dummy gate layer is electrically connected to the gate layer.

[0055] In this embodiment, the semiconductor structure may include a dielectric layer (e.g., ILD1), drain conductive contacts (e.g., DCT1, S / D_CT), and a wiring layer (e.g., ML1). The dielectric layer may be disposed on a substrate (e.g., SUB1) and may cover the gate structure and the dummy gate structure. The drain conductive contacts may be embedded in the dielectric layer and electrically connected to the drain region, wherein the dummy gate structure may be disposed between the gate structure and the drain conductive contacts. The wiring layer may be disposed on the dielectric layer and may be electrically connected to the gate layer, wherein the dummy gate layer may be directly electrically connected to the gate layer or may be electrically connected to the gate layer through the wiring layer.

[0056] In summary, in the semiconductor structure of the above embodiments, the dummy gate layer is configured above the lightly doped region and electrically connected to the gate layer. This can reduce the impact on the breakdown voltage while increasing the doping concentration of the lightly doped region, thereby enabling the high-voltage semiconductor device containing this semiconductor structure to simultaneously have the desired drive voltage and breakdown voltage.

[0057] 10: Block 11, 12, 13: String 100, 200, 300, 400, 500, 600, 700, 800: Semiconductor Structure AA1, AA2, AA3: Active Zone AF: Active fin BL1, BL2, BL3: Bit lines CSL: Common Source Line D1: First Direction D2: Second Direction DCT1: Drain conductive contact DGL1, DGL2, DGL3, DGL4, DGL5, DGL6, DGL7, DGL8: Dummy gate layers DGCT1: Conductive contact DGI1, DGI2, DGI3: Dummy gate insulation layer DR1: Drain Zone GCT1: Gate conductive contact GL1, GL2, GL3: Gate layers GI1, GI2, GI3: Gate insulation layer GSL: Grounding Selection Line HV1, HV2, HV3: High-voltage semiconductor components IL1: Dielectric layer IS: Isolation Structure LDD1, LDD2, LDD3: Lightly doped regions LDD2a: Side portion LDD2b: Bottom part LP1, LP2, LP3, LP4, LP5: Part 1 M0, M1, M2: Memory Cells ML1: Wiring layer S / D: Source / Drain Region S / D_CT: Conductive Contact SCT1: Source conductive contact SUB1, SUB2, SUB3: Base SR1: Source Region SSL0~SSL3: Serial select lines Sub0~Sub3: Sub-blocks TCH1: Ditch VP1, VP2, VP3, VP4, VP5, VP6: Part Two WL1, WLm, WLj: Character lines X, Y, Z: Direction

Claims

1. A semiconductor structure, comprising: The substrate includes an active region and a source region, a drain region, and at least one lightly doped region disposed in the active region; A gate layer is disposed above the active region, wherein the source region and the drain region are disposed on opposite sides of the gate layer in a first direction and the lightly doped region is disposed between the gate layer and the drain region; a dummy gate layer is disposed above the lightly doped region and electrically connected to the gate layer; and a drain conductive contact is disposed on the drain region, wherein the dummy gate layer is disposed between the gate layer and the drain conductive contact.

2. The semiconductor structure as claimed in claim 1, wherein the dummy gate layer is in direct contact with the gate layer.

3. The semiconductor structure of claim 2, wherein the dummy gate layer includes at least a first portion extending in the first direction and at least a second portion extending in a second direction other than the first direction, the second portion extending over the active region and contacting the gate layer through the first portion.

4. The semiconductor structure as claimed in claim 3, wherein the first portion is disposed outside the active region.

5. The semiconductor structure as claimed in claim 3, wherein the dummy gate layer comprises a plurality of the first portions respectively disposed at opposite ends of the second portion in the second direction.

6. The semiconductor structure as claimed in claim 3, wherein the dummy gate layer comprises a plurality of second portions arranged in the first direction.

7. The semiconductor structure as described in claim 1, further comprising: A wiring layer is disposed above the gate layer, and the dummy gate layer is electrically connected to the gate layer through the wiring layer.

8. The semiconductor structure as claimed in claim 7, wherein the top surface of the dummy gate layer is in direct contact with the wiring layer.

9. The semiconductor structure as described in claim 8, further comprising: A conductive contact is disposed on the dummy gate layer and electrically connects the dummy gate layer to the wiring layer.

10. The semiconductor structure of claim 7, wherein the dummy gate layer is spaced apart from the gate layer in the first direction.

11. The semiconductor structure of claim 1, wherein the substrate includes a trench in which the active region is formed, the gate layer and the dummy gate layer each include a portion covering the bottom surface and sidewall of the trench, and the lightly doped region includes a side portion formed at the sidewall of the trench and a bottom portion formed at the bottom surface of the trench.

12. The semiconductor structure of claim 1, wherein the substrate includes an active fin projecting from the top surface of the substrate and wherein the active region is formed therein, the gate layer and the dummy gate layer each include a portion of the top surface and sidewalls covering the active fin, and the lightly doped region is formed in the active fin.

13. A semiconductor structure comprising: The substrate includes an active region and a first source / drain region, a second source / drain region, and a plurality of lightly doped regions disposed in the active region; A gate layer is disposed above the active region, wherein the first source / drain region and the second source / drain region are disposed on opposite sides of the gate layer in a first direction, and a plurality of lightly doped regions are respectively disposed between the gate layer and the first source / drain region and between the gate layer and the second source / drain region; and a plurality of dummy gate layers are respectively disposed above the plurality of lightly doped regions of the substrate and electrically connected to the gate layer, wherein the plurality of dummy gate layers are in direct contact with the gate layer.

14. The semiconductor structure of claim 13, wherein each of the dummy gate layers includes at least a first portion extending in the first direction and at least a second portion extending in a second direction other than the first direction, the second portion extending over the active region and contacting the gate layer through the first portion.

15. The semiconductor structure of claim 14, wherein each of the dummy gate layers includes a plurality of first portions disposed at opposite ends of the second portion in the second direction.

16. The semiconductor structure of claim 14, wherein each of the dummy gate layers includes a plurality of second portions arranged in the first direction.

17. A semiconductor structure comprising: A substrate includes an active region and a source region, a drain region, and at least one lightly doped region disposed in the active region, wherein the lightly doped region is disposed between the source region and the drain region in a first direction; a gate structure is disposed on the active region and includes a gate layer and a gate insulating layer between the gate layer and the substrate, wherein the source region and the drain region are disposed on opposite sides of the gate layer in the first direction and the lightly doped region is disposed between the gate layer and the drain region; and a dummy gate structure is disposed on the lightly doped region and includes a dummy gate layer and a dummy gate insulating layer between the dummy gate layer and the substrate, wherein the dummy gate layer is electrically connected to the gate layer.

18. The semiconductor structure as described in claim 17, further comprising: A dielectric layer disposed on the substrate and covering the gate structure and the dummy gate structure; a drain conductive contact embedded in the dielectric layer and electrically connected to the drain region, wherein the dummy gate structure is disposed between the gate structure and the drain conductive contact; and a wiring layer disposed on the dielectric layer and electrically connected to the gate layer, wherein the dummy gate layer is directly electrically connected to the gate layer or electrically connected to the gate layer through the wiring layer.

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