Display device and manufacturing method of active device substrate

Abstract

A display device includes a substrate, a light shielding layer, a buffer layer, a semiconductor layer, an insulating layer, a first conductive layer, a second conductive layer, a first source electrode and a first drain electrode. The substrate has a display area and a peripheral area outside the display area. The display area has a first active device area, and the peripheral area has a calibration mark area. The buffer layer is disposed on the substrate and extends from the first active device area to the calibration mark area. The semiconductor layer is disposed on the buffer layer and is located in the first active device area. The insulating layer is disposed on the semiconductor layer and covers the first active device area and the calibration mark area. The first conductive layer is disposed on the insulating layer and has a first alignment component located on the calibration mark area. The second conductive layer is disposed on the insulating layer and has a second alignment component located on the calibration mark area. The second alignment component is located around the first alignment component.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a display device and an active element substrate. Prior Technology

[0002] In many display devices, thin-film transistors (TFTs) are used for signal processing. These TFTs may be located in driving circuits or pixel structures. Generally, electrode and semiconductor material layers are deposited using thin-film deposition technology, and these electrode and semiconductor material layers are then patterned to obtain the electrodes and semiconductor layers in the TFT. Typically, photoresist patterns are used as masks for patterning. However, during the fabrication of the photoresist pattern, alignment issues may cause the formed photoresist pattern to deviate from its intended position, increasing the variation in the channel length of the TFT and thus affecting its yield. Summary of the Invention

[0003] At least one embodiment of the present invention provides a method for manufacturing an active element substrate, comprising the following steps: Providing a substrate having a display area and a peripheral area outside the display area; the display area having at least one sub-pixel area, wherein the sub-pixel area has a first active element area, and the peripheral area has at least one calibration mark area; forming a light-shielding layer on the substrate, the light-shielding layer having a first light-shielding portion located in the first active element area; forming a buffer layer on the substrate and covering the first light-shielding portion; forming a semiconductor layer on the buffer layer of the substrate, the semiconductor layer having a first semiconductor portion located in the first active element area; forming an insulating layer on the buffer layer and the semiconductor layer and covering the first active element area and the at least one calibration mark area; forming a first conductive layer on the insulating layer... The first active element region and the at least one calibration mark region are covered; a first photoresist pattern is formed on the first conductive layer, wherein the first photoresist pattern has a first sub-photoresist portion and a second sub-photoresist portion respectively located on the first active element region and the at least one calibration mark region; the first conductive layer is etched using the first photoresist pattern as an etching mask to form a first alignment member on the at least one calibration mark region and a first gate portion on the first active element region; the first gate portion and the first sub-photoresist portion located on the first active element region are used as doping masks, and an ion implantation process is performed on the semiconductor layer outside the doping mask to form an ion implantation process in the first semiconductor portion of the first active element region. A first doped region and a first undoped region are formed, and the first photoresist pattern is removed; a second conductive layer is formed on the insulating layer, the first alignment member, and the first gate portion, covering the first active element region and the at least one calibration mark region; a second photoresist pattern is formed on the second conductive layer, wherein the second photoresist pattern has a third sub-photoresist portion and a fourth sub-photoresist portion respectively located on the first active element region and the at least one calibration mark region, the third sub-photoresist portion covers a portion of the second conductive layer on the first active element region and its overlap with a portion of the first gate portion, and the fourth sub-photoresist portion has an opening to expose a portion of the second conductive layer of the at least one calibration mark region; the second photoresist pattern is then formed. The second conductive layer is etched using an etching mask to form a second alignment member on the at least one correction mark region and a second gate portion on the first active element region, exposing a portion of the first undoped region and a portion of the first doped region. The second alignment member is located around the first alignment member, and a portion of the second gate portion overlaps with the first gate portion and the first doped region. Using the second gate portion and the third sub-photoresist portion located in the first active element region as a heavily doped mask, a heavy doping process is performed on the semiconductor layer outside the heavily doped mask to form two first heavily doped regions in a portion of the first doped region and a portion of the first undoped region in the first active element region, and these first heavily doped regions are separated from each other.An etch-back process is performed on the second gate portion and the first gate portion to reduce their widths and expose a portion of the first doped region and a portion of the first undoped region located in the first active device region, and the second photoresist pattern is removed; using the second gate portion located in the first active device region as a lightly doped mask, a light doping process is performed on the semiconductor layer outside the lightly doped mask to form a first lightly doped region in the portion of the first undoped region in the first active device region; and a first source and a first drain are formed on the insulating layer to be electrically connected to the first heavily doped regions in the first active device region, respectively.

[0004] At least one embodiment of the present invention provides a display device, comprising a substrate having a display area and a peripheral area outside the display area, the display area having at least one sub-pixel area, wherein the sub-pixel area has a first active element area, and the peripheral area has at least one correction mark area; a light-shielding layer disposed on the substrate, having a first light-shielding portion located in the first active element area; a buffer layer disposed on the substrate and covering the first light-shielding portion; a semiconductor layer disposed on the buffer layer of the substrate, having a first semiconductor portion located in the first active element area, wherein the first semiconductor portion has a first doped region, a first undoped region, a first lightly doped region, and two first heavily doped regions, the first doped region and the first undoped region being located between the first lightly doped regions and the first heavily doped regions, and the first doped region being located between the first undoped region and the first lightly doped regions. Between one of the heavily doped regions, the first lightly doped region is located between the first undoped region and the other of the first heavily doped regions; an insulating layer is disposed on the buffer layer and the semiconductor layer and covers the first active element region and the at least one correction mark region; a first conductive layer is disposed on the insulating layer and has a first alignment member located on the at least one correction mark region and a first gate portion located on the first active element region, wherein the first gate portion overlaps with the first undoped region; a second conductive layer is disposed on the insulating layer and has a second alignment member located on the at least one correction mark region and a second gate portion located on the first active element region, wherein the second alignment member is located around the first alignment member, and a portion of the second gate portion overlaps with the first gate portion and the first doped region, wherein the first gate portion and the second gate portion constitute a first gate; And a first source and a first drain, disposed on the insulating layer and electrically connected to the first heavily doped regions of the first active element region. Simple Explanation of the Diagram

[0005] Figure 1 is a top view schematic diagram of a display device according to an embodiment of the present invention. Figure 2 is a cross-sectional schematic diagram of a display device according to an embodiment of the present invention. Figures 3A to 3O are cross-sectional schematic diagrams of the various stages of manufacturing the display device of Figure 2. Figure 4A is a top view of the correction mark area according to an embodiment of the present invention. Figure 4B is a top view of the correction mark area according to another embodiment of the present invention. Figure 5A is a cross-sectional view of the correction mark area in Figure 4A. Figure 5B is a cross-sectional view of the correction mark area in Figure 4B. Figure 6 shows the overlay distribution of the first gate portion and the second gate portion after the first alignment member is installed. Figure 7 shows the IV curves of the thin-film transistor fabricated according to an embodiment of the present invention at different voltages. Implementation

[0006] Figure 1 is a top view schematic diagram of a display device according to an embodiment of the present invention. Referring to Figure 1, the substrate 100 of the display device has a display area AA and a peripheral area PA surrounding the display area AA. The shape of the display area AA can be adjusted as needed, for example, rectangular, circular, elliptical or other suitable shapes.

[0007] The display area AA is provided with an array of pixel structures, each pixel structure containing active elements (e.g., thin-film transistors), passive elements (e.g., capacitors), and other suitable elements. In some embodiments, the pixel structure also includes a display unit, such as a micro light-emitting diode, an organic light-emitting diode, a liquid crystal medium, an electrophoretic medium, or other suitable elements.

[0008] The peripheral area PA is provided with various circuit structures, such as those for providing signals to the pixel structures on the display area AA. In this embodiment, the peripheral area PA includes a correction mark area MR. The correction mark area MR is provided with marks used to detect / correct the exposure process during the manufacturing of the display device. The correction mark area MR can be located at any position in the peripheral area PA. In this embodiment, the correction mark area MR is located at the four corners of the peripheral area PA, but the invention is not limited thereto. In other embodiments, the correction mark area MR may also be located at other positions.

[0009] Figure 2 is a schematic cross-sectional view of a display device according to an embodiment of the present invention. Figure 2 shows a portion of the display area AA and the peripheral area PA of Figure 1. Referring to Figure 2, the display device 10 includes a substrate 100, a light-shielding layer 110, a buffer layer 120, a semiconductor layer 130, an insulating layer 140, a first conductive layer 150, a second conductive layer 160, an interlayer dielectric layer 170, a first source electrode 182, a first drain electrode 184, a second source electrode 186, a second drain electrode 188, and a display unit 190.

[0010] The substrate 100 has a display area AA and a peripheral area PA located outside the display area AA. The display area AA has at least one sub-pixel area PXL, wherein the sub-pixel area PXL has a first active element area TR, a second active element area DG, and a capacitor area CR. The peripheral area PA has at least one correction mark area MR.

[0011] The first active element region TR includes a thin-film transistor, particularly a protrusion gate channel bridge thin-film transistor (PGCB TFT). The thin-film transistor includes a first light-shielding portion 112, a first semiconductor portion 132, a first gate portion 154, a second gate portion 164, a first source 182, and a first drain 184.

[0012] The second active element region (DG) includes a double-gate transistor structure. The double-gate transistor structure includes a second light-shielding section 114, a second semiconductor section 134, a third gate section 156, a fourth gate section 166, a second source 186, and a second drain 188.

[0013] The capacitor region CR includes a capacitor. The capacitor includes a third light-shielding part 116, a third semiconductor part 136, and an electrode 168.

[0014] The calibration marking area MR includes a first alignment member 152 and a second alignment member 162.

[0015] In some embodiments, the structure of the sub-pixel region PXL can be represented by nTmC, where T is the number of transistors in the sub-pixel region PXL, C is the number of capacitors in the sub-pixel region PXL, and n and m are positive integers, with n > m. Therefore, there can be many different combinations of the number of transistors and capacitors in the sub-pixel region PXL, such as 2T1C / 3T1C / 4T1C / 5T1C / 6T1C / 4T2C / 5T2C / 6T2C / 7T2C / 7T1C, etc., and this disclosure is not limited thereto. In this embodiment, the sub-pixel region PXL has a 2T1C architecture. 2T represents that the sub-pixel region PXL has two transistors, or two active elements, namely a thin-film transistor in the first active element region TR, serving as a driving element or an emitting controller, and a dual-gate transistor in the second active element region DG, serving as a switching element. 1C represents that the sub-pixel region PXL has one capacitor, namely the capacitor in the capacitor region CR.

[0016] Please refer to Figure 2. As shown in Figure 2, a light-shielding layer 110 is disposed on the substrate 100, and has a first light-shielding portion 112 located in the first active element region TR, a second light-shielding portion 114 located in the second active element region DG, and a third light-shielding portion 116 located in the capacitor region CR. In this embodiment, the first light-shielding portion 112, the second light-shielding portion 114, and the third light-shielding portion 116 are separated from each other, but the present invention is not limited thereto. In other embodiments, any two or more of the first light-shielding portion 112, the second light-shielding portion 114, and the third light-shielding portion 116 are connected to each other.

[0017] A buffer layer 120 is disposed on the substrate 100 and extends from the first active element region TR to the capacitor region CR and the second active element region DG, and extends to the calibration mark region MR. The buffer layer 120 covers the first light-shielding portion 112, the second light-shielding portion 114, and the third light-shielding portion 116. Specifically, in this embodiment, the buffer layer 120 covers the top surface of the first light-shielding portion 112, the top surface of the second light-shielding portion 114, and the top surface of the third light-shielding portion 116. In other words, the first light-shielding portion 112, the second light-shielding portion 114, and the third light-shielding portion 116 are located between the buffer layer 120 and the substrate 100.

[0018] Semiconductor layer 130 is disposed on buffer layer 120 of substrate 100, and has a first semiconductor portion 132 located in first active element region TR, a second semiconductor portion 134 located in second active element region DG, and a third semiconductor portion 136 located in capacitor region CR.

[0019] In the first active element region TR, the first semiconductor section 132 has a first doped region 132A, a first undoped region 132B, a first lightly doped region 132D, and two first heavily doped regions 132C. The first doped region 132A and the first undoped region 132B are located between the first heavily doped region 132C and the first lightly doped region 132D. The first doped region 132A is located between one of the first undoped region 132B and the first heavily doped region 132C, and the first lightly doped region 132D is located between the other of the first undoped region 132B and the first heavily doped region 132C. The first undoped region 132B, also known as the channel region, has a low doping concentration (or is undoped) and the highest resistivity. The first heavily doped region 132C has a high doping concentration and the lowest resistivity. The doping concentration of the first lightly doped region 132D is lower than that of the first heavily doped region 132C, and the resistivity of the first lightly doped region 132D is higher than that of the first heavily doped region 132C. In addition, in some embodiments, the doping concentrations of the two first heavily doped regions 132C may be the same or different.

[0020] In the second active element region DG, the second semiconductor section 134 has a second undoped region 134B, two second lightly doped regions 134C, and two second heavily doped regions 134A. The second undoped region 134B and the second lightly doped region 134C are located between the second heavily doped region 134A. One of the second lightly doped regions 134C is located between one of the second undoped region 134B and the second heavily doped region 134A, and the other lightly doped region 134C is located between the other of the second undoped region 134B and the second heavily doped region 134A. The second undoped region 134B has a lower doping concentration (or is undoped) and the highest resistivity. The second heavily doped region 134A has a higher doping concentration and the lowest resistivity. The doping concentration of the second lightly doped region 134C is lower than that of the second heavily doped region 134A, and the resistivity of the second lightly doped region 134C is higher than that of the second heavily doped region 134A. In some embodiments, the doping concentrations of the two second heavily doped regions 134A may be the same or different. In some embodiments, the doping concentrations of the two second lightly doped regions 134C may be the same or different. Furthermore, the doping concentration of the first heavily doped region 132C is approximately the same as that of the second heavily doped region 134A, and both have similar resistivity. [ ]

[0021] In the capacitor region CR, the third semiconductor portion 136 has a first doped region 132A. In some embodiments, the first doped region extends from the first semiconductor portion 132 to the third semiconductor portion. In other embodiments, the first doped region 132A of the first semiconductor portion 132 and the first doped region 132A of the third semiconductor portion 136 are not connected to each other.

[0022] An insulating layer 140 is disposed on the buffer layer 120 and the semiconductor layer 130 and covers the first active element region TR, the second active element region DG, the capacitor region CR, and at least one calibration mark region MR.

[0023] A first conductive layer 150 is disposed on an insulating layer 140 and has a first alignment member 152 located on at least one calibration mark region MR, a first gate portion 154 located on a first active element region TR, and a third gate portion 156 located on a second active element region DG. In the first active element region TR, the first gate portion 154 overlaps with a first undoped region 132B. In the second active element region DG, the third gate portion 156 overlaps with a second undoped region 134B.

[0024] A second conductive layer 160 is disposed on the insulating layer 140, and has a second alignment member 162 located on at least one calibration mark region MR, a second gate portion 164 located on a first active element region TR, a fourth gate portion 166 located on a second active element region DG, and an electrode 168 located on a capacitor region CR. In the calibration mark region MR, the second alignment member 162 is located around the first alignment member 152.

[0025] The second alignment member 162 partially overlaps with the first alignment member 152, and a through hole V is present at the overlap of the second alignment member 162 and the first alignment member 152. For example, both the first alignment member 152 and the second alignment member 162 have through holes V and overlap. In other words, the through hole wall of the second alignment member 162 overlaps with and is connected to the through hole wall of the first alignment member 152. In some embodiments, at least one of the first alignment member 152 and the second alignment member 162 has a through hole V. In this embodiment, both the first alignment member 152 and the second alignment member 162 have through holes V. In other embodiments, only the second alignment member 162 may have a through hole V, while the first alignment member 152 may not have a through hole V, or only the first alignment member 152 may have a through hole V, while the second alignment member 162 may not have a through hole V.

[0026] In some embodiments, either the first alignment member 152 or the second alignment member 162 may be open (i.e., the top view of the first alignment member 152 and the second alignment member 162 may have gaps or breaks) or non-open (i.e., the top view of the first alignment member 152 and the second alignment member 162 is complete without gaps or breaks).

[0027] In the first active element region TR, a portion of the second gate portion 164 overlaps with the first gate portion 154 and the first doped region 132A. The first gate portion 154 and the second gate portion 164 constitute the first gate.

[0028] In the second active element region DG, the fourth gate portion 166 and the third gate portion 156 overlap with the second undoped region 134B.

[0029] In the capacitor region CR, electrode 168 overlaps with part of the first doped region 132A.

[0030] The interlayer dielectric layer 170 is located on the second alignment member 162, the second gate portion 164, the fourth gate portion 166, the electrode 168 and the insulating layer 140, and covers the second alignment member 162, the second gate portion 164, the fourth gate portion 166, the electrode 168 and the insulating layer 140.

[0031] In the first active element region TR, a first source 182 and a first drain 184 are disposed on the interlayer dielectric layer 170 to be electrically connected to the first heavily doped region 132C of the first active element region TR, respectively. In this embodiment, the first source 182 and the first drain 184 are located on the interlayer dielectric layer 170 and are connected to the first heavily doped region 132C of the first semiconductor portion 132 through vias in the interlayer dielectric layer 170 and the insulating layer 140.

[0032] In the second active device region DG, the second source 186 and the second drain 188 are on the interlayer dielectric layer 170 and are electrically connected to the second heavily doped region 134A of the second active device region DG, respectively. In this embodiment, the second source 186 and the second drain 188 are located on the interlayer dielectric layer 170 and are connected to the second heavily doped region 134A of the second semiconductor portion 134 through vias in the interlayer dielectric layer 170 and the insulating layer 140.

[0033] A self-emissive element 190 is disposed on the substrate 100 and electrically connected to the first drain 184 or the first source 182 on the first active element region TR. In some embodiments, the self-emissive element 190 is, for example, a micro light-emitting diode, an organic light-emitting diode, a liquid crystal medium, an electrophoretic display medium, or other suitable elements.

[0034] As shown in Figure 2, the first light-shielding portion 112, buffer layer 120, first semiconductor portion 132, insulating layer 140, first gate portion 154, second gate portion 164, first source 182, and first drain 184 on the first active element region TR constitute a first active element, and the first gate portion 154 and the second gate portion 164 constitute a first gate. In this embodiment, the first gate has two heights: the height of the second gate portion 164, which is the height of the second conductive layer 160, and the sum of the heights of the first gate portion 154 and the second gate portion 164, which is the sum of the heights of the first conductive layer 150 and the second conductive layer 160.

[0035] As shown in Figure 2, the second light-shielding portion 114, buffer layer 120, second semiconductor portion 134, insulating layer 140, third gate portion 156, fourth gate portion 166, second source 186, and second drain 188 on the second active element region DG constitute a second active element, and the third gate portion 156 and the fourth gate portion 166 constitute a second gate. In this embodiment, the height of the second gate is the sum of the height of the third gate portion 156 and the height of the fourth gate portion 166, that is, the sum of the height of the first conductive layer 150 and the height of the second conductive layer 160.

[0036] As shown in Figure 2, the third light-shielding portion 116, buffer layer 120, third semiconductor portion 136, insulating layer 140, and electrode 168 on the capacitor region CR constitute a capacitor. In this embodiment, the height of electrode 168 is the same as the height of the second conductive layer 160.

[0037] Figures 3A to 3O are cross-sectional schematic diagrams of the various stages of manufacturing the display device of Figure 2.

[0038] Please refer to Figure 3A. A substrate 100 is provided, which has a display area AA and a peripheral area PA located outside the display area AA. The display area AA has at least one sub-pixel area PXL, wherein the sub-pixel area PXL has a first active element area TR, and the peripheral area PA has at least one correction mark area MR.

[0039] In some embodiments, the substrate 100 is, for example, a rigid substrate, and its material may be glass, quartz, organic polymer, or opaque / reflective material (e.g., conductive material, metal, wafer, ceramic, or other suitable material) or other suitable material. However, the invention is not limited thereto, and in other embodiments, the substrate 100 may also be a flexible substrate or a stretchable substrate. For example, the materials of flexible substrates and stretchable substrates include polyimide (PI), polydimethylsiloxane (PDMS), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyurethane (PU), or other suitable materials.

[0040] In the embodiment of FIG3A, a buffer layer 120 is formed on the substrate 100 and covers a first light-shielding portion 112 located in the first active element region TR, a second light-shielding portion 114 located in the second active element region DG, a third light-shielding portion 116 located in the capacitor region CR, and at least one correction mark region MR.

[0041] In some embodiments, at least one of the first light-shielding portion 112, the second light-shielding portion 114, and the third light-shielding portion 116 may be a single layer or multiple layers, and the material may include metals such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, and nickel, the aforementioned alloys, the aforementioned metal oxides, the aforementioned metal nitrides, or combinations thereof, or other conductive materials. In some embodiments, the first light-shielding portion 112, the second light-shielding portion 114, and the third light-shielding portion 116 may be transparent materials, reflective materials, light-absorbing (blackening) materials, or other suitable materials. In some embodiments, if the first light-shielding portion 112, the second light-shielding portion 114, and the third light-shielding portion 116 are multiple layers, the materials may be the same or different materials. In some embodiments, when the first light-shielding portion 112, the second light-shielding portion 114, and the third light-shielding portion 116 are made of reflective materials or a combination of reflective and transparent materials, they can serve not only to block light from the outer surface of the substrate 100 from entering the semiconductor layer 130, but also as bottom gates for the first active element region TR and / or the second active element region DG. In some embodiments, the method of forming the first light-shielding portion 112, the second light-shielding portion 114, and the third light-shielding portion 116 includes: first, forming a conductive material layer on the substrate 100; then, patterning the aforementioned conductive material layer to form the first light-shielding portion 112, the second light-shielding portion 114, and the third light-shielding portion 116. In some embodiments, the method of forming the conductive material layer includes sputtering, electroplating, electroless plating, physical vapor deposition, chemical vapor deposition, or other suitable processes.

[0042] In the embodiment shown in FIG3A, the first light-shielding portion 112, the second light-shielding portion 114, and the third light-shielding portion 116 directly contact the substrate 100, but the present invention is not limited thereto. In other embodiments, a buffer layer is first formed on the substrate 100, and then the first light-shielding portion 112, the second light-shielding portion 114, and the third light-shielding portion 116 are formed on the buffer layer.

[0043] In some embodiments, the buffer layer 120 has a single-layer or multi-layer structure, and the material includes silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, hafnium oxide, aluminum oxide, organic insulating materials, other suitable materials, or combinations thereof. In some embodiments, the multi-layer structure of the buffer layer 120 may be made of the same material or different materials. In some embodiments, the method of forming the buffer layer 120 includes physical vapor deposition, chemical vapor deposition, atomic layer deposition, coating, or other suitable processes. In some embodiments, the thickness of the buffer layer 120 is 500 angstroms to 10,000 angstroms.

[0044] In the embodiment of FIG3A, a semiconductor layer 130 is formed on the buffer layer 120 of the substrate 100, and the semiconductor layer 130 has a first semiconductor portion 132 located in the first active element region TR, a second semiconductor portion 134 located in the second active element region DG, and a third semiconductor portion 136 located in the capacitor region CR. The semiconductor layer 130 does not extend to the correction mark region MR.

[0045] The first semiconductor portion 132, the second semiconductor portion 134, and the third semiconductor portion 136 of the semiconductor layer 130 have the same material. In some embodiments, the first semiconductor portion 132, the second semiconductor portion 134, and the third semiconductor portion 136 are each a single-layer or multi-layer structure, comprising a silicon-containing semiconductor material, such as amorphous silicon, polycrystalline silicon, microcrystalline silicon, monocrystalline silicon, oxide semiconductor materials (e.g., indium zinc oxide, indium gallium zinc oxide, or other suitable materials, or combinations thereof), or other suitable materials or combinations thereof. In some embodiments, polycrystalline silicon is preferred. In some embodiments, the method of forming the first semiconductor portion 132, the second semiconductor portion 134, and the third semiconductor portion 136 of the semiconductor layer 130 includes: first, forming the semiconductor layer 130 on the buffer layer 120; then, patterning the aforementioned semiconductor layer 130 to form the first semiconductor portion 132, the second semiconductor portion 134, and the third semiconductor portion 136.

[0046] In the embodiment of FIG3A, an insulating layer 140 is formed on the buffer layer 120 and the semiconductor layer 130 and covers the first active element region TR, the second active element region DG, the capacitor region CR and at least one correction mark region MR.

[0047] In some embodiments, the insulating layer 140 has a single-layer or multi-layer structure, and its material includes silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, hafnium oxide, aluminum oxide, organic insulating materials, other suitable materials, or combinations thereof. In some embodiments, the multi-layer structure of the insulating layer 140 may be made of the same material or different materials. In some embodiments, the method of forming the insulating layer 140 includes physical vapor deposition, chemical vapor deposition, atomic layer deposition, coating, or other suitable processes. In some embodiments, the thickness of the insulating layer 140 is 200 angstroms to 2000 angstroms.

[0048] Please refer to Figure 3B. A first conductive layer 150 is formed on the insulating layer 140 and covers the first active element region TR, the second active element region DG, the capacitor region CR, and at least one correction mark region MR. In some embodiments, the first conductive layer 150 has a single-layer or multi-layer structure, and its material includes metals such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, and nickel, the above alloys, the above metal oxides, the above metal nitrides, or combinations thereof, or other conductive materials. In some embodiments, the multi-layer structure of the first conductive layer 150 may be made of the same material or different materials. In some embodiments, the method of forming the first conductive layer 150 includes sputtering, electroplating, electroless plating, physical vapor deposition, chemical vapor deposition, or other suitable processes. In some embodiments, the thickness of the first conductive layer 150 is greater than 500 Å, but the present invention is not limited thereto.

[0049] Please refer to Figure 3C. A first photoresist pattern PR1 is formed on the first conductive layer 150. The first photoresist pattern PR1 has a first sub-photoresist portion PR1A located on the first active element region TR, a fifth photoresist portion PR1C located on the second active element region DG, and a second sub-photoresist portion PR1B located on at least one correction mark region MR. Specifically, a full-layer photoresist material layer is first formed on the first conductive layer 150. Then, an exposure process is performed on the photoresist material layer using a photomask to form the first sub-photoresist portion PR1A, the fifth photoresist portion PR1C, and the second sub-photoresist portion PR1B.

[0050] Please refer to Figure 3D. The first conductive layer 150 is etched using the first photoresist pattern PR1 as an etching mask. Specifically, the first alignment member 152 is formed on at least one correction mark region MR using the second sub-photoresist PR1B as an etching mask, and the first gate portion 154 is formed on the first active element region TR using the first sub-photoresist PR1A as an etching mask. The first conductive layer 150 is etched using the fifth photoresist PR1C as an etching mask to form the third gate portion 156 on the second active element region DG. On the other hand, the first conductive layer 150 is etched to expose the insulating layer 140 on the capacitor region CR. In some embodiments, the aforementioned etching process includes a dry etching process, a wet etching process, or other suitable processes.

[0051] Please refer to Figure 3E. Using the first gate portion 154 and the first sub-photoresist portion PR1A located in the first active element region TR, and the third gate portion 156 and the fifth photoresist portion PR1C located in the second active element region DG as doping masks, an ion implantation process IP1 is performed on the semiconductor layer 130 outside the doping mask to form a first doped region 132A and a first undoped region 132B in the first semiconductor portion 132 of the first active element region TR, and to form the first doped region 132A in the third semiconductor portion 136 of the capacitor region CR.

[0052] In some embodiments, the first doped region 132A of the first semiconductor portion 132 and the first doped region 132A of the third semiconductor portion 136 comprise P-type silicon semiconductors, and the dopant selected in the ion implantation process IP1 is aluminum (Al), boron (B), gallium (Ga), or other suitable materials. In some embodiments, the first doped region 132A of the first semiconductor portion 132 and the first doped region 132A of the third semiconductor portion 136 comprise N-type silicon semiconductors, and the dopant selected in the ion implantation process IP1 is antimony (Sb), arsenic (As), phosphorus (P), or other suitable materials. In some embodiments, the ion implantation process IP1 may be referred to as a heavily doped process, and the first doped region 132A of the first semiconductor portion 132 and the first doped region 132A of the third semiconductor portion 136 may be referred to as a P+ region or an N+ region.

[0053] Please refer to Figure 3F. The removal of the first photoresist pattern PR1 includes a first sub-photoresist portion PR1A located in the first active element region TR, a fifth photoresist portion PR1C located in the second active element region DG, and a second sub-photoresist portion PR1B located in the correction mark region MR. In some embodiments, the first photoresist pattern PR1 is removed by an ashing process, a stripping process, or other suitable processes.

[0054] Since the first conductive layer 150 is used as a doping mask for the ion implantation process IP1, after the ion implantation process IP1 is completed and the first photoresist pattern PR1 is removed, the first alignment member 152 of the correction marking region MR can be used to mark the positions of the first doped region 132A, the first undoped region 132B, and the first gate portion 154.

[0055] Please refer to Figure 3G. A second conductive layer 160 is formed over the insulating layer 140, the first gate portion 154, the third gate portion 156, and the first alignment member 152, and covers the first active element region TR, the second active element region DG, and at least one correction mark region MR. The second conductive layer 160 also covers the capacitance region CR. In some embodiments, the second conductive layer 160 has a single-layer or multi-layer structure, and its material includes metals such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, and nickel, the aforementioned alloys, the aforementioned metal oxides, the aforementioned metal nitrides, or combinations thereof, or other conductive materials. In some embodiments, the multi-layer structure of the second conductive layer 160 may be made of the same material or different materials. In some embodiments, the method of forming the second conductive layer 160 includes sputtering, electroplating, electroless plating, physical vapor deposition, chemical vapor deposition, or other suitable processes. In some embodiments, the first conductive layer 150 and the second conductive layer 160 have the same material.

[0056] Please refer to Figure 3H. A second photoresist pattern PR2 is formed on the second conductive layer 160. The second photoresist pattern PR2 has a third sub-photoresist portion PR2A located in the first active element region TR, a sixth photoresist portion PR2C located in the second active element region DG, a seventh photoresist portion PR2D located in the capacitor region CR, and a fourth sub-photoresist portion PR2B located in at least one correction mark region MR. Specifically, a full-layer photoresist material layer is first formed on the second conductive layer 160. Then, an exposure process is performed on the photoresist material layer using a photomask to form the third sub-photoresist portion PR2A, the sixth photoresist portion PR2C, the seventh photoresist portion PR2D, and the fourth sub-photoresist portion PR2B.

[0057] In the first active element region TR, the third sub-photoresist portion PR2A covers a portion of the second conductive layer 160 on the first active element region TR and overlaps with a portion of the first gate portion 154.

[0058] In the second active element region DG, the sixth photoresist portion PR2C covers a portion of the second conductive layer 160 on the second active element region DG and overlaps with a portion of the third gate portion 156.

[0059] In at least one correction marking region MR, the fourth sub-photoresist portion PR2B has an opening 161 to expose a portion of the second conductive layer 160 of the at least one correction marking region MR.

[0060] In the aforementioned exposure process, the equipment and / or photomask used in the exposure process are aligned using a first alignment member 152. For example, light is shone onto the first alignment member 152, and the position of the first alignment member 152 is confirmed by the transmission and / or reflection of the light, thereby determining the exposure position of the photoresist material layer. After the exposure process, a development process is performed to remove unwanted portions of the photoresist material layer, leaving the third sub-photoresist portion PR2A located in the first active element region TR, the sixth photoresist portion PR2C located in the second active element region DG, the seventh photoresist portion PR2D located in the capacitor region CR, and the fourth sub-photoresist portion PR2B located in at least one calibration mark region MR, forming the second photoresist pattern PR2.

[0061] In this embodiment, the fourth sub-photoresist PR2B overlaps with the first alignment member 152. The position of the fourth sub-photoresist PR2B and the first alignment member 152 is measured to confirm whether the exposure process is executed accurately. For example, the relative position of the fourth sub-photoresist PR2B and the first alignment member 152 is confirmed by light transmission and / or reflection, thereby obtaining the process offset parameters of the exposure process for the third sub-photoresist PR2A, the sixth photoresist PR2C, the seventh photoresist PR2D, and the fourth sub-photoresist PR2B of the second photoresist pattern PR2. If the exposure process of the second photoresist pattern PR2 has an excessive offset, the second photoresist pattern PR2 can be removed, and the exposure process can be corrected using the previously obtained process offset parameters. A photoresist material layer is re-formed on the conductive second conductive layer 160, and then the photoresist material layer is exposed using the corrected exposure process. This method can improve the process yield.

[0062] Please refer to Figure 3I. The second conductive layer 160 is etched using the second photoresist pattern PR2 as an etching mask. Specifically, the third sub-photoresist PR2A is used as an etching mask to form a second gate portion 164 on the first active element region TR, exposing a portion of the first undoped region 132B and a portion of the first doped region 132A. A portion of the second gate portion 164 overlaps with the first gate portion 154 and the first doped region 132A. The second conductive layer 160 is etched using the sixth photoresist PR2C as an etching mask to form a fourth gate portion 166 on the second active element region DG, exposing a portion of the second semiconductor portion 134. The fourth gate portion 166 overlaps with the third gate portion 156. The second conductive layer 160 is etched using the seventh photoresist PR2D as an etching mask to form an electrode 168 on the capacitor region CR, overlapping a portion of the first doped region 132A. The second conductive layer 160 is etched using the fourth sub-photoresist PR2B as an etching mask to form a second alignment member 162 in at least one correction mark region MR. The second alignment member 162 is located around the first alignment member 152, wherein the second alignment member 162 partially overlaps with the first alignment member 152, and a through-hole V is present at the overlap of the second alignment member 162 and the first alignment member 152. In some embodiments, the aforementioned etching process includes a dry etching process, a wet etching process, or other suitable processes.

[0063] Please refer to Figure 3J. Using the second gate portion 164 and the third sub-photoresist portion PR2A located in the first active element region TR, and the fourth gate portion 166 and the sixth photoresist portion PR2C located in the second active element region DG as heavily doped masks, a heavy doping process IP2 is performed on the semiconductor layer 130 outside the heavily doped mask. Two first heavily doped regions 132C are formed in a portion of the first doped region 132A and a portion of the first undoped region 132B in the first active element region TR, and the first heavily doped regions 132C are phase-separated. Two second heavily doped regions 134A and a second undoped region 134B are formed in a portion of the second semiconductor portion 134 in the second active element region DG, and the second heavily doped regions 134A are phase-separated.

[0064] In some embodiments, the first heavily doped region 132C of the first semiconductor section 132 and the second heavily doped region 134A of the second semiconductor section 134 comprise P-type silicon semiconductors, and the dopant selected in the heavy doping process IP2 is aluminum (Al), boron (B), gallium (Ga), or other suitable materials. In some embodiments, the first heavily doped region 132C of the first semiconductor section 132 and the second heavily doped region 134A of the second semiconductor section 134 comprise N-type silicon semiconductors, and the dopant selected in the heavy doping process IP2 is antimony (Sb), arsenic (As), phosphorus (P), or other suitable materials. In some embodiments, the first heavily doped region 132C of the first semiconductor section 132 and the second heavily doped region 134A of the second semiconductor section 134 may be referred to as P+ regions or N+ regions. The first doped region 132A, the first heavily doped region 132C of the first semiconductor section 132, and the second heavily doped region 134A of the second semiconductor section 134 comprise the same dopant as the first doped region 132A in the capacitor region CR.

[0065] In some embodiments, the doping concentration of the first heavily doped region 132C is greater than or substantially equal to the doping concentration of the first doped region 132A.

[0066] In some embodiments, since a portion of the first heavily doped region 132C also receives doping from the ion implantation process IP1, a portion of the first heavily doped region 132C may include the region that has received ion implantation process IP1 (see FIG. 3E) plus heavily doped process IP2, and another portion of the first heavily doped region 132C may have only received heavily doped process IP2. In some embodiments, the doping concentration of the first heavily doped region 132C adjacent to the first doped region 132A is greater than or equal to the doping concentration of the first heavily doped region 132C adjacent to the first undoped region 132B.

[0067] Please refer to Figure 3K. An etch-back process is performed on the second gate portion 164 and the first gate portion 154 of the first active element region TR, the fourth gate portion 166 and the third gate portion 156 of the second active element region DG, and the electrode 168 of the capacitor region CR to reduce the width of the second gate portion 164 and the first gate portion 154 of the first active element region TR and expose a portion of the first doped region 132A and a portion of the first undoped region 132B located in the first active element region TR; to reduce the width of the fourth gate portion 166 and the third gate portion 156 of the second active element region DG and expose a portion of the second undoped region 134B located in the second active element region DG; and to reduce the width of the electrode 168 of the capacitor region CR.

[0068] In some embodiments, the width and thickness of the third sub-photoresist portion PR2A, the fourth sub-photoresist portion PR2B, the sixth photoresist portion PR2C, and the seventh photoresist portion PR2D of the second photoresist pattern PR2 are also reduced during the etch-back process.

[0069] Please refer to Figure 3L. Using the second gate portion 164 located in the first active element region TR and the fourth gate portion 166 located in the second active element region DG as light doping masks, a light doping process IP3 is performed on the semiconductor layer 130 outside the light doping mask to form a first light doped region 132D in a portion of the first undoped region 132B in the first active element region TR, and two second light doped regions 134C are formed in a portion of the second undoped region 134B in the second active element region DG, wherein the second light doped regions 134C are phase-separated.

[0070] In some embodiments, the light doping process IP3 is performed after the removal of the third sub-photoresist portion PR2A, the fourth sub-photoresist portion PR2B, the sixth photoresist portion PR2C, and the seventh photoresist portion PR2D of the second photoresist pattern PR2, but the present invention is not limited thereto.

[0071] In some embodiments, the first lightly doped region 132D of the first semiconductor portion 132 and the second lightly doped region 134C of the second semiconductor portion 134 comprise P-type silicon semiconductors, and the dopant selected in the light doping process IP3 is aluminum (Al), boron (B), gallium (Ga), or other suitable materials. In some embodiments, the first lightly doped region 132D of the first semiconductor portion 132 and the second lightly doped region 134C of the second semiconductor portion 134 comprise N-type silicon semiconductors, and the dopant selected in the light doping process IP3 is antimony (Sb), arsenic (As), phosphorus (P), or other suitable materials. In some embodiments, the first lightly doped region 132D of the first semiconductor portion 132 and the second lightly doped region 134C of the second semiconductor portion 134 may be referred to as a P-region or an N-region. The first doped region 132A, the first heavily doped region 132C, and the first lightly doped region 132D in the first semiconductor section 132, as well as the second heavily doped region 134A and the second lightly doped region 134C in the second semiconductor section 134, and the first doped region 132A in the capacitor region CR include the same dopants.

[0072] In some embodiments, the doping concentration of the first doped region 132A is greater than the doping concentration of the first lightly doped region 132D. In some embodiments, the doping concentration of the first heavily doped region 132C is greater than or substantially equal to the doping concentration of the first doped region 132A.

[0073] Please refer to Figure 3M. The removal of the second photoresist pattern PR2 includes a third sub-photoresist portion PR2A located in the first active element region TR, a sixth photoresist portion PR2C located in the second active element region DG, a seventh photoresist portion PR2D located in the capacitor region CR, and a fourth sub-photoresist portion PR2B located in the correction mark region MR. In some embodiments, the second photoresist pattern PR2 is removed by an ashing process, a stripping process, or other suitable processes.

[0074] In this embodiment, the channel length and its variation in the protrusion gate channel bridge thin film transistor (PGCB TFT) of the first active element region TR are important parameters for evaluating the performance of this transistor. The smaller the variation in this channel length, the more stable the quality of this transistor.

[0075] In the process described in Figures 3H to 3M of this embodiment, the variation in channel length depends on two variables. One is the variation in the length of the first undoped region 132B. The other is the alignment variation during the alignment of the second conductive layer 160.

[0076] In this embodiment, the maximum offset of the length of the first undoped region 132B is 0.3 micrometers. The maximum offset of the second conductive layer 160 during alignment is related to the alignment of the second photoresist pattern PR2. In this embodiment, the position of the second photoresist pattern PR2 can be corrected according to the first alignment member 152, and the maximum offset of the second photoresist pattern PR2, that is, the maximum offset between the geometric center of the fourth sub-photoresist portion PR2B and the geometric center of the first alignment member 152, is 0.4 micrometers.

[0077] Therefore, the channel length variation of the gate-extended bridging thin-film transistor in the first active element region TR is the square of the maximum offset of the first undoped region 132B plus the square of the maximum offset during alignment of the second conductive layer 160, i.e., 0.32 + 0.42 = 0.25. Therefore, the maximum offset of the channel length of the gate-extended bridging thin-film transistor in the first active element region TR is the square root of the variation, i.e., 0.5 micrometers.

[0078] Since only one alignment correction is required during the process, namely, correcting the relative position of the second photoresist pattern PR2 and the first alignment member 152, the alignment misalignment problem caused by the superposition of process variations in the lithography process can be effectively reduced. Therefore, the relative position between the first gate portion 154, the second gate portion 164 and the first undoped region 132B will only be affected by the process variations when forming the second photoresist pattern PR2, and will not be affected by the process variations when forming the first photoresist pattern PR1.

[0079] Please refer to Figure 3N. An interlayer dielectric layer 170 is formed over the second gate portion 164 and the first gate portion 154 of the first active element region TR, the fourth gate portion 166 and the third gate portion 156 of the second active element region DG, the electrode 168 of the capacitor region CR, and the second alignment member 162 and the first alignment member 152 of at least one correction mark region MR. In this embodiment, the interlayer dielectric layer 170 also covers the insulating layer 140. In some embodiments, the interlayer dielectric layer 170 may not cover the second alignment member 162 and the first alignment member 152 of the correction mark region MR.

[0080] In some embodiments, the interlayer dielectric layer 170 has a single-layer or multi-layer structure, and its material includes silicon oxide, silicon nitride, silicon oxynitride, organic insulating materials, other suitable materials, or combinations thereof. In some embodiments, the multilayer structure of the interlayer dielectric layer 170 may be made of the same material or different materials. In some embodiments, the method of forming the interlayer dielectric layer 170 includes physical vapor deposition, chemical vapor deposition, atomic layer deposition, coating, or other suitable processes.

[0081] Please refer to Figure 30. A first source 182, a first drain 184, a second source 186, and a second drain 188 are formed on the insulating layer 140 and the interlayer dielectric layer 170 to electrically connect to the first heavily doped region 132C of the first active device region TR and the second heavily doped region 134A of the second active device region DG, respectively. Specifically, in some embodiments, a plurality of vias are formed through the interlayer dielectric layer 170 and the insulating layer 140 by an etching process. These vias expose the first heavily doped region 132C of the first active device region TR and the second heavily doped region 134A of the second active device region DG. These vias correspond to the positions of the first source 182, the first drain 184, the second source 186, and the second drain 188, respectively. In some embodiments, the first source 182, the first drain 184, the second source 186, and the second drain 188 have a single-layer or multi-layer structure, and their materials include metals such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, and nickel, the aforementioned alloys, the aforementioned metal oxides, the aforementioned metal nitrides, or combinations thereof, or other conductive materials. In some embodiments, the multi-layer structure of the first source 182, the first drain 184, the second source 186, and the second drain 188 may be made of the same material or different materials. In some embodiments, the method of forming the first source 182, the first drain 184, the second source 186, and the second drain 188 includes sputtering, electroplating, electroless plating, physical vapor deposition, chemical vapor deposition, or other suitable processes.

[0082] A self-emissive element 190 is formed and electrically connected to the first source 182 of the first active element region TR. In some embodiments, the self-emissive element 190 may also be located on the first drain 184, but the present invention is not limited thereto. In some embodiments, the self-emissive element 190 may be an inorganic self-emissive element, an organic self-emissive element, or other suitable element. At least one control element electrically connected to the self-emissive element 190 may be referred to as a driving element, a light-emitting control element, or other element.

[0083] Figure 4A is a top view of a correction mark area according to one embodiment of the present invention. Figure 4B is a top view of a correction mark area according to another embodiment of the present invention. Figure 5A is a cross-sectional view of the correction mark area of ​​Figure 4A. Figure 5B is a cross-sectional view of the correction mark area of ​​Figure 4B.

[0084] Please refer to Figures 4A and 5A simultaneously. Figures 4A and 5A are cross-sectional and top views, respectively, of the fourth sub-photoresist portion PR2B, the second conductive layer 160, and the first alignment member 152 in the correction mark region MR in Figure 3H. In this embodiment, the fourth sub-photoresist portion PR2B partially covers the first alignment member 152 to position other portions of the second photoresist pattern PR2, including the third sub-photoresist portion PR2A located in the first active element region TR, the sixth photoresist portion PR2C located in the second active element region DG, and the seventh photoresist portion PR2D located in the capacitor region CR.

[0085] In other embodiments, the fourth sub-photoresist portion PR2B of the correction mark region MR can have different configuration relationships. Please refer to Figures 4B and 5B simultaneously. Figures 4A and 5A are the fourth sub-photoresist portion of the correction mark region MR in Figure 3H. In this embodiment, the fourth sub-photoresist portion PR2B surrounds but does not cover the first alignment member 152, thereby positioning other parts of the second photoresist pattern PR2, including the third sub-photoresist portion PR2A located in the first active element region TR, the sixth photoresist portion PR2C located in the second active element region DG, and the seventh photoresist portion PR2D located in the capacitor region CR.

[0086] Figure 6 shows the overlay distribution of the first gate portion and the second gate portion after the first alignment member is installed. As shown in Figure 6, by setting the first alignment member 152, the overlay offset of the first gate portion 154 and the second gate portion 164 is less than + / -0.2μm, indicating that the first alignment member 152 helps to determine the position of the second gate portion 164.

[0087] Figure 7 shows the IV curves of the thin-film transistor fabricated according to an embodiment of the present invention at different voltages. As shown in Figure 7, the relationship between gate voltage and drain current is shown when different drain voltages (Vd) are applied to the thin-film transistor (e.g., the thin-film transistor in the first active element region TR) obtained by the manufacturing method provided in the embodiment of the present invention. As can be seen from Figure 7, the thin-film transistor obtained by the manufacturing method provided in the embodiment of the present invention has good electrical properties.

[0088] In summary, the present invention can avoid the problem of misalignment between the first gate portion 154, the second gate portion 164 and the first undoped region 132B due to excessive process variation by setting the first alignment member 152.

[0089] 10: Display device 100:Substrate 110: Light-shielding layer 112: First shading section 114: Second shading section 116: Third shading section 120: Buffer layer 130: Semiconductor layer 132: First Semiconductor Division 132A: First doped region 132B: First undoped region 132C: First doped region 132D: First lightly doped region 134: Second Semiconductor Division 134A: Second doped region 134B: Second undoped region 134C: Second lightly doped region 136: Third Semiconductor Division 140: Insulation layer 150: First conductive layer 152: First alignment component 154: First gate section 156: Third gate section 160: Second conductive layer 161: Opening 162: Second alignment component 164: Second gate section 166: Fourth gate section 168: Electrode 170: Interlayer dielectric layer 182: First Source 184: First Drain 186: Second Source 188: Second Drain 190: Self-illuminating component AA: Display area CR: Capacitor area DG: Second Active Component Region IP1: Ion Implantation Process IP2: Heavily Doped Process IP3: Lightly Doped Process MR: Correction Marker Area PA: Surrounding Area TR: First Active Component Region PR1: First photoresist pattern PR1A: First Sub-photoresist Section PR1B: Second Sub-photoresist Section PR1C: Fifth photoresist section PR2: Second photoresist pattern PR2A: Third Sub-photoresist Section PR2B: Fourth Sub-photoresist Section PR2C: Sixth photoresist section PR2D: Seventh photoresist section PXL: sub-pixel area V: Through hole

Claims

1. A method for manufacturing an active component substrate, comprising: A substrate is provided having a display area and a peripheral area outside the display area. The display area has at least one sub-pixel area, wherein the sub-pixel area has a first active element area, and the peripheral area has at least one correction mark area. A light-shielding layer is formed on the substrate, the light-shielding layer having a first light-shielding portion located in the first active element area. A buffer layer is formed on the substrate and covers the first light-shielding portion. A semiconductor layer is formed on the buffer layer of the substrate, and the semiconductor layer has a first semiconductor portion located in the first active element area. An insulating layer is formed on the buffer layer and the semiconductor layer and covers the first active element area and the at least one correction mark area. A first conductive layer is formed on the insulating layer and covers the first active element area and the at least one correction mark area. A first photoresist pattern is formed on the first conductive layer, wherein the first photoresist pattern has a first sub-photoresist portion and a second sub-photoresist portion located in the first active element area and the at least one correction mark area, respectively. The first conductive layer is etched using the first photoresist pattern as an etching mask to form a first alignment member in the at least one correction mark region and a first gate portion in the first active element region; the first gate portion and the first sub-photoresist portion located in the first active element region are used as doping masks, and an ion implantation process is performed on the semiconductor layer outside the doping mask to form a first doped region and a first undoped region in the first semiconductor portion of the first active element region, and the first photoresist pattern is removed; a second conductive layer is formed on the insulating layer and the first alignment member and the first gate portion, covering the first active element region and the at least one correction mark region; A second photoresist pattern is formed on the second conductive layer, wherein the second photoresist pattern has a third sub-photoresist portion and a fourth sub-photoresist portion located on the first active element region and the at least one correction mark region, respectively. The third sub-photoresist portion covers a portion of the second conductive layer on the first active element region and overlaps with a portion of the first gate portion. The fourth sub-photoresist portion has an opening to expose a portion of the second conductive layer in the at least one correction mark region. The second conductive layer is etched using the second photoresist pattern as an etching mask to form a second alignment member on the at least one correction mark region and a second gate portion on the first active element region, exposing a portion of the first undoped region and a portion of the first doped region, wherein the second alignment member is located around the first alignment member, and a portion of the second gate portion overlaps with the first gate portion and the first doped region. Using the second gate portion and the third sub-photoresist portion located in the first active element region as a heavily doped mask, a heavy doping process is performed on the semiconductor layer outside the heavily doped mask to form two first heavily doped regions in a portion of the first doped region and a portion of the first undoped region in the first active element region, and the first heavily doped regions are separated from each other.An etch-back process is performed on the second gate portion and the first gate portion to reduce their widths and expose a portion of the first doped region and a portion of the first undoped region located in the first active device region, and the second photoresist pattern is removed; using the second gate portion located in the first active device region as a lightly doped mask, a light doping process is performed on the semiconductor layer outside the lightly doped mask to form a first lightly doped region in the portion of the first undoped region in the first active device region; and a first source and a first drain are formed on the insulating layer to be electrically connected to the first heavily doped regions in the first active device region, respectively.

2. The method for manufacturing an active element substrate as described in claim 1, wherein, The sub-pixel region further includes a second active element region, the light-shielding layer further includes a second light-shielding portion located in the second active element region and the buffer layer further covers the second light-shielding portion, the semiconductor layer further includes a second semiconductor portion located in the second active element region and the insulating layer further covers the second active element region, and the method further includes: forming the first conductive layer on the insulating layer and covering the second active element region; forming a fifth photoresist portion of the first photoresist pattern on the first conductive layer and located in the second active element region; etching the first conductive layer using the fifth photoresist portion as an etching mask to form a third gate portion on the second active element region; forming the second conductive layer on the insulating layer and the third gate portion and covering the second active element region; forming a sixth photoresist portion of the second photoresist pattern on the second conductive layer and located in the second active element region; The second conductive layer is etched using the sixth photoresist portion as an etching mask to form a fourth gate portion on the second active device region and expose a portion of the second semiconductor portion, wherein the fourth gate portion and the third gate portion overlap; the fourth gate portion and the sixth photoresist portion located in the second active device region are used as the heavily doped mask, and the heavily doped process is performed on the second semiconductor portion outside the heavily doped mask to form two second heavily doped regions and a second undoped region in a portion of the second semiconductor portion in the second active device region, wherein the second heavily doped regions are separated from each other; the etch-back process is performed on the fourth gate portion and the third gate portion to reduce the width of the fourth gate portion and the third gate portion and expose a portion of the second undoped region located in the second active device region; Using the fourth gate portion located in the second active element region as the lightly doped mask, the light doping process is performed on the semiconductor layer outside the lightly doped mask to form two second lightly doped regions in a portion of the second undoped region of the second active element region, and the second photoresist pattern is removed, wherein the second lightly doped regions are separated from each other; and a second source and a second drain are formed on the insulating layer to be electrically connected to the second heavily doped regions of the second active element region, respectively.

3. A method for manufacturing an active element substrate as described in claim 2, wherein, The sub-pixel region further includes a capacitor region, the light-shielding layer further includes a third light-shielding portion located in the capacitor region and the buffer layer further covers the third light-shielding portion, the semiconductor layer further includes a third semiconductor portion located in the capacitor region and the insulating layer further covers the capacitor region, and the method further includes: forming the first conductive layer on the insulating layer and covering the capacitor region; etching the first conductive layer to expose the insulating layer on the capacitor region, and performing the ion implantation process on the third semiconductor portion to form the first doped region in the third semiconductor portion of the capacitor region; forming the second conductive layer on the insulating layer and covering the capacitor region; forming a seventh photoresist portion, one of the second photoresist patterns, on the second conductive layer and located on the capacitor region; and using the seventh photoresist portion as an etching mask to etch the second conductive layer to form an electrode on the capacitor region and overlapping a portion of the first doped region.

4. A method for manufacturing an active element substrate as described in claim 3, wherein, The method further includes performing the etch-back process on the electrode to reduce the width of the electrode.

5. A method for manufacturing an active element substrate as described in claim 1, wherein, The second alignment member partially overlaps with the first alignment member, and there is a through hole at the overlap between the second alignment member and the first alignment member.

6. A display device, comprising: A substrate having a display area and a peripheral area outside the display area, the display area having at least one sub-pixel area, wherein the sub-pixel area has a first active element area, and the peripheral area has at least one correction mark area; a light-shielding layer disposed on the substrate, and having a first light-shielding portion located in the first active element area; a buffer layer disposed on the substrate and covering the first light-shielding portion; a semiconductor layer disposed on the buffer layer of the substrate, and having a first semiconductor portion located in the first active element area, wherein the first semiconductor portion has a first doped region, a first undoped region, a first lightly doped region, and two first heavily doped regions, the first doped region and the first undoped region and the first lightly doped region being located between the first heavily doped regions, the first doped region being located between one of the first undoped region and the first heavily doped regions, and the first lightly doped region being located between the first undoped region and the other of the first heavily doped regions; An insulating layer is disposed on the buffer layer and the semiconductor layer and covers the first active element region and the at least one calibration mark region; a first conductive layer is disposed on the insulating layer and has a first alignment member located on the at least one calibration mark region and a first gate portion located on the first active element region, wherein the first gate portion overlaps with the first undoped region; a second conductive layer is disposed on the insulating layer and has a second alignment member located on the at least one calibration mark region and a second gate portion located on the first active element region, wherein the second alignment member is located around the first alignment member, and a portion of the second gate portion overlaps with the first gate portion and the first doped region, wherein the first gate portion and the second gate portion constitute a first gate; and a first source and a first drain are disposed on the insulating layer and electrically connected to the first heavily doped regions of the first active element region, respectively.

7. The display device as claimed in claim 6, wherein, The sub-pixel region further includes a second active element region; the light-shielding layer further includes a second light-shielding portion located in the second active element region and the buffer layer further covers the second light-shielding portion; the semiconductor layer further includes a second semiconductor portion located on the second active element region and the insulating layer further covers the second active element region, wherein the second semiconductor portion has a second undoped region, two second lightly doped regions and two second heavily doped regions, the second undoped region and the second lightly doped regions are located between the second heavily doped regions, one of the second lightly doped regions is located between the second undoped region and one of the second heavily doped regions, and the other of the second lightly doped regions is located between the second undoped region and the other of the second heavily doped regions; The first conductive layer further includes a third gate portion located on the second active element region; and the second conductive layer further includes a fourth gate portion located on the second active element region, and the fourth gate portion and the third gate portion overlap with the second undoped region; and the second active element region further includes a second source and a second drain on the insulating layer to be electrically connected to the second heavily doped regions of the second active element region, respectively.

8. The display device as claimed in claim 7, wherein, The sub-pixel region further includes a capacitor region, the light-shielding layer further includes a third light-shielding portion located in the capacitor region and the buffer layer further covers the third light-shielding portion; the semiconductor layer further includes a third semiconductor portion located in the capacitor region and the insulating layer further covers the capacitor region, wherein the third semiconductor portion has the first doped region; the second conductive layer further includes an electrode located on the capacitor region and overlaps with a portion of the first doped region.

9. The display device as claimed in claim 6, wherein, The second alignment member partially overlaps with the first alignment member, and there is a through hole at the overlap between the second alignment member and the first alignment member.

10. The display device as claimed in claim 6 further includes at least one self-emissive element disposed on the substrate and electrically connected to the first drain or the first source on the first active element region.

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